0 R XCR3064XL 64 Macrocell CPLD DS017 (v1.6) January 8, 2002 0 14 Product Specification Features Description • Lowest power 64 macrocell CPLD • 6.0 ns pin-to-pin logic delays • System frequencies up to 145 MHz • 64 macrocells with 1,500 usable gates The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz. • Available in small footprint packages • 44-pin PLCC (36 user I/O pins) - 44-pin VQFP (36 user I/O pins) - 48-ball CS BGA (40 user I/O pins) - 56-ball CP BGA (48 user I/O pins) - 100-pin VQFP (68 user I/O pins) TotalCMOS Design Technique for Fast Zero Power Optimized for 3.3V systems - Ultra-low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power™ (FZP) CMOS design technology Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3064XL TotalCMOS CPLD (data taken with four resetable up/down, 16-bit counters at 3.3V, 25°C). 35.0 Advanced system features 30.0 - In-system programming - Input registers - Predictable timing model - Up to 23 available clocks per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Typical ICC (mA) • - 25.0 20.0 15.0 10.0 5.0 • Fast ISP programming times • Port Enable pin for dual function of JTAG ISP pins • 2.7V to 3.6V supply voltage at industrial temperature range • Programmable slew rate control per macrocell • Security bit prevents unauthorized access • Refer to XPLA3 family data sheet (DS012) for architecture description 0.0 0 20 40 60 80 100 120 140 Frequency (MHz) DS017_01_102401 Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C Table 1: ICC vs. Frequency (VCC = 3.3V, 25°C) Frequency (MHz) 0 1 5 10 20 40 60 80 100 120 140 Typical ICC (mA) 0 0.2 1.0 2.0 3.9 7.6 11.3 14.8 18.5 22.1 25.6 © 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS017 (v1.6) January 8, 2002 Product Specification www.xilinx.com 1-800-255-7778 1 R XCR3064XL 64 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions(1) Symbol Parameter Test Conditions Min. Max. Unit 2.4 - V - 0.4 V VOH(2) Output High voltage IOH = –8 mA VOL Output Low voltage for 3.3V outputs IOL = 8 mA IIL Input leakage current VIN = GND or VCC –10 10 µA IIH I/O High-Z leakage current VIN = GND or VCC –10 10 µA ICCSB Standby current VCC = 3.6V - 100 µA ICC Dynamic current(3,4) f = 1 MHz - 0.5 mA f = 50 MHz - 15 mA CIN Input pin capacitance(5) f = 1 MHz - 8 pF CCLK Clock input capacitance(5) f = 1 MHz - 12 pF CI/O I/O pin capacitance (5) f = 1 MHz - 10 pF Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. See Table 1, Figure 1 for typical values. 4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 5. Typical values, not tested. 100 90 IOL (3.3V) 80 70 mA 60 50 IOH (3.3V) 40 30 IOH (2.7V) 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts DS012_10_041901 Figure 2: Typical I/V Curve for the XPLA3 Family 2 www.xilinx.com 1-800-255-7778 DS017 (v1.6) January 8, 2002 Product Specification R XCR3064XL 64 Macrocell CPLD AC Electrical Characteristics Over Recommended Operating Conditions(1,2) -6 Symbol -10 Min. Max. Min. Max. Min. Max. Unit - 5.5 - 7.0 - 9.1 ns - 6.0 - 7.5 - 10.0 ns - 4.0 - 5.0 - 6.5 ns Setup time (fast input register) 2.5 - 2.5 - 3.0 - ns Setup time (single p-term) 3.5 - 4.3 - 5.4 - ns TSU2 Setup time (OR array) 4.0 - 4.8 - 6.3 - ns TH(4) Hold time 0 - 0 - 0 - ns TWLH(4) Global Clock pulse width (High or Low) 2.5 - 3.0 - 4.0 - ns TtPLH(4) P-term clock pulse width 4.0 - 5.0 - 6.0 - ns Input rise time - 20 - 20 - 20 ns Input fall time - 20 - 20 - 20 ns TPD1 Parameter -7 Propagation delay time (single p-term) array)(3) TPD2 Propagation delay time (OR TCO Clock to output (global synchronous pin clock) TSUF TSU1 TR TL (4) (4) (4) fSYSTEM (4) TCONFIG TINIT(4) TPOE(4) TPOD(4) TPCO(4) TPAO (4) (4) Maximum system frequency - 145 - 119 - 95 MHz time(5) - 60 - 60 - 60 µs ISP initialization time - 60 - 60 - 60 µs P-term OE to output enabled - 7.5 - 9.3 - 11.2 ns P-term OE to output disabled(6) - 7.5 - 9.3 - 11.2 ns P-term clock to output - 6.5 - 8.3 - 10.7 ns P-term set/reset to output valid - 8.0 - 9.3 - 11.2 ns Configuration Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 6 mA at 3.6V. 6. Output CL = 5 pF. DS017 (v1.6) January 8, 2002 Product Specification www.xilinx.com 1-800-255-7778 3 R XCR3064XL 64 Macrocell CPLD Internal Timing Parameters(2) -6 Symbol Parameter -7 -10 Min. Max. Min. Max. Min. Max. Unit Buffer Delays TIN Input buffer delay - 1.3 - 1.6 - 2.2 ns TFIN Fast Input buffer delay - 2.3 - 3.0 - 3.1 ns TGCK Global Clock buffer delay - 0.8 - 1.0 - 1.3 ns TOUT Output buffer delay - 2.2 - 2.7 - 3.6 ns TEN Output buffer enable/disable delay - 4.2 - 5.0 - 5.7 ns - 1.3 - 1.6 - 2.0 Internal Register and Combinatorial Delays TLDI Latch transparent delay TSUI Register setup time 1.0 - 1.0 - 1.2 - ns THI Register hold time 0.3 - 0.5 - 0.7 - ns TECSU Register clock enable setup time 2.0 - 2.5 - 3.0 - ns TECHO Register clock enable hold time 3.0 - 4.5 - 5.5 - ns TCOI Register clock to output delay - 1.0 - 1.3 - 1.6 ns TAOI Register async. S/R to output delay - 2.5 - 2.3 - 2.1 ns TRAI Register async. recovery - 4.0 - 5.0 - 6.0 ns TLOGI1 Internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns TLOGI2 Internal logic delay (PLA OR term) - 2.5 - 3.2 - 4.2 ns - 2.4 - 2.9 - 3.5 ns Feedback Delays TF ZIA delay Time Adders TLOGI3 Fold-back NAND delay - 6.0 - 7.5 - 9.5 ns TUDA Universal delay - 1.5 - 2.0 - 2.5 ns TSLEW Slew rate limited delay - 4.0 - 5.0 - 6.0 ns Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA3 family data sheet (DS012) for timing model. 4 www.xilinx.com 1-800-255-7778 DS017 (v1.6) January 8, 2002 Product Specification R XCR3064XL 64 Macrocell CPLD Switching Characteristics VCC S1 Component R1 R2 C1 R1 Values 390Ω 390Ω 35 pF VIN VOUT R2 Measurement TPOE (High) TPOE (Low) TP C1 S1 Open Closed Closed S2 Closed Open Closed Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV. S2 DS017_03_102401 Figure 3: AC Load Circuit 5.6 +3.0V 90% 5.5 (ns) 5.4 10% 0V 5.3 TR 5.2 1.5 ns TL 1.5 ns 5.1 5.0 4.9 1 2 4 8 16 Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS017_05_042800 Number of Adjacent Outputs Switching DS017_04_042800 Figure 5: Voltage Waveform Figure 4: Derating Curve for TPD2 DS017 (v1.6) January 8, 2002 Product Specification www.xilinx.com 1-800-255-7778 5 R XCR3064XL 64 Macrocell CPLD Pin Descriptions Table 3: XCR3064XL I/O Pins Function MacroBlock cell PC44 VQ44 CS48 CP56 VQ100 Table 2: XCR3064XL User I/O Pins Total User I/O Pins PC44 VQ44 CS48 CP56 VQ100 2 15 12 6 D1 F1 13 36 36 40 48 68 2 16 - - - - 14 3 1 32(1) 26(1) E5(1) F10(1) 62(1) 3 2 31 25 E7 G8 61 3 3 - - - - 60 3 4 29 23 F7 H10 58 Table 3: XCR3064XL I/O Pins Function MacroBlock cell PC44 VQ44 CS48 CP56 VQ100 6 1 1 41 35 C5 C8 85 3 5 - - - - 57 1 2 40 34 A6 A8 84 3 6 - - - - 56 1 3 - - - - 83 3 7 - - F6 K8 54 1 4 - - - A9 81 3 8 - - - K10 52 1 5 - - - A5 80 3 9 28 22 G7 K9 48 1 6 - - A7 A10 79 3 10 27 21 G6 J10 47 1 7 - - - - 76 3 11 26 20 F5 H8 46 1 8 39 33 B6 B10 75 3 12 25 19 G5 H7 45 1 9 38(1) 32(1) B7(1) C10(1) 73(1) 3 13 24 18 F4 H6 44 1 10 37 31 D4 D8 71 3 14 - - - - 42 1 11 36 30 C6 E8 69 3 15 - - - K7 41 1 12 - - - - 68 3 16 - - - - 40 1 13 - - - - 67 4 1 13(1) 7(1) D2(1) G1(1) 15(1) 1 14 34 28 D6 F8 65 4 2 14 8 E1 F3 16 1 15 33 27 D7 E10 64 4 3 - - - - 17 1 16 - - - - 63 4 4 16 10 F1 G3 19 2 1 4 42 A2 C4 92 4 5 17 11 G1 J1 20 2 2 5 43 A1 C3 93 4 6 - - - - 21 2 3 6 44 C4 A1 94 4 7 - - - - 23 2 4 - - - - 96 4 8 - - - K1 25 2 5 - - - B1 97 4 9 18 12 E4 K4 29 2 6 - - - - 98 4 10 19 13 F2 K2 30 2 7 - - - A2 99 4 11 20 14 G2 K3 31 2 8 - - B2 A3 100 4 12 21 15 F3 H3 32 2 9 7(1) 1(1) B1(1) C1(1) 4(1) 4 13 - - G3 H4 33 2 10 8 2 C2 D1 6 4 14 - - - - 35 2 11 9 3 C1 D3 8 4 15 - - - K5 36 2 12 - - - - 9 4 16 - - - - 37 2 13 - - - - 10 2 14 11 5 D3 E3 12 Notes: 1. JTAG pins www.xilinx.com 1-800-255-7778 DS017 (v1.6) January 8, 2002 Product Specification R XCR3064XL 64 Macrocell CPLD Table 4: XCR3064XL Global, JTAG, Port Enable, Power, and No connect Pins Pin Type PC44 VQ44 CS48 CP56 VQ100 IN0 / CLK0 2 40 A3 C5 90 IN1 / CLK1 1 39 B4 C6 89 IN2 / CLK2 44 38 A4 C7 88 IN3 / CLK3 43 37 B5 A6 87 TCK 32 26 E5 F10 62 TDI 7 1 B1 C1 4 TDO 38 32 B7 C10 73 TMS 13 7 D2 G1 15 PORT_EN 10(1) 4(1) C3(1) E1(1) 11(1) VCC 3, 15, 23, 35 9, 17, 29, 41 B3, C7, E2, G4 A4, D10, H1, H5 3, 18, 34, 39, 51, 66, 82, 91 GND 22, 30, 42 16, 24, 36 A5, E3, E6 A7, G10, K6 26, 38, 43, 59, 74, 86, 95 No Connects - - - - 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for more information. DS017 (v1.6) January 8, 2002 Product Specification www.xilinx.com 1-800-255-7778 7 R XCR3064XL 64 Macrocell CPLD Ordering Information Example: XCR3064XL -7 VQ 44 C Device Type Temperature Range Number of Pins Speed Grade Package Type Device Ordering Options Speed Package Temperature -10 10 ns pin-to-pin delay PC44 44-pin Plastic Leaded Chip Carrier C = Commercial TA = 0°C to + 70°C VCC = 3.0V to 3.6V -7 7.5 ns pin-to-pin delay VQ44 44-pin Very Thin Quad Flat Pack I = Industrial TA = –40°C to + 85°C VCC = 2.7V to 3.6V -6 6 ns pin-to-pin delay CS48 48-ball Chip Scale Package CP56 56-ball Chip Scale Package VQ100 100-pin Very Thin Quad Flat Package Component Availability Pins 100 56 48 44 44 Type Plastic VQFP Plastic BGA Plastic BGA Plastic VQFP Plastic PLCC Code VQ100 CP56 CS48 VQ44 PC44 -6 C C C C C -7, -10 C,I C,I C,I C,I C,I XCR3064XL 8 www.xilinx.com 1-800-255-7778 DS017 (v1.6) January 8, 2002 Product Specification R XCR3064XL 64 Macrocell CPLD Revision History The following table shows the revision history for this document.. Date Version 06/01/00 1.0 Initial Xilinx release. 08/30/00 1.1 Added 48-ball CS BGA package. 11/18/00 1.2 Updated to full production data sheet; corrected note in Table 4 to read: "port enable pin is brought High". 12/08/00 1.3 Added PC44 package. 04/11/01 1.4 Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. 04/19/01 1.5 Updated Typical I/V curve, Figure 2: added voltage levels. 01/08/02 1.6 Moved ICC vs. Freq Figure 1 and Table 1 to page 1. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TSUF and TFIN spec to match software timing. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement. Updated note 5 in AC Characteristics table lowering typical current draw during configuration. DS017 (v1.6) January 8, 2002 Product Specification Revision www.xilinx.com 1-800-255-7778 9