TI ADS4449IZCRT

ADS4449
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SBAS603 – APRIL 2013
Quad-Channel, 14-Bit, 250-MSPS, Low-Power ADC
Check for Samples: ADS4449
FEATURES
DESCRIPTION
•
•
•
•
The ADS4449 is a high-linearity, quad-channel, 14bit, 250-MSPS, analog-to-digital converter (ADC).
The four ADC channels are separated into two blocks
with two ADCs each. Designed for low power
consumption and high spurious-free dynamic range
(SFDR), the device has low-noise performance and
outstanding SFDR over a large input frequency
range.
1
2
•
•
•
Quad Channel
14-Bit Resolution
Maximum Sampling Data Rate: 250 MSPS
Power Dissipation:
– 365 mW per Channel
Spectral Performance at 170-MHz IF (typ):
– SNR: 69 dBFS
– SFDR: 86 dBc
DDR LVDS Digital Output Interface
Package: 144-Pin BGA (10-mm × 10-mm)
APPLICATIONS
•
•
•
•
•
Multi-Carrier GSM Cellular Infrastructure Base
Stations
RADAR and Smart Antenna Arrays
Multi-Carrier Multi-Mode Cellular Infrastructure
Base Stations
Active Antenna Arrays for Wireless
Infrastructures
Communications Test Equipment
0
DAB0P, DAB0M or
OVRABP, OVRABM
FIN = 170 MHz
SFDR = 89 dBc
SNR = 69 dBFS
SINAD = 68.9 dBFS
THD = 85 dBc
−20
14-Bit
ADC
AINP,
AINM
14
Digital
Block
CLKOUTABP,
CLKOUTABM
14-Bit
ADC
BINP,
BINM
DAB[13:1]P,
DAB[13:1]M
Amplitude (dB)
−40
Output
Formatter
CLKINP,
CLKINM
DDR
LVDS
−60
CINP,
CINM
14-Bit
ADC
DINP,
DINM
14-Bit
ADC
−80
DCD0P, DCD0M or
OVRCDP, OVRCDM
Digital
Block
14
DCD[13:1]P,
DCD[13:1]M
−100
VCM
Configuration Registers
Figure 1. Spectrum For 170-MHz Input Frequency
PDN
G005
SNRB
125
SDATA
100
SDOUT
50
75
Frequency (MHz)
SEN
25
SCLK
0
RESET
−120
CLKOUTCDP,
CLKOUTCDM
Common
Mode
Figure 2. Basic Block Diagram
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ADS4449
SBAS603 – APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE AND ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED TEMPERATURE
RANGE
ADS4449
BGA-144
ZCR
–40°C to +85°C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage range
Voltage between
Voltage applied to input pins
Temperature
VALUE
UNIT
AVDD33
–0.3 to +3.6
V
AVDD
–0.3 to +2.1
V
DRVDD
–0.3 to +2.1
V
AVSS and DRVSS
–0.3 to +0.3
V
AVDD and DRVDD
–2.4 to +2.4
V
AVDD33 and DRVDD
–2.4 to +3.9
V
AVDD33 and AVDD
–2.4 to +3.9
V
XINP, XINM
–0.3 to minimum (1.9, AVDD + 0.3)
V
CLKP, CLKM (2)
–0.3 to minimum (1.9, AVDD + 0.3)
V
RESET, SCLK, SDATA, SEN, PDN
–0.3 to +3.9
V
Operating free-air, TA
–40 to +85
°C
Operating junction, TJ
Storage, Tstg
Electrostatic discharge (ESD)
rating
(1)
(2)
2
Human body model (HBM)
+150
°C
–65 to +150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKM is less than
| 0.3 V |). This recommendation prevents the ESD protection diodes at the clock input pins from turning on.
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SBAS603 – APRIL 2013
THERMAL INFORMATION
ADS4449
THERMAL METRIC (1)
ZCR (BGA)
UNITS
144 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
5.1
θJB
Junction-to-board thermal resistance
12.6
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
12.4
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
35.9
°C/W
SPACER
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
1.8
1.9
2.0
V
1.7
1.8
2.0
V
SUPPLIES
AVDD33
AVDD
Supply voltage
DRVDD
ANALOG INPUTS
Differential input voltage range
2
Input common-mode voltage
VCM ± 0.025
Analog input common-mode current (per input pin of each channel)
V
1.5
VCM current capability
Maximum analog input frequency
VPP
µA/MSPS
5
mA
2-VPP input amplitude (1)
400
MHz
1.4-VPP input amplitude
500
MHz
CLOCK INPUTS
Input clock sample rate
184
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
0.2
250
MSPS
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
Input clock duty cycle
1.8
40%
50%
VPP
60%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRVSS
(default strength)
3.3
pF
RLOAD
Differential load resistance between the LVDS output pairs (LVDS mode)
100
Ω
TEMPERATURE RANGE
TA
TJ
(1)
(2)
Operating free-air temperature
Operating junction temperature
+85
°C
Recommended
–40
+105
°C
Maximum rated (2)
+125
°C
See the Theory of Operation section.
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate.
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SPECIAL PERFORMANCE MODES
Best performance can be achieved by writing certain modes depending upon source impedance, band of
operation and sampling speed. Table 1 summarizes the different these modes.
Table 1. High-Performance Modes Summary (1)
SPECIAL MODES SUMMARY
SPECIAL MODE NAME
ADDRESS (Hex)
DATA (Hex)
INPUT FREQUENCIES
(Up to 125 MHz)
High-frequency mode
F1
20
Not required
Must
58
20
Optional
Optional
70
20
Optional
Optional
88
20
Optional
Optional
A0
20
Optional
Optional
High SNR mode (2)
(1)
(2)
INPUT FREQUENCIES
(> 125 MHz)
See the Serial Interface Registers section for details.
High SNR mode improves SNR typically by 1 dB at 170 MHz input frequency. See the Using High SNR Mode Register Settings section.
ELECTRICAL CHARACTERISTICS
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC clock frequency = 250 MHz,
50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
Default resolution
14
Bits
2
VPP
ANALOG INPUTS
Differential input full-scale
VCM
Common mode input voltage
1.15
RIN
Input resistance, differential
V
At 170-MHz input frequency
700
Ω
CIN
Input capacitance, differential
At 170-MHz input frequency
3.3
pF
Analog input bandwidth, 3 dB
With a 50-Ω source driving the ADC
analog inputs
500
MHz
DYNAMIC ACCURACY
EO
Offset error
Gain error (1)
EG
Specified across devices and channels
–15
15
mV
As a result of internal
reference inaccuracy
alone
Specified across devices and channels
–5
5
%FS
Of channel alone
Specified across channels within a device
Channel gain error temperature coefficient (1)
±0.2
%FS
0.001
Δ%/°C
POWER SUPPLY (2)
IAVDD33
3.3-V analog supply
51
mA
1.9-V analog supply
350
mA
IDRVDD
1.8-V digital supply
355
PTOTAL
Total
1.47
Standby
400
IAVDD
Supply current
PDISS(standby)
PDISS(global)
(1)
(2)
4
Power dissipation
Global power-down
6
mA
1.6
W
mW
52
mW
There are two sources of gain error: internal reference inaccuracy and channel gain error.
A 185-MHz, full-scale, sine-wave input signal is applied to all four channels.
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC clock frequency = 250 MHz,
50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise
noted.
PARAMETER
DYNAMIC AC CHARACTERISTICS
TEST CONDITIONS
MIN
Signal-to-noise ratio
SINAD
SFDR
THD
HD2
HD3
(3)
(4)
MAX
UNITS
fIN = 40 MHz
71.1
dBFS
fIN = 70 MHz
71
dBFS
69.5
dBFS
69
dBFS
fIN = 220 MHz
68.5
dBFS
fIN = 307 MHz
67.5
dBFS
fIN = 350 MHz
67
dBFS
fIN = 40 MHz
70.9
dBFS
fIN = 70 MHz
70.8
dBFS
fIN = 140 MHz
69.3
dBFS
68.8
dBFS
fIN = 220 MHz
68.3
dBFS
fIN = 307 MHz
66.8
dBFS
fIN = 350 MHz
66.3
dBFS
fIN = 140 MHz
SNR
TYP
(3)
Signal-to-noise and distortion ratio
Spurious-free dynamic range
Total harmonic distortion
Second-order harmonic distortion (4)
Third-order harmonic distortion
fIN = 170 MHz
fIN = 170 MHz
67.5
66.9
fIN = 40 MHz
84
dBc
fIN = 70 MHz
87
dBc
fIN = 140 MHz
85
dBc
86
dBc
fIN = 220 MHz
84
dBc
fIN = 307 MHz
78
dBc
fIN = 350 MHz
77
dBc
fIN = 40 MHz
83
dBc
fIN = 70 MHz
84
dBc
fIN = 140 MHz
82
dBc
83
dBc
fIN = 220 MHz
82
dBc
fIN = 307 MHz
76
dBc
fIN = 350 MHz
75
dBc
fIN = 40 MHz
96
dBc
fIN = 70 MHz
87
dBc
fIN = 140 MHz
86
dBc
86
dBc
fIN = 220 MHz
84
dBc
fIN = 307 MHz
78
dBc
fIN = 350 MHz
77
dBc
fIN = 40 MHz
83
dBc
fIN = 70 MHz
89
dBc
fIN = 140 MHz
85
dBc
86
dBc
fIN = 220 MHz
85
dBc
fIN = 307 MHz
80
dBc
fIN = 350 MHz
78
dBc
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
78.5
75
78.5
79.5
Phase and amplitude imbalances onboard must be minimized to obtain good performance.
The minimum value across temperature is ensured by bench characterization.
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are at TA = +25°C, full temperature range is TMIN = –40°C to TMAX = +85°C, ADC clock frequency = 250 MHz,
50% clock duty cycle, AVDD33V = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, and –1-dBFS differential input, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC AC CHARACTERISTICS (continued)
Worst spur
(non HD2, HD3)
100
dBc
fIN = 70 MHz
100
dBc
fIN = 140 MHz
95
dBc
95
dBc
fIN = 220 MHz,
95
dBc
fIN = 307 MHz
85
dBc
fIN = 350 MHz
85
fIN = 170 MHz
DNL
Differential nonlinearity
INL
Integral nonlinearity
PSRR
fIN = 40 MHz
87
-0.95
dBc
±0.5
±1.5
LSBs
±5.25
LSBs
Input overload recovery
Recovery to within 1% (of final value) for
6-dB output overload with sine-wave input
1
Clock
cycle
Crosstalk
With a full-scale, 220-MHz signal on
aggressor channel and no signal on victim
channel
90
dB
AC power-supply rejection ratio
For 50-mVPP signal on AVDD supply
< 30
dB
DIGITAL CHARACTERISTICS
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level '0' or '1'. AVDD33 = 3.3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (1) (RESET, SCLK, SDATA, SEN, PDN)
VIH
High-level input voltage
All digital inputs support 1.8-V logic
levels. SPI supports 3.3-V logic levels.
VIL
Low-level input voltage
All digital inputs support 1.8-V logic
levels. SPI supports 3.3-V logic levels.
IIH
High-level input
current
RESET, SCLK, PDN pins
VHIGH = 1.8 V
10
µA
SEN (2) pin
VHIGH = 1.8 V
0
µA
IIL
Low-level input
current
RESET, SCLK, PDN pins
VLOW = 0 V
0
µA
SEN pin
VLOW = 0 V
10
µA
DRVDD
V
1.25
V
0.45
V
DIGITAL OUTPUTS (SDOUT)
VOH
High-level output voltage
VOL
Low-level output voltage
DRVDD –
0.1
0
0.1
V
DIGITAL OUTPUTS, LVDS INTERFACE
(DAB[13:0]P, DAB[13:0]M, DCD[13:0]P, DCD[13:0]M, CLKOUTABP, CLKOUTABM, CLKOUTCDP, CLKOUTCDM)
VODH
High (3)
Standard-swing LVDS
270
350
465
mV
Low
Standard-swing LVDS
–465
–350
–270
mV
VODL
Output differential
voltage
VOCM
Output common-mode voltage
(1)
(2)
(3)
6
1.05
V
RESET, SDATA, and SCLK have an internal 150-kΩ pull-down resistor.
SEN has an internal 150-kΩ pull-up resistor to DRVDD.
With an external 100-Ω termination.
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TIMING REQUIREMENTS (1)
Typical values are at +25°C, AVDD33 = 3.3 V, AVDD = 1.9 V, DRVDD = 1.8 V, sine-wave input clock, CLOAD = 3.3 pF (2), and
RLOAD = 100 Ω (3), unless otherwise noted.
Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = +85°C.
PARAMETER
tA
TEST CONDITIONS
MIN
Aperture delay
tJ
0.7
Aperture delay matching
Between any two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
DRVDD supply
1.2
1.6
UNIT
ns
ps
±150
ps
140
fs rms
100
µs
Time to valid data after coming out of channel power
down
10
µs
Default latency in 14-bit mode
10
Output clock
cycles
Digital gain enabled
13
Output clock
cycles
Digital gain and offset correction enabled
14
Output clock
cycles
Time to valid data after coming out of global power
down
ADC latency (4) (5)
MAX
±70
Aperture jitter
Wake up time
TYP
OUTPUT TIMING (6)
tSU
Data setup time (7) (8) (9)
Data valid to CLKOUTxxP zero-crossing
0.6
0.85
ns
tH
Data hold time (7) (8) (9)
CLKOUTxxP zero-crossing to data becoming invalid
0.6
0.84
ns
LVDS bit clock duty cycle
Differential clock duty cycle (CLKOUTxxP –
CLKOUTxxM)
tPDI
Clock propagation delay (5)
Input clock falling edge cross-over to output clock
falling edge cross-over, 184 MSPS ≤ sampling
frequency ≤ 250 MSPS
tdelay
Delay time
Input clock falling edge cross-over to output clock
falling edge cross-over, 184 MSPS ≤ sampling
frequency ≤ 250 MSPS
tRISE,
tFALL
Data rise and fall time
Rise time measured from –100 mV to +100 mV
0.1
ns
tCLKRISE,
tCLKFALL
Output clock rise and fall
time
Rise time measured from –100 mV to +100 mV
0.1
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
50%
0.25 × tS + tdelay
6.9
8.65
ns
10.5
ns
Timing parameters are ensured by design and characterization and are not tested in production.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
RLOAD is the differential load resistance between the LVDS output pair.
ADC latency is given for channels B and D. For channels A and C, latency reduces by half of the output clock cycles.
Overall latency = ADC latency + tPDI.
Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
Note that these numbers are taken with delayed output clocks by writing the following registers: address A9h, value 02h; and address
ACh, value 60h. Refer to the Serial Interface Registers section. By default after reset, minimum setup time and minimum hold times are
520 ps each.
The setup and hold times of a channel are measured with respect to the same channel output clock.
Table 2. LVDS Timings Across Lower Sampling Frequencies
SETUP TIME (ns)
SAMPLING FREQUENCY
(MSPS)
MIN
TYP
210
0.89
185
1.06
HOLD TIME (ns)
MAX
MIN
TYP
1.03
0.82
1.01
1.21
0.95
1.15
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PARAMETRIC MEASUREMENT INFORMATION
LVDS OUTPUT TIMING
Figure 3 shows a timing diagram of the LVDS output voltage levels. Figure 4 shows the latency described in the
Timing Requirements table.
DxnP
Logic 0
VODL
Logic 1
VODH
DxnM
VOCM
GND
Figure 3. LVDS Output Voltage Levels
Input
Signal
N+3
N+2
N+1
Sample
N
N+4
N+12
N+11
N+10
tA
CLKINM
Input
Clock
CLKINP
CLKOUTABM
(CLKOUTCDM)
CLKOUTABP
(CLKOUTCDP)
10 Clock Cycles
DDR
LVDS
tPDI
Output Data
DABP, DABM
(DCDP, DCDM)
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
(Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)
N-10
N-9
N-8
N-7
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
Ch B
Ch A
(Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C) (Ch D) (Ch C)
N-1
N
N+1
Figure 4. Latency Timing
8
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PARAMETRIC MEASUREMENT INFORMATION (continued)
All 14 data bits of one channel are included in the digital output interface at the same time, as shown in Figure 5.
Channel A and C data are output on the rising edge of the output clock while channels B and D are output on the
falling edge of the output clock.
CLKOUTABM
CLKOUTABP
DAB[13:0]P,
DAB[13:0]M
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
Sample N
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
DA[13:0]P,
DA[13:0]M
Sample N + 1
DB[13:0]P,
DB[13:0]M
Sample N + 2
CLKOUTCDM
CLKOUTCDP
DCD[13:0]P,
DCD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
Sample N
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
DC[13:0]P,
DC[13:0]M
Sample N + 1
DD[13:0]P,
DD[13:0]M
Sample N + 2
Figure 5. LVDS Output Interface Timing
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PIN CONFIGURATION
ZCR PACKAGE
BGA-144
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
A
AVDD
AVDD
CINM
CINP
AVDD
VCM
VCM
AVDD
BINM
BINP
AVDD
AVDD
B
DINP
AVSS
AVDD
AVDD
AVSS
AVDD33
AVDD33
AVSS
AVDD
AVDD
AVSS
AINM
C
DINM
AVSS
AVSS
AVSS
AVSS
CLKINM
CLKINP
AVSS
AVSS
AVSS
AVSS
AINP
D
AVDD
AVDD
VCM
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
VCM
AVDD
AVDD
E
AVDD33
AVDD33
NC
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
PDN
AVDD33
AVDD33
F
DCD13M
DCD13P
DRVDD
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
DRVSS
DRVDD
DAB13P
DAB13M
G
DCD12M
DCD12P
NC
NC
NC
RESET
SCLK
SDATA
SEN
SDOUT
DAB12P
DAB12M
H
DCD11M
DCD11P
DCD6P
DCD6M
DRVDD
DRVDD
DRVDD
DRVDD
DAB6M
DAB6P
DAB11P
DAB11M
J
DCD10M
DCD10P
DCD5P
DCD5M
DCD2P
DRVDD
DRVDD
DAB2M
DAB5M
DAB5P
DAB10P
DAB10M
K
DCD9M
DCD9P
DCD4P
DCD4M
DCD2M
DRVDD
DRVDD
DAB2P
DAB4M
DAB4P
DAB9P
DAB9M
L
DCD8M
DCD8P
DCD3P
DCD3M
DCD1P
DCD1M
DAB1M
DAB1P
DAB3M
DAB3P
DAB8P
DAB8M
M
DCD7M
DCD7P
CLKOUT
CDP
CLKOUT
CDM
DCD0P/
OVRCDP
DCD0M/
OVRCDM
DAB0M/
OVRABM
DAB0P/
OVRABP
CLKOUT
ABM
CLKOUT
ABP
DAB7P
DAB7M
10
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PIN FUNCTIONS
PIN
NAME
NUMBER
I/O
DESCRIPTION
AINM
B12
I
Negative differential analog input for channel A
AINP
C12
I
Positive differential analog input for channel A
AVDD33
B6, B7, E1, E2, E11, E12
I
Analog 3.3-V power supply
AVDD
A1, A2, A5, A8, A11, A12,
B3, B4, B9, B10, D1, D2,
D11, D12
I
Analog 1.9-V power supply
AVSS
B2, B5, B8, B11, C2-C5,
C8-C11, D4-D9
I
Analog ground
BINM
A9
I
Negative differential analog input for channel B
BINP
A10
I
Positive differential analog input for channel B
CINM
A3
I
Negative differential analog input for channel C
CINP
A4
I
Positive differential analog input for channel C
CLKINM
C6
I
Negative differential clock input
CLKINP
C7
I
Positive differential clock input
CLKOUTABM
M9
O
Negative differential LVDS clock output for channel A and B
CLKOUTABP
M10
O
Positive differential LVDS clock output for channel A and B
CLKOUTCDM
M4
O
Negative differential LVDS clock output for channels C and D
CLKOUTCDP
M3
O
Positive differential LVDS clock output for channels C and D
DAB[13:1]P,
DAB0P/OVRABP,
DAB[13:1]M,
DAB0M/OVRABM
F11, F12, G11, G12,
H9-H12, J8-J12, K8-K12,
L7-L12, M7, M8, M11, M12
O
DDR LVDS outputs for channels A and B.
DCD[13:1]P,
DCD0P/OVRCDP,
DCD[13:1]M,
DCD0M/OVRCDM
F1, F2, G1, G2, H1-H4,
J1-J5, K1-K5, L1-L6, M1,
M2, M5, M6
O
DDR LVDS outputs for channels C and D.
DINM
C1
I
Negative differential analog input for channel D
DINP
B1
I
Positive differential analog input for channel D
DRVDD
F3, F10, H5-H8, J6, J7, K6,
K7
I
Digital 1.8-V power supply
DRVSS
E4-E9, F4-F9
I
Digital ground
NC
E3, G3, G4, G5
-
Do not connect
PDN
E10
I
Power-down control; active high. Logic high is power down.
RESET
G6
I
Hardware reset; active high
SCLK
G7
I
Serial interface clock input
SDATA
G8
I
Serial interface data input
SDOUT
G10
O
Serial interface data output
SEN
G9
I
Serial interface enable
VCM
A6, A7, D3, D10
O
Common-mode voltage for analog inputs. All VCM pins are internally connected together.
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FUNCTIONAL BLOCK DIAGRAM
DAB0P, DAB0M or
OVRABP, OVRABM
14-Bit
ADC
AINP,
AINM
14
Digital
Block
CLKOUTABP,
CLKOUTABM
14-Bit
ADC
BINP,
BINM
DAB[13:1]P,
DAB[13:1]M
Output
Formatter
CLKINP,
CLKINM
DDR
LVDS
14-Bit
ADC
CINP,
CINM
DCD0P, DCD0M or
OVRCDP, OVRCDM
Digital
Block
14-Bit
ADC
DINP,
DINM
VCM
14
DCD[13:1]P,
DCD[13:1]M
CLKOUTCDP,
CLKOUTCDM
Common
Mode
12
SNRB
PDN
SDOUT
SDATA
SEN
SCLK
RESET
Configuration Registers
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TYPICAL CHARACTERISTICS
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
0
0
FIN = 40 MHz
SFDR = 84 dBc
SNR = 71.1 dBFS
SINAD = 70.9 dBFS
THD = 84 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
FIN = 70 MHz
SFDR = 87 dBc
SNR = 70.9 dBFS
SINAD = 70.8 dBFS
THD = 84 dBc
0
25
50
75
100
Frequency (MHz)
−120
125
0
25
100
125
G002
Figure 7. FFT FOR 70-MHz INPUT SIGNAL
0
0
FIN = 100 MHz
SFDR = 85 dBc
SNR = 70.2 dBFS
SINAD = 70.1 dBFS
THD = 84 dBc
−20
FIN = 140 MHz
SFDR = 87 dBc
SNR = 69.7 dBFS
SINAD = 69.6 dBFS
THD = 84 dBc
−20
−40
Amplitude (dB)
−40
Amplitude (dBFS)
75
Frequency (MHz)
G001
Figure 6. FFT FOR 40-MHz INPUT SIGNAL
−60
−60
−80
−80
−100
−100
−120
50
0
25
50
75
100
Frequency (MHz)
125
−120
0
25
50
75
Frequency (MHz)
100
G003
Figure 8. FFT FOR 100-MHz INPUT SIGNAL
G004
Figure 9. FFT FOR 140-MHz INPUT SIGNAL
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
0
0
FIN = 170 MHz
SFDR = 89 dBc
SNR = 69 dBFS
SINAD = 68.9 dBFS
THD = 85 dBc
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
FIN = 230 MHz
SFDR = 86 dBc
SNR = 68.6 dBFS
SINAD = 68.5 dBFS
THD = 84 dBc
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
50
75
Frequency (MHz)
100
125
G005
G006
Figure 10. FFT FOR 170-MHz INPUT SIGNAL
Figure 11. FFT FOR 230-MHz INPUT SIGNAL
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 45 MHz
fIN2 = 50 MHz
2−Tone IMD = 87 dBFS
SFDR = 92 dBFS
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−80
−100
−100
0
25
50
75
100
Frequency (MHz)
125
−120
0
25
50
75
100
Frequency (MHz)
G007
Figure 12. FFT FOR TWO-TONE INPUT SIGNAL
(–7 dBFS)
14
−60
−80
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 45 MHz
fIN2 = 50 MHz
2−Tone IMD = 99 dBFS
SFDR = 99 dBFS
125
G008
Figure 13. FFT FOR TWO-TONE INPUT SIGNAL
(–36 dBFS)
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
0
0
Each Tone at
−7 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
2−Tone IMD = 97 dBFS
SFDR = 102 dBFS
−20
−20
−40
Amplitude (dB)
Amplitude (dB)
−40
−60
−60
−80
−80
−100
−100
−120
Each Tone at
−36 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
2−Tone IMD = 101 dBFS
SFDR = 100 dBFS
0
25
50
75
Frequency (MHz)
100
−120
125
0
25
50
75
Frequency (MHz)
100
125
G009
G010
Figure 14. FFT FOR TWO-TONE INPUT SIGNAL
(–7 dBFS)
Figure 15. FFT FOR TWO-TONE INPUT SIGNAL
(–36 dBFS)
25
93
Input Frequency = 170 MHz
91
Temperature = −40 C
Temperature = 25 C
Temperature = 85 C
20
88
Count (%)
SFDR (dBc)
85
82
15
10
79
76
5
73
40
80
120
160
200
240
280
320
360
Input Frequency (MHz)
400
0
−108
−105
−104
−103
−102
−101
−100
−99
−98
−97
−96
−95
−94
−93
−92
−91
−90
−89
−88
−87
−86
−85
−84
−83
−82
70
HD2 (dBc)
G011
G039
Figure 16. SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
Figure 17. HD2 DISTRIBUTION OVER MULTIPLE DEVICES
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
72
104
40 MHz
100 MHz
130 MHz
100
71
170 MHz
230 MHz
300 MHz
350 MHz
400 MHz
450 MHz
96
92
88
SFDR (dBc)
SNR (dBFS)
70
69
68
84
80
76
67
72
66
68
40
80
120
160
200
240
280
320
360
64
400
Input Frequency (MHz)
1
1.5
2
2.5 3 3.5 4
Digital Gain (dB)
4.5
5
5.5
G013
130
75.5
40 MHz
100 MHz
130 MHz
73
72
170 MHz
230 MHz
300 MHz
Input Frequency = 70 MHz
350 MHz
400 MHz
450 MHz
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
75
120
110
71
74
100
70
73.5
90
73
80
72.5
70
67
72
60
66
71.5
50
65
71
40
64
70.5
30
SNR (dBFS)
74.5
69
68
63
62
70
−70
0
0.5
1
1.5
2
2.5
3
3.5
Digital Gain (dB)
4
4.5
5
5.5
6
Figure 19. SPURIOUS-FREE DYNAMIC RANGE
vs DIGITAL GAIN
74
SNR (dBFS)
0.5
G012
Figure 18. SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY
6
−60
−50
−40
−30
−20
−10
0
20
Amplitude (dBFS)
G015
G014
Figure 20. SIGNAL-TO-NOISE RATIO vs DIGITAL GAIN
16
0
SFDR (dBc,dBFS)
65
Figure 21. PERFORMANCE vs INPUT AMPLITUDE
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
74
120
72
94
100
73
90
72.5
80
72
70
71.5
60
71
50
70.5
40
70
SFDR (dBc)
SFDR (dBFS)
SNR
30
20
−50
−40
−30
−20
Amplitude (dBFS)
−10
71.5
90
71
88
70.5
86
70
84
69.5
82
69
68.5
80
69.5
0
92
SNR (dBFS)
73.5
SFDR (dBc,dBFS)
110
SFDR (dBc)
Input Frequency = 185 MHz
SNR (dBFS)
Input Frequency = 185 MHz
SFDR
SNR
69
78
0.7
0.8
68
1.3
0.9
1
1.1
1.2
Input Common−Mode Voltage (V)
G016
G017
Figure 22. PERFORMANCE vs INPUT AMPLITUDE
Figure 23. PERFORMANCE vs
INPUT COMMON-MODE VOLTAGE
71
90
Input Frequency = 185 MHz
Input Frequency = 185 MHz
89
70.5
88
SNR (dBFS)
SFDR (dBc)
70
87
86
69.5
69
85
DRVDD = 1.7 V
DRVDD = 1.8 V
DRVDD = 1.9 V
DRVDD = 2 V
84
83
−40
−15
10
35
Temperature (°C)
68.5
60
85
68
−40
DRVDD = 1.7 V
DRVDD = 1.8 V
DRVDD = 1.9 V
DRVDD = 2 V
−15
10
35
Temperature (°C)
60
G018
Figure 24. SPURIOUS-FREE DYNAMIC RANGE vs
DRVDD SUPPLY AND TEMPERATURE
G019
Figure 25. SIGNAL-TO-NOISE RATIO vs
DRVDD SUPPLY AND TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
71
90
Input Frequency = 185 MHz
Input Frequency = 185 MHz
89
70.5
88
70
SNR (dBFS)
SFDR (dBc)
87
86
69.5
85
69
84
68.5
AVDD = 1.8 V
AVDD = 1.9 V
AVDD = 2 V
83
82
−40
−15
10
35
Temperature (°C)
60
68
−40
85
AVDD = 1.8 V
AVDD = 1.9 V
AVDD = 2 V
−15
10
35
Temperature (°C)
60
85
G020
G021
Figure 26. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD SUPPLY AND TEMPERATURE
Figure 27. SIGNAL-TO-NOISE RATIO vs
AVDD SUPPLY AND TEMPERATURE
71
90
Input Frequency = 185 MHz
Input Frequency = 185 MHz
89
70.5
88
70
SNR (dBFS)
SFDR (dBc)
87
86
69.5
85
69
84
68.5
AVDD3V = 3.15 V
AVDD3V = 3.3 V
AVDD3V = 3.45 V
83
82
−40
−15
10
35
Temperature (°C)
60
85
68
−40
AVDD3V = 3.15 V
AVDD3V = 3.3 V
AVDD3V = 3.45 V
−15
10
35
Temperature (°C)
60
G022
Figure 28. SPURIOUS-FREE DYNAMIC RANGE vs
AVDD3V SUPPLY AND TEMPERATURE
18
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G023
Figure 29. SIGNAL-TO-NOISE RATIO vs
AVDD3V SUPPLY AND TEMPERATURE
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
71
72
92
98
70.5
96
70
94
69.5
92
69
90
68.5
88
68
86
67.5
84
67
82
66.5
80
66
SFDR
SNR
78
76
0.2
0.5
0.8
1.1
1.4
1.7
Differential Clock Amplitudes (Vpp)
2
THD (dBc)
Input Frequency = 185 MHz
SNR (dBFS)
SFDR (dBc)
Input Frequency = 185 MHz
91
71.5
90
71
89
70.5
88
70
87
69.5
86
69
85
68.5
84
68
83
65.5
65
2.3
82
SNR
THD
25
30
35
40
45
50
55
60
Input Clock Duty Cycle (%)
65
70
75
SNR (dBFS)
100
67.5
67
G024
G025
Figure 30. PERFORMANCE vs CLOCK AMPLITUDE
Figure 31. PERFORMANCE vs CLOCK DUTY CYCLE
0
0
Input Frequency = 185 MHz
50−mVPP Signal Superimposed on VCM
−5
FIN = 185 MHz
FCM = 10 MHz, 50−mVPP
SFDR = 76 dBc
Amlpitude(FIN) = −1 dBFS
Amlpitude(FCM) = −95 dBFS
Amplitude
FIN + FCM = −77.2 dBFS
Amplitude
FIN − FCM = −80.9 dBFS
−20
−10
−15
−40
Amplitude (dB)
CMRR (dB)
−20
−25
−30
−35
−40
−60
−80
−45
−50
−100
−55
−60
0
50
100
150
200
250
Frequency of Input Common−Mode Signal (MHz)
300
−120
0
25
50
75
Frequency (MHz)
100
125
G026
Figure 32. COMMON-MODE REJECTION RATIO SPECTRUM
G027
Figure 33. COMMON-MODE REJECTION RATIO vs
TEST SIGNAL FREQUENCY
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
0
−20
−25
−20
−30
−40
Amplitude (dB)
PSRR (dB)
−35
−40
−45
−50
−60
−80
−55
−60
−100
−65
−70
FIN = 10 MHz
FPSRR = 2 MHz, 50−mVPP
Amlpitude(FIN) = −1 dBFS
Amlpitude(FPSRR) = −87 dBFS
Amplitude
FIN + FPSRR = −60.6 dBFS
Amplitude
FIN − FPSRR = −60 dBFS
PSRR on AVDD Supply
PSRR on AVDD3V Supply
Input Frequency = 10 MHz
50−mVPP Signal Superimposed on Supply
0
50
100
150
200
250
Frequency of Signal on Supply (MHz)
−120
300
0
10
20
30
Frequency (MHz)
40
50
G028
G029
Figure 34. POWER-SUPPLY REJECTION RATIO
SPECTRUM FOR AVDD
Figure 35. POWER-SUPPLY REJECTION RATIO vs
TEST SIGNAL FREQUENCY
1.6
800
Input Frequency = 185 MHz
AVDD Power
AVDD3V Power
DRVDD Power
700
1.4
Input Frequency = 185 MHz
600
Analog Power (mW)
Total Power (W)
1.2
1.0
0.8
500
400
300
0.6
200
0.4
0.2
100
1
26
51
76 101 126 151 176
Sampling Speed (MSPS)
201
226 250
0
1
G030
Figure 36. TOTAL POWER vs SAMPLING FREQUENCY
20
26
51
76 101 126 151 176
Sampling Speed (MSPS)
201
226 250
G031
Figure 37. POWER BREAKUP vs SAMPLING FREQUENCY
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
250
87
83
Sampling Frequency, MSPS
240
87
230
87
87
91
87
83
95
210
70
75
87
91
220
80
80
70
75
87
87
200
91
190
87
50
87
83
91
100
70
150
75
75
80
200
250
300
350
Input Frequency, MHz
80
70
400
85
90
450
95
Figure 38. SPURIOUS-FREE DYNAMIC RANGE
(0-dB Gain)
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
250
Sampling Frequency, MSPS
88 86 84
90
240
79
82
76
230
220
90
88
86
84
86
84
82
79
76
210
200
90
190
88
50
100
74
76
150
78
82
200
250
300
350
Input Frequency, MHz
80
82
84
79
400
86
76
450
88
90
Figure 39. SPURIOUS-FREE DYNAMIC RANGE
(6-dB Gain)
22
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
250
70.2 69.8 69.4
Sampling Frequency, MSPS
240
69
68.5
68
67.5
66.5
67
66
70.6
230
65.5
220
70.2
69.8
69.4 69 68.5
68
67.5
67
66.5
66
210
200
190
50
69.4 6968.568
69.8
70.2
100
66
150
67.5
67
66.5
200
250
300
350
Input Frequency, MHz
400
67
68
69
66
450
70
Figure 40. SIGNAL-TO-NOISE RATIO
(0-dB Gain)
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
250
64.5
Sampling Frequency, MSPS
240
64.1
63.7
63.3
64.9
230
62.5
62.9
64.7
220
64.5
64.1 63.7
210
64.9
63.3
64.7
62.9
64.7
200
190
64.5
63.3
63.7
64.1
64.5
50
100
62.5
150
62.9
62.5
200
250
300
350
Input Frequency, MHz
63
63.5
64
400
450
64.5
Figure 41. SIGNAL-TO-NOISE RATIO
(6-dB Gain)
24
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DEVICE CONFIGURATION
The ADS4449 can be configured with a serial programming interface (SPI), as described in the Serial Interface
section. In addition, the device has control pins that control power-down.
SERIAL INTERFACE
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface input data), and SDOUT (serial interface
readback data) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data (SDATA) are
latched at every SCLK falling edge when SEN is active (low). Serial data are loaded into the register at every
16th SCLK falling edge when SEN is low. When the word length exceeds a multiple of 16 bits, the excess bits
are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits
form the register address and the remaining eight bits are the register data. The interface can function with SCLK
frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through a hardware reset by applying a high pulse on the RESET pin (of widths greater than 10 ns),
as shown in Figure 42; or
2. By applying a software reset. When using the serial interface, set the RESET bit (D1 in register 00h) high.
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In
this case, the RESET pin is kept low.
Register Address
SDATA
A6
A7
A5
A4
A3
Register Data
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tDH
tSCLK
tDSU
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 42. Serial Interface Timing
Table 3. Timing Characteristics for Figure 42
PARAMETER
MIN
> dc
TYP
MAX
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDI setup time
25
ns
tDH
SDI hold time
25
ns
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Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back, as shown in
Figure 43. This readback mode can be useful as a diagnostic check to verify the serial interface communication
between the external controller and ADC.
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers except register
address 00h.
2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.
3. The device outputs the contents (D[7:0]) of the selected register on the SDOUT pin (pin G10).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
Note that the contents of register 00h cannot be read back because the register contains RESET and READOUT
bits. When the READOUT bit is disabled, the SDOUT pin is in a high-impedance state. If serial readout is not
used, the SDOUT pin must not be connected (must float).
Register Address A[7:0] = 00h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = 01h
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SEN
The SDOUT pin is in a high-impedance state (READOUT = 0).
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
SDATA
A7
A6
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
The SDOUT pin functions as a serial readout (READOUT = 1).
b) Read contents of Register 45h. This register is initialized with 04h.
Figure 43. Serial Readout Timing Diagram
SDOUT comes out at the SCLK rising edge with an approximate delay (tSD_DELAY) of 8 ns, as shown in Figure 44.
SCLK
tSD_DELAY
SDOUT
Figure 44. SDOUT Delay Timing
26
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SERIAL INTERFACE REGISTERS
Table 4 summarizes the ADS4449 registers.
Table 4. Register Map
REGISTER
ADDRESS
A[7:0] (Hex)
D7
D6
D5
D4
REGISTER DATA
D3
D2
D1
D0
00
0
0
0
0
0
0
RESET
READOUT
0
0
01
LVDS SWING
25
DIGITAL GAIN CH B
DIGITAL GAIN
BYPASS CH B
TEST PATTERN CH B
2B
DIGITAL GAIN CH A
DIGITAL GAIN
BYPASS CH A
TEST PATTERN CH A
31
DIGITAL GAIN CH D
DIGITAL GAIN
BYPASS CH D
TEST PATTERN CH D
DIGITAL GAIN CH C
DIGITAL GAIN
BYPASS CH C
TEST PATTERN CH C
37
3D
0
0
3F
0
0
0
0
OFFSET CORR
EN1
0
0
0
0
CUSTOM PATTERN[13:8]
40
42
0
CUSTOM PATTERN[7:0]
0
0
45
0
0
0
DIS OVR ON LSB
A9
0
0
0
0
AC
0
DIGITAL ENABLE
0
0
0
SEL OVR
GLOBAL POWER
DOWN
0
CONFIG PDN PIN
CLOCKOUT DELAY PROG CH AB
CLOCKOUT DELAY PROG CH CD
C3
0
0
ALWAYS WRITE
1
FAST OVR THRESH PROG
C4
EN FAST OVR
THRESH
0
0
0
0
0
0
0
CF
0
0
0
0
OFFSET CORR
EN2
0
0
0
D6
ALWAYS WRITE
1
0
0
0
0
0
0
0
D7
0
0
0
0
ALWAYS WRITE
1
ALWAYS WRITE
1
0
0
F1
0
0
HIGH FREQ
MODE
0
0
HIGH SNR MODE
CH A
0
0
0
0
0
ENABLE LVDS SWING PROG
58
0
0
59
ALWAYS WRITE
1
0
0
0
0
0
0
0
HIGH SNR MODE
CH B
0
0
0
0
0
70
0
0
71
ALWAYS WRITE
1
0
0
0
0
0
0
0
0
0
0
0
0
88
0
0
HIGH SNR MODE
CH D
89
ALWAYS WRITE
1
0
0
0
0
0
0
0
A0
0
0
HIGH SNR MODE
CH C
0
0
0
0
0
A1
ALWAYS WRITE
1
0
0
0
0
0
0
0
FE
0
0
0
0
PDN CH D
PDN CH C
PDN CH A
PDN CH B
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DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
RESET
READOUT
Bits D[7:2]
Always write '0'
Bit D1
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to '0'.
Bit D0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance
state. (default)
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with
CMOS logic levels running from the DRVDD supply.
Register Address 01h (Default = 00h)
D7
D6
D5
D4
D3
LVDS SWING
Bits D[7:2]
D2
D1
D0
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing only after the ENABLE LVDS SWING PROG bits
are set to '11'.
000000 = Default LVDS swing; ±350 mV with an external 100-Ω termination (default)
011011 = ±420-mV LVDS swing with an external 100-Ω termination
110010 = ±470-mV LVDS swing with an external 100-Ω termination
010100 = ±560-mV LVDS swing with an external 100-Ω termination
001111 = ±160-mV LVDS swing with an external 100-Ω termination
Bits D[1:0]
28
Always write '0'
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Register Address 25h (Default = 00h)
D7
D6
D5
D4
D3
DIGITAL GAIN CH B
Bits D[7:4]
DIGITAL GAIN BYPASS CH B
D2
D1
D0
TEST PATTERN CH B
DIGITAL GAIN CH B: Channel B digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel B. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH B: Channel B digital gain bypass
0 = Normal operation (default)
1 = Digital gain feature for channel B is bypassed
Bits D[2:0]
TEST PATTERN CH B: Channel B test pattern programmability
These bits program the test pattern for channel B.
000 = Normal operation (default)
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
Output data ([D:0]) are an alternating sequence of 01010101010101 and
10101010101010.
100 = Outputs digital ramp
Output data increments by one 14-bit LSB every clock cycle from code 0 to code
16383
101 = Outputs custom pattern
To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh
and 40h.
110 = Unused
111 = Unused
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Register Address 2Bh (Default = 00h)
D7
D6
D5
D4
D3
DIGITAL GAIN CH A
Bits D[7:4]
DIGITAL GAIN BYPASS CH A
D2
D1
D0
TEST PATTERN CH A
DIGITAL GAIN CH A: Channel A digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel A. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH A: Channel A digital gain bypass
0 = Normal operation (default)
1 = Digital gain feature for channel A is bypassed
Bits D[2:0]
TEST PATTERN CH A: Channel A test pattern programmability
These bits program the test pattern for channel A.
000 = Normal operation (default)
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
Output data ([D:0]) are an alternating sequence of 01010101010101 and
10101010101010.
100 = Outputs digital ramp
Output data increments by one 14-bit LSB every clock cycle from code 0 to code
16383
101 = Outputs custom pattern
To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh
and 40h.
110 = Unused
111 = Unused
30
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Register Address 31h (Default = 00h)
D7
D6
D5
D4
D3
DIGITAL GAIN CH D
Bits D[7:4]
DIGITAL GAIN BYPASS CH D
D2
D1
D0
TEST PATTERN CH D
DIGITAL GAIN CH D: Channel D digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel D. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH D: Channel D digital gain bypass
0 = Normal operation (default)
1 = Digital gain feature for channel A is bypassed
Bits D[2:0]
TEST PATTERN CH D: Channel D test pattern programmability
These bits program the test pattern for channel D.
000 = Normal operation (default)
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
Output data ([D:0]) are an alternating sequence of 01010101010101 and
10101010101010.
100 = Outputs digital ramp
Output data increments by one 14-bit LSB every clock cycle from code 0 to code
16383
101 = Outputs custom pattern
To program test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh and
40h.
110 = Unused
111 = Unused
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Register Address 37h (Default = 00h)
D7
D6
D5
D4
D3
DIGITAL GAIN CH C
Bits D[7:4]
DIGITAL GAIN BYPASS CH C
D2
D1
D0
TEST PATTERN CH C
DIGITAL GAIN CH C: Channel C digital gain programmability
These bits set the digital gain programmability from 0 dB to 6 dB in 0.5-dB steps for
channel C. Set the DIGITAL ENABLE bit to '1' beforehand to enable this feature.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit D3
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
DIGITAL GAIN BYPASS CH C: Channel C digital gain bypass
0 = Normal operation (default)
1 = Digital gain feature for channel A is bypassed
Bits D[2:0]
TEST PATTERN CH C: Channel C test pattern programmability
These bits program the test pattern for channel C.
000 = Normal operation (default)
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
Output data ([D:0]) are an alternating sequence of 01010101010101 and
10101010101010.
100 = Outputs digital ramp
Output data increments by one 14-bit LSB every clock cycle from code 0 to code
16383
101 = Outputs custom pattern
To program a test pattern, use the CUSTOM PATTERN D[13:0] bits of registers 3Fh
and 40h.
110 = Unused
111 = Unused
32
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Register Address 3Dh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
OFFSET CORR EN1
0
0
0
0
0
Bits D[7:6]
Always write '0'
Bit D5
OFFSET CORR EN1: Offset correction setting
This bit enables the offset correction feature for all four channels after the DIGITAL
ENABLE bit is set to ‘1,’ correcting mid-code to 8191. In addition, write the OFFSET
CORR EN2 bit (register CFh, value 08h) for proper operation of the offset correction
feature.
0 = Offset correction disabled (default)
1 = Offset correction enabled
Bits D[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
D7
0
D6
D5
D4
D3
D2
D1
D0
0
CUSTOM
PATTERN D13
CUSTOM
PATTERN D12
CUSTOM
PATTERN D11
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
Bits D[7:6]
Always write '0'
Bits D[5:0]
CUSTOM PATTERN D[13:8]
Set the custom pattern using these bits for all four channels.
Register Address 40h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
CUSTOM
PATTERN D7
CUSTOM
PATTERN D6
CUSTOM
PATTERN D5
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
Bits D[7:0]
CUSTOM PATTERN D[7:0]
Set the custom pattern using these bits for all four channels.
Register Address 42h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
DIGITAL ENABLE
0
0
0
Bits D[7:4]
Always write '0'
Bit D3
DIGITAL ENABLE
1 = Digital gain and offset correction features disabled
1 = Digital gain and offset correction features enabled
Bits D[2:0]
Always write '0'
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Register Address 45h (Default = 00h)
D7
D6
0
D5
D4
D3
D2
D1
D0
0
DIS OVR
ON LSB
SEL OVR
GLOBAL POWER DOWN
0
CONFIG PDN PIN
0
Bits D[7:5]
Always write '0'
Bit D4
DIS OVR ON LSB
0 = Effective ADC resolution is 13 bits (the LSB of a 14-bit output is OVR) (default)
1 = ADC resolution is 14 bits
Bit D3
SEL OVR: OVR selection
0 = Fast OVR selected (default)
1 = Normal OVR selected. See the Overrange Indication (OVRxx) section for details.
Bit D2
GLOBAL POWER DOWN
0 = Normal operation (default)
1 = Global power down. All ADC channels, internal references, and output buffers are
powered down. Wakeup time from this mode is slow (100 µs).
Bit D1
Always write '0'
Bit D0
CONFIG PDN PIN
Use this bit to configure PDN pin.
0 = The PDN pin functions as a standby pin. All channels are put in standby. Wake-up
time from standby mode is fast (10 µs). (default)
1 = The PDN pin functions as a global power-down pin. All ADC channels, internal
references, and output buffers are powered down. Wake-up time from global power
mode is slow (100 µs).
Register Address A9h (Default = 00h)
D7
D6
D5
D4
0
0
0
0
Bits D[7:4]
Always write '0'
Bits D[6:3]
CLOCKOUT DELAY PROG CH AB
D3
D2
D1
D0
CLOCKOUT DELAY PROG CH AB
These bits program the clock out delay for channels A and B, see Table 5.
34
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Register Address ACh (Default = 00h)
D7
D6
0
D5
D4
D3
CLOCKOUT DELAY PROG CH CD
Bit D7
Always write '0'
Bits D[7:4]
CLOCKOUT DELAY PROG CH CD
D2
D1
D0
0
ALWAYS
WRITE 1
0
These bits program the clock out delay for channels C and D, as shown in Table 5.
Bits D[2:1]
Always write '0'
Bit D[0]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
Table 5. Clock Out Delay Programmability for All Channels
CLOCKOUT DELAY PROG CHxx
DELAY (ps)
0000 (default)
0 (default)
0001
–30
0010
70
0011
30
0100
–150
0101
–180
0110
–70
0111
–110
1000
270
1001
230
1010
340
1011
300
1100
140
1101
110
1110
200
1111
170
Register Address C3h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
FAST OVR THRESH PROG
Bits D[7:0]
FAST OVR THRESH PROG
The ADS4449 has a fast OVR mode that indicates an overload condition at the ADC
input. The input voltage level at which the overload is detected is referred to as the
threshold and is programmable using the FAST OVR THRESH PROG bits.
FAST OVR is triggered seven output clock cycles after the overload condition occurs. To
enable the FAST OVR programmability, enable the EN FAST OVR THRESH register bit.
The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the
FAST OVR THRESH PROG bits] / 255).
After reset, when EN FAST OVR THRESH PROG is set, the default value of the FAST
OVR THRESH PROG bits is 230 (decimal).
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Register Address C4h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
EN FAST OVR THRESH
0
0
0
0
0
0
0
Bit D7
EN FAST OVR THRESH
This bit enables the ADS4449 to be programmed to select the fast OVR threshold.
Bits D[6:0]
Always write '0'
Register Address CFh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
OFFSET CORR EN2
0
0
0
Bits D[7:4]
Always write '0'
Bit D3
OFFSET CORR EN2
This bit must be set to ‘1’ when the OFFSET CORR EN1 bit is selected.
Bits D[2:0]
Always write '0'
Register Address D6h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
ALWAYS
WRITE 1
0
0
0
0
0
0
0
Bits D[7]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
Bits D[6:0]
Always write '0'
Register Address D7h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
ALWAYS WRITE 1
ALWAYS
WRITE 1
0
0
Bits D[7:4], Bits
D[1:0]
Always write '0'
Bits D[3]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
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Register Address F1h (Default = 00h)
D7
D6
D5
D4
D3
0
0
HIGH FREQ MODE
0
0
Bits D[7:6]
Always write '0'
Bit D5
HIGH FREQ MODE
D2
D1
D0
ENABLE LVDS SWING PROG
0 = Default (default)
1 = Use for input frequencies > 125 MHz
Bits D[4:3]
Always write '0'
Bits D[2:0]
ENABLE LVDS SWING PROG
This bit enables the LVDS swing control with the LVDS SWING bits.
00 = LVDS swing control disabled (default)
01 = Do not use
10 = Do not use
11 = LVDS swing control enabled
Register Address 58h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HIGH SNR
MODE CH A
0
0
0
0
0
Bits D[7:6], Bits
D[4:0]
Always write '0'
Bit D5
HIGH SNR MODE CH A
See the Using High SNR MODE Register Settings section.
Register Address 59h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
ALWAYS
WRITE 1
0
0
0
0
0
0
0
Bits D[7]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
Bits D[6:0]
Always write '0'
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Register Address 70h (Default = 00h)
D7
0
D6
D5
D4
D3
D2
D1
D0
0
HIGH SNR
MODE CH B
0
0
0
0
0
Bits D[7:6], Bits
D[4:0]
Always write '0'
Bit D5
HIGH SNR MODE CH B
See the Using High SNR MODE Register Settings section.
Register Address 71h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
ALWAYS
WRITE 1
0
0
0
0
0
0
0
Bits D[7]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
Bits D[6:0]
Always write '0'
Register Address 88h (Default = 00h)
D7
0
D6
D5
D4
D3
D2
D1
D0
0
HIGH SNR
MODE CH D
0
0
0
0
0
Bits D[7:6], Bits
D[4:0]
Always write '0'
Bit D5
HIGH SNR MODE CH D
See the Using High SNR MODE Register Settings section.
Register Address 89h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
ALWAYS
WRITE 1
0
0
0
0
0
0
0
Bits D[7]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
Bits D[6:0]
38
Always write '0'
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Register Address A0h (Default = 00h)
D7
0
D6
D5
D4
D3
D2
D1
D0
0
HIGH SNR
MODE CH C
0
0
0
0
0
Bits D[7:6], Bits
D[4:0]
Always write '0'
Bit D5
HIGH SNR MODE CH C
See the Using High SNR MODE Register Settings section.
Register Address A1h (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
ALWAYS
WRITE 1
0
0
0
0
0
0
0
Bits D[7]
Always write '1'
This bit is set to 0 by default. User must set it to 1 after reset or power-up.
Bits D[6:0]
Always write '0'
Register Address FEh (Default = 00h)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
PDN CH D
PDN CH C
PDN CH A
PDN CH B
Bits D[7:4]
Always write '0'
Bit D3
PDN CH D: Power-down channel D
Channel D is powered down.
Bit D2
PDN CH C: Power-down channel C
Channel C is powered down.
Bit D1
PDN CH B: Power-down channel B
Channel B is powered down.
Bit D0
PDN CH A: Power-down channel A
Channel A is powered down.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS4449 is a quad-channel, 14-bit, analog-to-digital converter (ADC) with sampling rates up to
250 MSPS. At every falling edge of the input clock, the analog input signal for each channel is sampled
simultaneously. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each
stage, the sampled-and-held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference
(residue) between the stage input and quantized equivalent is gained and propagates to the next stage. At every
clock, each subsequent stage resolves the sampled input with greater accuracy. The digital outputs from all
stages are combined in a digital correction logic block and are digitally processed to create the final code, after a
data latency of 10 clock cycles. The digital output is available in a double data rate (DDR) low-voltage differential
signaling (LVDS) interface and is coded in binary twos complement format.
ENABLING 14-BIT RESOLUTION
By default after reset, the ADS4449 outputs 11-bit data on the Dxx13P, Dxx13M and Dxx3P, Dxx3M pins and
OVR information on the Dxx0P, Dxx0M pins. When the ALWAYS WRITE 1 bits are set, the ADC outputs 13-bit
data on the Dxx13P, Dxx13M and Dxx1P, Dxx1M pins and OVR information on the Dxx0P, Dxx0M pins. To
enable 14-bit resolution, the DIS OVR ON LSB register bit must be set to '1' as indicated in Table 6.
Table 6. ADC configuration
DATA ON ADC PINS
ADC PIN NAMES
AFTER RESET
ALWAYS WRITE 1 = 1
ALWAYS WRITE 1 = 1
DIS OVR ON LSB = 1
Dxx13
D13
D13
D13
—
—
—
—
Dxx3
D3
D3
D3
Dxx2
Logic 0
D2
D2
Dxx1
Logic 1
D1
D1
Dxx0
OVR
OVR
D0
Comments
11-bit data (D[13:3]) and OVR come
on ADC output pins
13-bit data (D[13:1]) and OVR come
on ADC output pins
14-bit data comes on ADC output
pins
ANALOG INPUT
The analog input consists of a switched-capacitor-based differential sample-and-hold architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 1.15 V, available on the
VCM pin. For a full-scale differential input, each input pin (INP, INM) must swing symmetrically between VCM +
0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing.
The input sampling circuit has a high 3-dB bandwidth that extends up to 500 MHz when a 50-Ω source drives the
ADC analog inputs.
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This configuration improves the
common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each
input pin is recommended to damp out ringing caused by package parasitics.
Spurious-free dynamic range (SFDR) performance can be limited because of several reasons (such as the effect
of sampling glitches, sampling circuit nonlinearity, and quantizer nonlinearity that follows the sampling circuit).
Depending on the input frequency, sampling rate, and input amplitude, one of these metrics plays a dominant
part in limiting performance. At very high input frequencies, SFDR is determined largely by the device sampling
circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity typically limits performance.
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Glitches are caused by opening and closing the sampling switches. The driving circuit should present a low
source impedance to absorb these glitches, otherwise these glitches may limit performance. A low impedance
path between the analog input pins and VCM is required from the common-mode switching currents perspective
as well. This impedance can be achieved by using two resistors from each input terminated to the common-mode
voltage (VCM).
The ADS4449 includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The R-C component values are also optimized to support high input
bandwidth (up to 500 MHz). However, using an external R-LC-R filter (refer to Figure 48, Figure 49, Figure 50,
Figure 51, and Figure 55) improves glitch filtering, thus further resulting in better performance.
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched source impedance. In doing so, the ADC input impedance must be considered. Figure 45,
Figure 46, and Figure 47 show the impedance (ZIN = RIN || CIN) at the ADC input pins.
XINP(1)
RIN
ZIN(2)
CIN
XINM(1)
(1) X = A, B, C, or D.
(2) ZIN = RIN || (1 / jωCIN).
Figure 45. ADC Equivalent Input Impedance
1
6
0.8
Differential Input Capacitance, Cin (pF)
Differential Input Resistance, Rin (kΩ)
0.9
0.7
0.6
0.5
0.4
0.3
4
3
2
1
0.2
0.1
100
5
200
300
Frequency (MHz)
400
500
0
100
G037
Figure 46. ADC Analog Input Resistance (RIN) vs
Frequency
200
300
Frequency (MHz)
400
500
G038
Figure 47. ADC Analog Input Capacitance (CIN) vs
Frequency
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Driving Circuit
Two example driving circuits with a 50-Ω source impedance are shown in Figure 48 and Figure 49. The driving
circuit in Figure 48 is optimized for input frequencies in the second Nyquist zone (centered at 185 MHz), whereas
the circuit in Figure 49 is optimized for input frequencies in third Nyquist zone (centered at 310 MHz).
Note that both drive circuits are terminated by 50 Ω near the ADC side. This termination is accomplished with a
25-Ω resistor from each input to the 1.15-V common-mode (VCM) from the device. This architecture allows the
analog inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals.
50 :
T1
T2
0.1 PF
10 :
INP
25 :
Band-Pass Filter
Centered at
f0 = 185 MHz
BW = 125 MHz
25 :
82 nH
RIN
10 pF
CIN
0.1 PF
25 :
25 :
INM
1:1
1:1
10 :
0.1 PF
VCM
Device
Figure 48. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies
in the Second Nyquist Zone
50 :
T1
T2
0.1 PF
10 :
INP
25 :
Band-Pass Filter
Centered at
f0 = 310 MHz
BW = 125 MHz
25 :
27 nH
RIN
10 pF
CIN
0.1 PF
25 :
25 :
INM
1:1
1:1
0.1 PF
10 :
VCM
Device
Figure 49. Driving Circuit for a 50-Ω Source Impedance and Input Frequencies
in the Third Nyquist Zone
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TI recommends terminating the drive circuit by a 50-Ω (or lower) impedance near the ADC for best performance.
However, in some applications higher impedances be required to terminate the drive circuit. Two example driving
circuits with 100-Ω differential termination are shown in Figure 50 and Figure 51. In these example circuits, the
1:2 transformer (T1) is used to transform the 50-Ω source impedance into a differential 100 Ω at the input of the
band-pass filter. In Figure 50, the parallel combination of two 68-Ω resistors and one 120-nH inductor and two
100-Ω resistors is used (100 Ω is the effective impedance in pass-band) for better performance.
50 :
T1
0.1 PF
T2
10 :
INP
68 :
Band-Pass Filter
Centered at
f0 = 185 MHz
BW = 125 MHz
25 :
100 :
120 nH
82 nH
RIN
10 pF
CIN
0.1 PF
100 :
68 :
25 :
10 :
1:2
INM
0.1 PF
1:1
VCM
Device
Figure 50. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies
in the Second Nyquist Zone
50 :
T1
T2
0.1 PF
10 :
INP
25 :
50 :
Band-Pass Filter
Centered at
f0 = 310 MHz
BW = 125 MHz
27 nH
RIN
10 pF
CIN
0.1 PF
50 :
25 :
10 :
1:2
1:1
0.1 PF
INM
VCM
Device
Figure 51. Driving Circuit for a 100-Ω Source Impedance and Input Frequencies
in the Third Nyquist Zone
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Using High SNR Mode Register Settings
The HIGH SNR MODE register settings can be used to further improve the SNR. However, there is a trade off
between improved SNR and degraded THD when these settings are used. These settings shut down the internal
spectrum-cleaning algorithm, resulting in THD performance degradation. Figure 52 and Figure 53 show the effect
of using HIGH SNR MODE. SNR improves by approximately 1 dB and THD degrades by 3 dB.
0
0
FIN = 170 MHz
SFDR = 93 dBc
SNR = 69.1 dBFS
SINAD = 69 dBFS
THD = 89 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
FIN = 170 MHz
SFDR = 89 dBc
SNR = 70.1 dBFS
SINAD = 70 dBFS
THD = 86 dBc
0
25
50
75
100
−120
125
Frequency (MHz)
0
25
50
75
Frequency (MHz)
G036
Figure 52. FFT (Default) at 170 MHz
100
125
G037
Figure 53. FFT with High SNR Mode at 170 MHz
Figure 54 shows SNR versus input frequency with and without these settings.
72
Default
HIGH SNR MODE Enable
71
70
SNR (dBFS)
69
68
67
66
65
64
40
90
140
190
240
290
340
Input Frequency (MHz)
390
440
490
G038
Figure 54. SNR vs Input Frequency with High SNR Mode
To obtain best performance, TI recommends keeping termination impedance between INP and INM low (for
instance, at 50 Ω differential). This setting helps absorb the kickback noise component of the spectrum-cleaning
algorithm. However, when higher termination impedances (such as 100 Ω) are required, shutting down the
spectrum-cleaning algorithm by using the HIGH SNR MODE register settings can be helpful.
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Input Common Mode
To ensure a low-noise, common-mode reference, the VCM pin should be filtered with a 0.1-µF, low-inductance
capacitor connected to ground. The VCM pin is designed to directly bias the ADC inputs (refer to Figure 48 to
Figure 51).
Each ADC input pin sinks a common-mode current of approximately 1.5 µA per MSPS of clock frequency. When
a differential amplifier is used to drive the ADC (with dc-coupling), ensure that the output common-mode of the
amplifier is within the acceptable input common-mode range of the ADC inputs (VCM ± 25 mV).
Clock Input
The ADS4449 clock inputs can be driven differentially with a sine, LVPECL, or LVDS source with little or no
difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95 V using
internal 5-kΩ resistors, as shown in Figure 55. This setting allows the use of transformer-coupled drive circuits for
sine-wave clock or ac-coupling for LVPECL, LVDS, and LVCMOS clock sources (see Figure 56, Figure 57, and
Figure 58).
For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to commonmode noise. TI recommends keeping the differential voltage between clock inputs less than 1.8 VPP to obtain
best performance. A clock source with very low jitter is recommended for high input frequency sampling. Bandpass filtering of the clock source can help reduce the effects of jitter. With a non-50% duty cycle clock input,
performance does not change.
Clock Buffer
LPKG
~ 2 nH
20 Ω
CLKP
CBOND
~ 1 pF
CEQ
RESR
~ 100 Ω
CEQ
5 kΩ
0.95V
LPKG
~ 2 nH
5 kΩ
20 Ω
CLKM
CBOND
~ 1 pF
RESR
~ 100 Ω
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 55. Internal Clock Buffer
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0.1 mF
ZO
CLKP
0.1 mF
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100 W
0.1 mF
ZO
CLKM
0.1 mF
CLKM
(1) RT is the termination resistor (optional).
Figure 56. Differential Sine-Wave Clock Driving
Circuit
Figure 58. LVDS Clock Driving Circuit
0.1 mF
ZO
CLKP
0.1 mF
CLKP
CMOS
Clock Input
150 W
Typical LVPECL
Clock Input
100 W
ZO
VCM
0.1 mF
CLKM
0.1 mF
CLKM
150 W
Figure 59. Typical LVCMOS Clock Driving Circuit
Figure 57. LVPECL Clock Driving Circuit
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Overrange Indication (OVRxx)
After reset, all serial interface register ALWAYS WRITE 1 bits must be set to '1'. Afterwards, 13-bit data are
output on the Dxx13P, Dxx13M to Dxx1P, Dxx1M pins and overrange information is output on the Dxx0P and
Dxx0M pins (where xx = channels A and B or channels C and D).
When the DIS OVR ON LSB bit is set to '1', 14-bit data are output on the Dxx13P, Dxx13M to Dxx0P, Dxx0M
pins without overrange information on the LSB bits.
The OVR timing diagram (13-bit data with OVR) is shown in Figure 60. In 14-bit mode, OVR is disabled by
setting the DIS OVR ON LSB bit to '1', as shown in Figure 61.
Register bits ALWAYS WRITE 1=1 & DIS OVR ON LSB=0
CLKOUTM
CLKOUTP
DA[13:1]P/M
DB[13:1]P/M
DAB0P, DAB0M
DA[13:1]P/M
DB[13:1]P/M
OVR A
OVR B
Sample N
DA[13:1]P/M
DB[13:1]P/M
OVR A
OVR B
13-BIT OUTPUT
OVER-RANGE
INDICATOR
Sample N+1
Figure 60. 13-Bit Data With OVR
Register bits ALWAYS WRITE 1=1 & DIS OVR ON LSB=1
CLKOUTM
CLKOUTP
DA[13:0]P/M
DB[13:0]P/M
DA[13:0]P/M
DB[13:0]P/M
Sample N
DA[13:0]P/M
DB[13:0]P/M
14-BIT OUTPUT
Sample N+1
Figure 61. 14-Bit Mode
Normal overrange indication (OVR) shows the event of the ADS4449 digital output being saturated when the
input signal exceeds the ADC full-scale range. Normal OVR has the same latency as digital output data.
However, an overrange event can be indicated earlier (than normal latency) by using the fast OVR mode. The
fast OVR mode (enabled by default) is triggered seven clock cycles after the overrange condition that occurred at
the ADC input. The fast OVR thresholds are programmable with the FAST OVR THRESH PROG bits (refer to
Table 4, register address C3h). At any time, either normal or fast OVR mode can be programmed on the Dxx0P
and Dxx0M pins.
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GAIN FOR SFDR AND SNR TRADE-OFF
The ADS4449 includes gain settings that can be used to obtain improved SFDR performance. The gain is
programmable from 0 dB to 6 dB (in 0.5-dB steps) using the DIGITAL GAIN CH X register bits. For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 7.
Table 7. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
Default after reset
2
1
Fine, programmable
1.78
2
Fine, programmable
1.59
3
Fine, programmable
1.42
4
Fine, programmable
1.26
5
Fine, programmable
1.12
6
Fine, programmable
1
SFDR improvement is achieved at the expense of SNR; for each gain setting, SNR degrades by approximately
0.5 dB to 1 dB. SNR degradation is diminished at high input frequencies. As a result, fine gain is very useful at
high input frequencies because SFDR improvement is significant with marginal degradation in SNR. Therefore,
fine gain can be used to trade-off between SFDR and SNR.
After a reset, the gain function is disabled. To use fine gain:
• First, program the DIGITAL ENABLE bits to enable digital functions.
• This setting enables the gain for all four channels and places the device in a 0-dB gain mode.
• For other gain settings, program the DIGITAL GAIN CH X register bits.
DIGITAL OUTPUT INFORMATION
The ADS4449 provides 14-bit digital data for each channel and two output clocks in LVDS mode. Output pins are
shared by a pair of channels that are accompanied by one dedicated output clock.
DDR LVDS Outputs
In the LVDS interface mode, the data bits and clock are output using LVDS levels. The data bits of two channels
are multiplexed and output on each LVDS differential pair of pins; see Figure 62 and Figure 63.
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CLKOUTxxP,
CLKOUTxxM
Dxx0P,
Dxx0M
Dxx1P,
Dxx1M
Dxx2P,
Dxx2M
14-Bit Output
Dxx12P,
Dxx12M
Dxx13P,
Dxx13M
Device
NOTE: xx = channels A and B or C and D.
Figure 62. DDR LVDS Interface
CLKOUTABM
CLKOUTABP
DAB[13:0]P,
DAB[13:0]M
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
Sample N
DA[13:0]P,
DA[13:0]M
DB[13:0]P,
DB[13:0]M
DA[13:0]P,
DA[13:0]M
Sample N + 1
DB[13:0]P,
DB[13:0]M
Sample N + 2
CLKOUTCDM
CLKOUTCDP
DCD[13:0]P,
DCD[13:0]M
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
Sample N
DC[13:0]P,
DC[13:0]M
DD[13:0]P,
DD[13:0]M
DC[13:0]P,
DC[13:0]M
Sample N + 1
DD[13:0]P,
DD[13:0]M
Sample N + 2
Figure 63. DDR LVDS Interface Timing Diagram
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LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 64. After reset, the buffer presents an
output impedance of 100 Ω to match with the external 100-Ω termination.
The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits (refer to Table 4, register address 01h).
The buffer output impedance behaves similar to a source-side series termination. By absorbing reflections from
the receiver end, the source-side termination helps improve signal integrity.
VDIFF(high)
High
Low
OUTP
External
100-W Load
OUTM
1.1 V
ROUT
VDIFF(low)
Low
High
Figure 64. LVDS Buffer Equivalent Circuit
Output Data Format
The ADS4449 transmits data in binary twos complement format. In the event of an input voltage overdrive, the
digital outputs go to the appropriate full-scale level. For a positive overdrive, the output code is 3FFh. For a
negative input overdrive, the output code is 400h.
BOARD DESIGN CONSIDERATIONS
For evaluation module (EVM) board information, refer to the ADS4449 EVM User's Guide (SLAU455).
Grounding
A single ground plane is sufficient to provide good performance, as long as the analog, digital, and clock sections
of the board are cleanly partitioned. See the ADS4449 EVM User's Guide (SLAU455) for details on layout and
grounding.
50
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Product Folder Links: ADS4449
ADS4449
www.ti.com
SBAS603 – APRIL 2013
DEFINITION OF SPECIFICATIONS
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as an
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate, unless otherwise noted.
Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a
least-squares curve fit of that transfer function, measured in units of LSBs.
Gain Error: Gain error is the deviation of the ADC actual input full-scale range from the ideal value. Gain error is
given as a percentage of the ideal input full-scale range. Gain error has two components: error as a result of
reference inaccuracy and error as a result of the channel. Both errors are specified independently as EGREF and
EGCHAN.
To a first-order approximation, the total gain error of ETOTAL is approximately EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) × fS ideal to (1 + 0.5 / 100) × fS ideal.
Offset Error: Offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. The coefficient is calculated by dividing the
maximum deviation of the parameter across the TMIN to TMAX range by the difference of TMAX – TMIN.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all other spectral components, including noise (PN) and distortion (PD) but excluding dc.
SINAD = 10Log10
PS
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
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51
PACKAGE OPTION ADDENDUM
www.ti.com
30-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ADS4449IZCR
ACTIVE
NFBGA
ZCR
144
168
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS4449I
ADS4449IZCRR
ACTIVE
NFBGA
ZCR
144
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
ADS4449I
ADS4449IZCRT
PREVIEW
NFBGA
ZCR
144
250
TBD
Call TI
Call TI
-40 to 85
ADS4449I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
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