DP83856B DP83856B 100Mb/s Repeater Information Base Literature Number: SNLS029A N DP83856B 100 Mb/s Repeater Information Base October 1997 Features The DP83856B 100 Mb/s Repeater Information Base is designed specifically to meet the management demands of today's high speed Ethernet networking systems. • Supports up to 16 DP83850 Repeater Interface Controllers (192, 100Mb ports on one segment) • Fully IEEE 802.3u clause 30 compatible • Network management statistics processed on a per activity (per packet) basis • Programmed I/O interface for statistics reporting • Uses external SRAM to maintain per port network management statistics counters • Single interrupt acknowledgment provides report on all per port SRAM based and P83856B based statistics • Parallel register interface to CPU (16-bit) • Allows indirect access to the DP83850 Repeater Interface Controller and DP83840 Physical Layer Device serial registers through a parallel register interface • 132 pin PQFP ol e The DP83856B simplifies design of managed multiport repeaters. Used in conjunction with up to 16 DP83850s it enables a repeater system to become a single managed entity that is fully compatible with the IEEE 802.3u clause 30 management requirements. te General Description The DP83856B device incorporates all the necessary functions and counters for collecting network statistics. Information is gathered on a per-packet, per-port basis: the port which is receiving the packet is the active port for statistics collection. bs System Diagram Man agement CPU Management I/O Device/s Management Memory/Cod e O CPU Bus DP83856B Inter Repeater Bus, TX Bus and Seri al Management Bus Si gnals DP83850 100 Mb/s Repeater Interface Controller 100 Mb/s PHY #1 100 Mb/s PHY #2 Statistics SRAM 100 Mb/s Repeater Information Base 100 Mb/s PHY #12 DP83850 100 Mb/s Repeater In terface Controller 100 Mb/s P HY #13 100 Mb/s PHY #14 100 Mb/s PHY #24 TRI-STATE is a registered trademark of National Semiconductor corporation. 1997 National Semiconductor Corportation www.national.com DP83856B 100 Mb/s Repeater Information Base PRELIMINARY Cascaded DP83850 #15 Cascaded DP83850 #1 Local DP83850 #0 TXD[3:0], T X_ER, TX_RDY, 2 ol e Source Address Latch Frames Octet s Source Ad dr. SA Changes F rameToo Long FCS Alig nment Runt s VeryLon gEven ts Symbol Co de Violat ions Data Rate Mismatches Notified By DP83850 Octet Derived Carr ier Derived Nibble, Octet, Collision, FC, & Netw ork Utilisation Counters SFD Detect Statistics G eneration 100 Mb/s Repeater Information Base DP83856 CPU Registers (128 words) Data Address SRAM Interface SRAM Arbiter Interrupt Generation & Control CPU Interface te Addr/Data -RST LC (25MHz) -SDV RDIO RDC Register Interface bs O RRDIR -SOE SR-W -SCS SD[15:0] SA[12:0] -CINT CR-W -CCS -CRDY CD[15:0] C A[7:1] 8K x 16 SRAM (20ns) Management CPU Interface Block Diagram -IR_COL, -IRD_V, MD[3:0], M_CK, -M_DV, -M_ER Inter Repeater Bus www.national.com Pin Connection Diagram 2.0 Pin Description 2.1 CPU Interface 2.2 SRAM Interface 2.3 Transmit Bus and Management Bus 2.4 MII Interface 2.5 Test Interface 2.6 Miscellaneous 2.7 Pin Type Designation 3.0 Functional Description 3.1 Statistics Generation 3.2 SRAM Interface 3.3 SRAM Arbiter 3.4 Interrupt Generation and Control 3.5 MII Register Interface 3.6 CPU Register Block 4.0 Registers 4.1 Register Memory Map 4.2 Configuration Register 4.3 Interrupt Register 4.4 SRAM Interface Register 4.5 MII Management Interface Register 4.6 SRAM Write Data Register 4.7 MII Write Data Register 4.8 Device ID Register 4.9 SRAM Read Data Registers 4.10 Carrier Count Register 4.11 Oct_Nib Count Register 4.12 Network Counters 4.13 MII Read Data Registers 5.0 A.C. & D.C. Specifications 5.1 D.C. Specifications 5.2 A.C. Specifications O bs ol e 1.0 te Table of Contents 6.0 System Considerations 6.1 Lost MII Read Error Status Events 6.2 Sixty-Three Byte Packet Counting 6.3 Initial Packet Logging 6.4 Random Activity On Management Interface 6.5 Symbol Error During Packet Count 3 www.national.com GND VCC 18 19 C D0 C D1 20 21 C D2 C D3 22 GND VCC GND VCC 32 33 C D8 C D9 34 CD 10 CD 11 CD 12 CD 13 GND VCC CD 14 CD 15 -M_ER -NAN D_E -NAND _O NC 118 117 M_C K -M_D V 121 120 119 VCC GN D 12 4 12 3 1 22 VC C GND 2 1 MD2 MD3 -RST -IR D_V 4 3 MD0 MD1 TXD0 LC 6 1 28 GND TXD1 8 7 1 27 126 125 TXD2 VC C 10 9 NC NC TX_RD Y TXD3 12 11 35 36 37 38 39 132 pin PQFP (top view) 40 41 42 43 44 45 111 GN D RES1 RDIO VCC 109 108 RES2 SA12 107 106 VCC GN D 105 104 SA11 SA10 103 102 101 SA9 VCC GN D SA8 99 98 97 96 SA7 SA6 95 94 VCC GN D 93 92 SA3 SA2 91 90 SA1 SA0 89 SA5 SA4 46 88 SR-W -SCS 47 48 87 86 -SOE VCC 49 50 85 84 GN D NC 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 CA5 CA4 GND VC C CA3 CA2 CA1 -CRDY GND VC C SD15 SD14 GND VC C SD13 SD12 SD11 SD10 SD9 SD8 SD7 SD6 GND VC C SD5 SD4 SD3 SD2 SD1 SD0 O VCC RRD IR RDC 100 NC -CCS GND NC NC -IR_C OL TX_ER 100 Mb/s Repeater Information Base CA7 CA6 GND VCC 132 13 1 13 0 12 9 -TEST_EN -TEST_ H_L 5 -TSTATE DP83856B DP83856 bs -C IN T CR -W 16 15 14 13 27 28 29 30 31 -SDV 115 114 113 112 110 26 C D6 C D7 116 te VCC C D5 23 24 25 ol e C D4 GND 17 1.0 Pin Connection Diagram Order Number DP83856BVF NS Package Number VF132A 4 www.national.com 2.0 Pin Descriptions 2.1 CPU Interface The CPU interface pins are a set of generic interface signals designed to accommodate many different CPU types with minimal external logic. The data interface is 16-bits wide and does not provide any steering capabilities. Furthermore, all accesses must be aligned on 16-bit boundaries, as indicated in the CPU Register map section 4.0. Type Active Description -CINT O/Z, L Low -CRDY O/Z, L Low -CCS I Low CPU Interrupt: Indicates that the DP83856B has at least one interrupt pending. The -CINT signal will remain active until the CPU reads the Interrupt Register. It is software’s responsibility to keep track of multiple interrupts pending, and service all of the interrupts. CPU Ready: Indicates that the DP83856B is ready to terminate the current cycle. The DP83856B asserts -CRDY on writes once it has strobed the data into its write data holding register. The DP83856B asserts -CRDY on reads once it has strobed data into its read data output register. CPU Chip Select: Chip select for internal DP83856B registers. Generated by external logic as an address decode of the DP83856B register space. -CCS must remain valid for the entire cycle. CPU Read-Write: Read/Write strobe for DP83856B internal registers. Read = 1, Write = 0. CPU Address [7:1]: Address bus for DP83856B register accesses. The DP83856B latches the address for internal use within 45ns of -CCS being asserted. CPU Data [15:0]: 16-bit data bus for DP83856B register accesses. CD[15:0] correspond to the low 16-bits of data on the CPU. The DP83856B implements Big Endian convention for data storage. All CPU register accesses should be 16-bit accesses aligned on 16-bit boundaries. CA[7:1] I - I - I/O/Z, M - bs CD[15:0] ol e CR-W te Signal Name 2.2 SRAM Interface O The SRAM interface pins are used to connect the DP83856B to a fast (20ns) external SRAM. The DP83856B supports up to an 8K x 16 bit SRAM configuration. Signal Name Type Active Description SA[12:0] O/Z, L - SD[15:0] I/O/Z/P, L - SR-W O/Z,L - -SCS O/Z, L Low -SOE O/Z, L Low SRAM Address [12:0]: The SRAM address bus should be directly connected to the fast external SRAM's address inputs. SRAM Data [15:0]: The SRAM data bus should be directly connected to the fast external SRAM's data pins. SRAM Read-Write: Should be directly connected to the fast external SRAM's write enable pin. Read = 1, Write = 0. SRAM Chip Select: Should be directly connected to the fast external SRAM's chip select pin. SRAM Output Enable: Should be directly connected to the fast external SRAM's (active low) output enable pin. 5 www.national.com 2.3 Transmit Bus and Management Bus Type Active Description TXD[3:0] I - TX_RDY I High TX_ER I High - IR_COL I Low - IRD_V I Low Transmit Data [3:0]: Transfers data from a local DP83850 to the DP83856B. TXD[3:0] is synchronous to the local clock signal LC, and is framed by the transmit ready signal TX_RDY. Transmit Data Ready: Asserted by a local DP83850 when non-idle symbols are repeated on any of the DP83850’s output ports. The DP83856B uses this signal as a framing signal for transmit data, transmit error, management data, management error, collision, data valid, and as an enable for carrier and network utilization timing. Transmit Data Error: Asserted by a local DP83850 when a transmit error occurs. The DP83856B monitors this signal to determine if the current reception was a Symbol Code violation error. TX_ER is synchronous to the local clock signal LC. Inter Repeater Collision: Asserted by any (all) DP83850s in the system which are currently experiencing a collision. The DP83856B monitors this signal during TX_RDY valid, and uses the information in statistics processing and collision counting. Inter Repeater Data Valid: Asserted by any DP83850 in the system which has won the Inter Repeater Bus arbitration and is transmitting valid data symbols. The DP83856B monitors this line at the beginning of the frame to establish whether the frame is a false carrier event. If TX_RDY is valid and -IR_DV is invalid when the DP83856B samples the -IR_DV line, then a false carrier event is counted. Management Data [3:0]: Data which is sourced by any DP83850 in the system which has won the Inter Repeater Bus arbitration. This data is synchronous to the management clock M_CK, and is framed by the transmit ready signal TX_RDY. The DP83856B uses this data to determine the source of the current data stream (DP83850 number and Port number). Management Data Valid: Asserted by any DP83850 in the system which has won the Inter Repeater Bus arbitration when it places valid data on MD[3:0]. The DP83856B monitors this line when TX_RDY is valid to determine when to latch the RIC and port number for the current reception. M_DV is synchronous to M_CK. Management Clock: All data transfers on the management bus are synchronized to the rising edge of this clock. M_CK is the reference 25MHz clock for determining the active DP83850, port, and elasticity buffer errors for the current packet reception. M_CK is sourced by any DP83850 in the system which has won the Inter Repeater Bus arbitration. Management Error: Asserted by any DP83850 in the system which has won the Inter repeater Bus arbitration when a data rate mismatch error occurs (elasticity buffer over/underrun). The DP83856B monitors this line during TX_RDY valid to determine if the current frame contains a data rate management error. -M_ER is synchronous to M_CK. ol e I - bs MD[3:0] te Signal Name I Low M_CK I - - M_ER I Low O - M_DV 6 www.national.com 2.4 MII Interface Type Active Description RDC O/Z, L - RDIO I/O/Z, L - RRDIR O/Z, L High - SDV O/Z, L Low Register Data Clock: A 2.5MHz clock which is continuously output from the DP83856B. Used to synchronize data transfers on the serial MII register bus. Register Data I/O: Serial MII register data signal. Used to transfer data to and from the DP83856B on MII register accesses. This signal should be buffered onto the backplane, using the RRDIR signal as a direction control for the buffer. The buffer does not require a tri-state enable. RIB Register Direction: Serial MII Register Direction pin to drive an external buffer. The buffer should default to READ, and toggle to WRITE only when the DP83856B is initiating an MII register access. 0 = MII Slave (DP83850 or PHY) drives RDIO 1 = DP83856B drives RDIO Serial Data Valid: Indicates that a valid MII access is in progress. It is asserted one half clock prior to the start of the cycle and remains valid for one half clock after the cycle is complete. te Signal Name Signal Name - TSTATE - TEST_EN Type Active Description I/P Low I/P Low I/P Low Tri-State: Pulling this pin low puts the DP83856B into a test mode that tristates all outputs except -NAND_E and -NAND_O. This allows an external tester to drive all the outputs of the DP83856B. Test mode Enable High/Low output test: Forces the DP83856B's outputs to the High or Low state as defined by the -TEST_H_L pin. This enables testers to check for outputs stuck at High or Low. Test mode output High/Low: When -TEST_EN is taken Low, the DP83856B's output pins (in two groups) are forced into the High or Low state as defined below: O bs - TEST_H_L ol e 2.5 Test Interface -TEST_H_L 0 1 Group 1 Outputs 1 0 Group 2 Outputs 0 1 Group 1 output pin numbers are: 21, 23, 27, 31, 35, 37, 39, 43, 61, 64, 68, 70, 72, 74, 78, 80, 82, 87, 89, 90, 92, 96, 98, 100, 104, 108, 113, 115. - NAND_E O, L Low - NAND_O O, L Low Group 2 output pin numbers are: 20, 22, 24, 30, 34, 36, 38, 42, 44, 65, 69, 71, 73, 75, 79, 81, 83, 88, 91, 93, 97, 99, 103, 105, 114, 116. NAND tree Even inputs output: The logical NAND of all of the even numbered inputs (except the test input -TEST_EN) and -RST. If all of the inputs are High, the output will go Low. If any of the inputs are Low, the output will remain High. NAND tree Odd inputs output: The logical NAND of all of the odd numbered inputs (except the test inputs -TSTATE, -TEST_H_L and LC). If all of the inputs are High, the output will go Low. If any of the inputs are Low, the output will remain High. 7 www.national.com 2.6 Miscellaneous Pins Signal Name Type Active Description LC I - - RST I Low RES1 RES2 O O - Local Clock: Primary clock for DP83856B device. All DP83856B internal state machines run off LC. This clock must be the same local clock used to drive the local DP83850 because the TX signals (to which the DP83856B must be synchronized) are all synchronous to the local clock. Must be a 25.000MHz, 40/60 duty cycle, 50ppm. Reset: The DP83856B is reset when this signal is asserted low. Asserting this signal will cause all DP83856B state machines and registers to enter their reset state. Reserved Output 1: Leave unconnected. Reserved Output 2: Leave unconnected. Description Input buffer. Input buffer with internal pull-up resistor. Output buffer, low drive(4mA). Output buffer with high impedance capability, low drive (4mA). Bi-directional buffer with high impedance capability, low drive (4mA). Bi-directional buffer with high impedance capability, medium drive (12mA). Bi-directional buffer with high impedance capability and pull-up resistor, low drive (4mA). ol e Type I I/P O, L O/Z, L te 2.7 Pin Type Designation I/O/Z, L I/O/Z, M O bs I/O/Z/P, L 8 www.national.com 3.0 Functional Description 3.1.2 Carrier Derived The following sections describe the different functional blocks of the DP83856B 100 Mb/s Repeater Information Base. Referring to the block diagram on page 2 of this datasheet, the DP83856B is used in conjunction with a number of DP83850s, a management CPU and a fast (20ns) 8k x 16 bit SRAM. The DP83856B collects and maintains network management statistics from the connected DP83850s and makes them available to the management CPU. Other statistics are a function of carrier. Carrier derived statistics have a high probability of occurring on activity bursts which do not include a valid SFD. To ensure accurate statistic gathering a carrier based detection scheme is implemented. A nibble counter is used to calculate the length of the carrier, which is used to create the carrier derived statistics. The DP83856B employs 32-bit counters for network utilization, false carrier events, and collisions. All of these counters monitor events for all ports, i.e. they are an aggregate of the total repeater events. Carrier derived statistics DP83856B include: gathered by the Runts Very Long Events (jabber) Network Utilization Repeater False Carrier Events Repeater Collisions (per port collision map obtained from DP83850s) ol e Inputs to the DP83856B Statistic Generation block include the Inter Repeater Bus signals, Management Bus signals and TX BUS signals. These signals provide the data streams necessary to create all the statistics collected by the DP83856B. The DP83856B uses the fast external SRAM to hold statistics for the current packet reception. Statistics for the current receive packet are collected in one of four ways: 3.1.1 Octet Derived te 3.1 Statistics Generation The majority of the statistics are a function of the octet count. Statistics based on octet counts imply that a valid SFD has been detected and an accurate count of the number of data bytes in the packet are available. bs 3.1.3 DP83850 Notified O The DP83856B Statistic Generation module has an SFD detect block, which indicates that a valid SFD has been detected so that the octet counter can be enabled. The Source Address latch is used to store the source address of the current packet, so that a comparison to the previous source address can be made at the end of the packet reception. Octet derived statistics include: For a few of the required statistics the DP83856B has no way of determining the occurrence of that event. These statistics are obtained by notification from the connected DP83850s. DP83850 notified statistics include: Data Rate Mismatches Symbol Code Violations 3.1.4 Collision Counter The 100 RIB has a 32 bit counter which is incremented any time the repeater experiences a collision. This counter is used to keep track of total number of collisions happening on the repeater. Frames Octets FCS Errors Alignment Errors Frames Too Long Source Address Source Address Changes 3.2 SRAM Interface The SRAM interface provides the logic required to communicate with the fast external SRAM. 9 www.national.com The interface between the DP83856B and the fast external SRAM is very straightforward. The fast external SRAM is a dedicated block of memory directly accessed only by the DP83856B. The DP83856B provides the address capability for 8Kx16 bits of SRAM. Figure 1 shows a memory map for the 8Kx16 configuration. For each port there are 11 statistics defined which are stored in SRAM. Ten of these statistics are 32 bit values, and one is a 48 bit value (Last Source Address). hardware implementation. All other statistics are stored in big endian mode. The DP83856B can be directly connected to the SRAM; there is no need for buffering between the DP83856B and the SRAM. The DP83856B requires fast SRAM with a maximum access time of 20ns. The SRAM interface block contains the address and data multiplexers to select between CPU and Statistic Update accesses. Data is multiplexed under control of the SRAM arbiter . Last Source Address is stored in little endian mode as two 32 bit values for simplicity of 13FF DP83850 #15 1E00 13E0 DP83850 #14 1C00 13C0 DP83850 #13 1A00 DP83850 #12 1800 1380 DP83850 #11 1600 1360 DP83850 #10 1400 Unused Reserved U nused Reserved ol e 13A0 Reserved U nused U nused Reserved Po rt 11 Po rt 10 1340 DP83850 #9 1200 Port 9 1320 Port 8 bs DP83850 #8 1000 1300 DP83850 #7 0E00 12E0 DP83850 #6 0C00 O 0A00 Port 6 12A0 1260 STAT 13 Reserved - Mid Lo Last SA 12F6 Reserved 12F4 Invalid Symbol Data Rate Mismatch Very Long 12EE 12EC 12EA Runt Count Frame Too Long Align Count 12E6 Hi Hi 12F8 12F0 Hi Lo Last SA 12F2 Hi Lo Lo Hi Lo Hi Lo Hi Lo Hi Lo Hi Lo Hi Lo Hi FC S Cou nt Lo Hi Port 2 12E4 SA Change Hi Lo DP83850 #1 Port 1 1220 DP83850 #0 12FA STAT 14 Reserved Lo Lo 1240 0200 STAT 15 Reserved 12E8 Port 3 DP83850 #2 0400 12FC Port 4 1280 DP83850 #3 0600 12FE Port 5 DP83850 #4 0800 0000 Port 7 12C0 DP83850 #5 12FF te 1FFF 1200 Port 0 12E2 12E0 Octet Count Frame Count Hi Lo Hi Figure 1. Memory Map for the DP83856 Statistics SRA M 10 www.national.com Layer Device registers (read & write) based on requests from the CPU. This interface uses the IEEE 802.3u clause 22 MII compliant serial interface protocol. 3.3 SRAM Arbiter The SRAM arbiter controls the SRAM data multiplexers depending on what type of access is being performed and creates all of the control signals for the SRAM, ensuring the timing is correct. There are three events that result in SRAM arbitration: The MII Register Interface eliminates the need for the CPU to talk directly to the DP83850 and Physical Layer Device registers. The amount of spare management CPU processing bandwidth is therefore increased. - End of packet request- Runt (Statistic Update State Machine) - End of packet request- Legal Length or greater (Statistic Update State Machine) - CPU request (read or write) te MII Protocol for performing reads and writes are as follows: READ <01><10><AAAAA><RRRRR><z0><xxxx xxxx xxxx xxxx> where <01> is a start bit sequence, <10> is a read opcode, <AAAAA> is the device address (up to 32 devices), and <RRRRR> is the register address (up to 32 registers). <z0> is a 2-bit turn-around time used to avoid contention on RDIO. During the first bit time no device actively drives RDIO (all devices are in a high-impedance state). During the second bit time, the slave device will drive a 0 onto RDIO. Finally, <xx ... xx> is 16 bits of data. ol e The arbiter assigns highest priority to EOP-runts and lowest priority to CPU requests. For single statistic reads, the arbiter produces two 16-bit locked read cycles on the SRAM to form the 32-bit value. For block reads the SRAM arbiter re-arbitrates after each 32-bit SRAM read (two 16-bit locked reads) to allow any higher priority event access to the SRAM. Writes to the SRAM must always be word (16-bit) accesses: byte writes are not supported. The CPU provides the opcode, type of access (read or write), register address, and device ID to the MII Interface Register, and then asserts a start command by writing a 1 to bit 0 (MII_ACC) of the Configuration Register. 3.4 Interrupt Generation and Control There are four events that can generate an interrupt: SRAM access complete MII Register access complete Invalid MII register read DP83856B error bs - O The DP83856B provides one interrupt line that is shared for all interrupts. The interrupt is an active low, level sensitive signal. Interrupts are generated based on a valid event occurring with the appropriate mask bit set. Interrupts are cleared by reading the interrupt register. The "Invalid MII register read" interrupt is generated based on the DP83856B detecting an error while performing a read access. The DP83856B looks for a leading 0 on reads; if it does not see it, it flags the read as invalid and generates the interrupt. WRITE <01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx> where <01> is a start bit sequence, <01> is a write opcode, <AAAAA> is the device address (up to 32 devices), and <RRRRR> is the register address (up to 32 registers). <10> is a 2-bit turn-around. For this turn-around, the DP83856B will drive a 1 for the first bit time and a zero for the second bit time. Finally, <xx ... xx> is 16 bits of data. Refer to the IEEE 802.3u standard for more details on the MII interface, its function and timing. 3.6 CPU Register Block The CPU register block provides the system management CPU access to all of the data in the DP83856B, SRAM and connected DP83850s and Physical Layer Devices 3.5 MII Register Interface The MII register interface block is a state machine that performs accesses to DP83850 and Physical 11 www.national.com All register accesses are word (16-bit) wide: byte access is not supported. The addresses given in the tables below assume that the user has connected the DP83856B to a management CPU in the normal 16-bit manner with address bits A1 through A7 from the CPU connected to bits CA1 to CA7 on the DP83856B. The addresses are thus the offset from the base address at which the DP83856B is located in the system. 4.0 Registers All the DP83856B registers are directly addressable by the system management CPU. Although some bits in the Configuration Register have been allocated to a register paging scheme, these are not currently used (they're there for future expansion) and should always be set to zero. 4.1 Register Memory Map Access R/W R/W R/W R/W R/W R/W R only R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - ol e te Register Configuration Register Interrupt Reserved SRAM Interface MII Management Interface SRAM Write Data MII Write Data Device ID Frame Count Hi Read Frame Count Lo Read Octet Count Hi Read Octet Count Lo Read Source Address Change Count Hi Read Source Address Change Count Lo Read FCS Error Count Hi Read FCS Error Count Lo Read Alignment Error Count Hi Read Alignment Error Count Lo Read Frame Too Long Count Hi Read Frame Too Long Count Lo Read Runt Count Hi Read Runt Count Lo Read Very Long Event Count Hi Read Very Long Event Count Lo Read Data Rate Mismatch Count Hi Read Data Rate Mismatch Count Lo Read Invalid Symbol Count Hi Read Invalid Symbol Count Lo Read Reserved Reserved Source Address Hi Read Source Address Mid Read Source Address Lo Read Reserved Reserved Carrier Count Register Oct_Nib Count Register Reserved O bs Address 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h - 7Eh 80h 82h 84h - 8Eh 12 www.national.com Register Memory Map Continued Access R/W R/W R/W R/W R/W R/W R only te R only R only R only R only R only R only - O bs A2h A4h A6h A8h AAh ACh AEh B0h - 1FEh Register Repeater Collisions Hi Read Repeater Collisions Lo Read Network Utilization Hi Read Network Utilization Lo Read False Carrier Hi Read False Carrier Lo Read Reserved MII Read Data / Port 0-11 Short Event Hi Block Read Data DP83850 Port 0-11 Short Event Lo Block Read Data DP83850 Port 0-11 Late Event Hi Block Read Data DP83850 Port 0-11 Late Event Lo Block Read Data DP83850 Port 0-11 Collision Hi Block Read Data DP83850 Port 0-11 Collision Lo Block Read Data DP83850 Port 0-11 Auto-Partitions Block Read Data Reserved Reserved ol e Address 90h 92h 94h 96h 98h 9Ah 9Ch - 9Eh A0h 13 www.national.com 4.2 Configuration Register Address: 00h Reset: All bits cleared to zero. D2 SR_ACC SR_ACC_TYPE Access Description R/W 0: DP83856B writes 0 after register access completes. 1: CPU initiates register access by writing 1 R/W R/W This bit indicates when the current DP83850 or Physical Layer device register access is complete. 0: DP83856B writes 0 after SRAM access completes. 1: CPU initiates SRAM access by writing 1. This bit indicates when the current SRAM access is complete. 0: Perform Single Access 1: Perform Block Access (Reads Only) All SRAM based statistics will be loaded into SRAM (CPU Addr. 10h 40h) te D1 Bit Name MII_ACC Note: If you set this bit to a 1, the STAT # field and the R/W bit in the SRAM I/F Register will be ignored (Addr 06h, bits 4:0 and 7 respectively). 0: Statistics gathering disabled 1: Statistics gathering enabled ol e Bit D0 MEN D(4:7) PAGE_SEL R/W R/W This bit enables management statistics gathering. These bits define which page of the register map the CPU is pointing to. Allows for 16 pages x 256 word registers. bs D3 Always write 0 for compatibility with later versions of DP83856B. Reserved R/W O D(8:15) Note: The Page bits are not implemented in current version. Write: 0 Read: Undefined. 14 www.national.com 4.3 Interrupt Register Address: 02h Reset: All bits cleared to zero. Access R D1 SR_ACC_STS R D2 RIBERR_STS R D3 MII_RD_ERR_STS R D4 MII_INT_MSK R/W D5 SR_ACC_MSK R/W D6 RIBERR_MSK R/W D7 MII_RD_ERR_MSK R/W D8 Reserved R/W R/W This bit indicates the occurrence of an MII register read error. 0: Disable -CINT signal. 1: Enable -CINT signal. This bit is a global enable for the -CINT signal. It has NO effect on the status bits. Write: 0 Read: Undefined. O bs D(9:15) INT_EN Description 1: MII access complete Interrupt asserted. Cleared by read of register. Writes ignored. 1: SRAM access complete Interrupt asserted. Cleared by read of register. Writes ignored. 1: DP83856B error Interrupt asserted. Cleared by read of register. Writes ignored. 1: MII (MII) register read error Interrupt asserted. Cleared by read of register. Writes ignored. 0: Mask MII access complete Interrupt. 1: Enable MII access complete Interrupt. 0: Mask SRAM access complete Interrupt. 1: Enable SRAM access complete Interrupt. 0: Mask DP83856B error Interrupt. 1: Enable DP83856B error Interrupt. 0: Mask MII Register Error Interrupt. 1: Enable MII Register Error Interrupt. te Bit Name MII_INT_STS ol e Bit D0 15 www.national.com 4.4 SRAM Interface Register Address: 06h Reset: All bits cleared to zero. Bit D(0:4) Bit Name STAT_ACC# Access Description R/W These bits set which STATISTIC the SRAM access is destined for. Values are: D(5:6) D7 Reserved R/W_SRAM PORT_ACC# R/W R/W R/W Always Write 0 0: SRAM Write 1: SRAM Read This bit defines whether the current CPU SRAM access is a read or a write. Ignored for block accesses. These bits set which PORT the access is destined for: Valid values are 0h - Bh (12 ports) These bits set which DP83850 the access is destined for. bs D(8:11) ol e te 00h: Frame Count 02h: Octet Count 04h: SA Change Count 06h: FCS Error Count 08h: Alignment Error Count 0Ah: Frame Too Long Count 0Ch: Runt Count 0Eh: Very Long Event Count 10h: Data Rate Mismatch Count 12h: Invalid Symbol Count 14h: Reserved 16h: Source Address Hi 18h: Source Address Lo 1Ah-1Eh: Reserved D(12:15) RIC_ACC# R/W Valid values are 0h - Fh (16 DP83850s) O Note: This register should NOT be accessed while an SRAM access is in progress (If bit D1 of Configuration Register is 1, then do not access this register). 16 www.national.com 4.5 MII Management Interface Register Address: 08h Reset: All bits cleared to zero. Bit D(0:4) D(5:9) Bit Name REG_ADDR DEV_ID D(10:11) OPCODE Access Description R/W These bits set which register the access is destined for. R/W These bits set which DEVICE_ID the access is destined for. R/W Opcode value: Corresponds to the opcodes defined in the MII specification. 01: Extended Addressed Mode Write, 16-bit payload. 10: Extended Addressed Mode Read, 16-bit payload. MII_ACC_TYP R/W MII Access Type: Sets the access type to single or block read:. te D12 Reserved R/W 1: Perform Block Read (DP83850 reads only). All DP83850 based counters will be loaded into registers (Address A0h-ACh). The OPCODE field should be set to 10 for block reads. REG_ADDR is set to register address corresponding to the Port_ShortEvent Counter for the desired port. Write: 0 Read: Undefined. bs D(13:15) ol e 0: Perform Single Access (All Physical Layer device accesses and all DP83850 accesses except DP83850 counters). 4.6 SRAM Write Data Register Address: 0Ah Reset: All bits cleared to zero. Bit Name WR_DATA O Bit D(0:15) Access Description R/W This register contains the data to be written on an SRAM write access. SRAM writes should only be performed during DP83856B initialization. 17 www.national.com 4.7 MII Write Data Register Address: 0Ch Reset: All bits cleared to zero. Bit D(0:15) Bit Name WR_DATA Access Description R/W This register contains the data to be written on an MII register write access. 4.8 Device ID Register Address: 0Eh Reset: All bits cleared to zero. D(4:7) DEVICE ID D(8:15) Reserved Access Description R These bits are the Revision level of the device and are embedded into the DP83856B silicon. Reads 0h for initial revisions. R These bits are a vendor specific code embedded in the DP83856B. Reads 0 for initial revision. R/W Write: 0 Read: Undefined. te Bit Name REV_LEVEL ol e Bit D(0:3) 4.9 SRAM Read Data Registers Addresses: 10h - 40h Reset: All bits cleared to zero. Bit Name SRAM Read Data Access Description R Contains data corresponding to the SRAM location selected. bs Bit D(0:15) O 4.10 Carrier Count Register Address: 80h Reset: All bits cleared to zero. Bit D(0:13) Bit Name Carrier Count D(14:15) Unused Access Description R/W Contains data which is used to preset the carrier counter FOR TEST PURPOSES only. This register can only be written when the MEN bit in the CONFIG register is 0. R/W Write: 0 Read: Undefined. 18 www.national.com 4.11 Oct_Nib Count Register Address: 82h Reset: All bits cleared to zero. Bit Name Oct_Nib Count D(12:15) Unused Access Description R/W Contains data which is used to preset the Octet-Nibble counter FOR TEST PURPOSES only. This register can only be written when the MEN bit in the CONFIG register is 0. R/W Write: 0 Read: Undefined. 4.12 Network Counters Addresses: 90h - 9Ah Reset: All bits cleared to zero. Bit Name Counter Data Access R/W Description Contains data corresponding to the selected counter. Disable the Management function by writing 0 to the MEN, bit D3 in the Configuration Register prior to writing to these counters. ol e Bit D(0:15) te Bit D(0:11) 4.13 MII Read Data Registers bs Addresses: A0h - ACh Reset: All bits cleared to zero. Bit D(15:0) Bit Name MII Data Access Description R Contains read data corresponding to the MII register selected. O For single Physical Layer Management register read accesses and single statistic read accesses to connected DP83850s, the read data appears in data register address A0h. When the DP83856B is instructed to do a block statistics read from a connected DP83850, the block of 7 read values is placed in the registers A0h to ACh. The register’s designations are given in the memory map in section 4.1 above. 19 www.national.com 5.0 A.C. and D.C. Specifications 5.1 D.C. Specifications ICC Parameter Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Minimum TRI-STATE Output Leakage Current Supply Current (Calculated) Conditions Min 3.7 Max Units V V V V 0.4 2.0 0.8 ±150 ±160 µA µA 150 mA te Symbol VOH VOL VIH VIL IIN IOZ 5.2 A.C. Specifications 5.2.1 CPU Read Timing ol e Some timing parameters are shown more than once (both on the same timing diagram, and in different sections) for clarity. T3 CA[7:1] T6 T10 T7 T8 T1 T9 bs -CCS T4 CR-W T5 T2 CD[15:0] O -CRDY T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Description -CCS low to CPU Data valid CPU Data valid to -CRDY low CPU Address hold from -CCS low CR-W hold from -CCS high CPU Data hold from -CCS high CPU Address setup to -CCS low CR-W setup to -CCS low -CCS high between cycles -CCS high to -CRDY high -CCS low to CPU Data driven 20 Min (ns) 10 60 0 0 0 0 100 0 Max (ns) 180 60 20 www.national.com 5.2.2 CPU Write Timing T3 CA[7:1] T6 T8 T11 T9 T4 T12 T7 -CCS CR-W T13 CD[15:0] ol e Description CPU Address hold from -CCS low CR-W hold from -CCS high CPU Address setup to -CCS low CR-W setup to -CCS low -CCS high between cycles -CCS high to -CRDY high -CCS low to -CRDY low -CCS low to CPU Data valid CPU Data hold from -CRDY low bs T3 T4 T6 T7 T8 T9 T11 T12 T13 te -CRDY Min (ns) 60 0 0 0 100 0 Max (ns) 60 180 70 - 5.2.3 MII Slave Timing (DP83856B receiving data on RDIO) T15 T14 T16 T17 T16 T17 O RDC T18 -SDV RRDIR RDIO (slave) T14 T15 T16 T17 T18 Description RDC pulse width RDC falling edge to RRDIR RDIO setup to RDC rising edge RDIO hold from RDC rising edge RDC falling edge to -SDV high Min (ns) 100 0 - 21 Typ (ns) 400 Max (ns) 60 60 www.national.com 5.2.4 MII Master Timing (DP83856B sending data on RDIO) T14 RDC T22 T23 T19 -SDV RRDIR T20 T20 T21 T21 Description RDC pulse width RDC falling edge to -SDV falling edge RDC falling edge to RDIO valid RDC falling edge to RDIO invalid RRDIR rising edge to -SDV falling edge RDC falling edge to -SDV rising edge 5.2.5 TX Bus Timing Min (ns) Typ (ns) 400 0 600 - ol e T14 T19 T20 T21 T22 T23 te RDIO(mstr) Max (ns) 60 60 60 T26 bs T24 T28 T29 T25 T27 LC TX_RDY TX_ER O TXD[3:0] T24 T25 T26 T27 T28 T29 Description TX_RDY setup to LC rising edge TX_RDY hold from LC rising edge TX_ER setup to LC rising edge TX_ER hold from LC rising edge TXD[3:0] setup to LC rising edge TXD[3:0] hold from LC rising edge Min (ns) 9 3 5 2 6 2 22 Typ (ns) Max (ns) - www.national.com 5.2.6 Management Bus Timing M_CK T30 T35 -M_DV T34 T33 -M_ER MD[3:0] 5.2.7 SRAM Read Timing Min (ns) 3 1 1 3 1 1 Typ (ns) Max (ns) - te Description -M_DV setup to M_CK rising edge MD[3:0] setup to M_CK rising edge MD[3:0] hold from M_CK rising edge -M_ER setup to M_CK rising edge -M_ER hold from M_CK rising edge -M_DV hold from M_CK rising edge ol e T30 T31 T32 T33 T34 T35 T32 T31 T41 T36 -SCS T37 T40 -SOE SR-W bs T39 SA[12:0] Addr.1 T38 SD[15:0] Data1 Description -SCS low to -SOE low -SOE low to SA[12:0] valid SA[12:0] valid to SD[15:0] valid (SRAM tsu) SA[12:0] width SA[12:0] invalid to -SOE high -SOE high to -SCS high O T36 T37 1 T38 2 T39 3 T40 4 T41 Notes: 1. 2. 3. 4. T39 Addr.2 T38 Data2 Min (ns) 0 50 0 35 Typ (ns) 20 Max (ns) 30 25 - All SRAM read cycles are Address controlled. SRAM must have a read access time of 20ns or faster. The DP83856B latches data prior to changing the SA[12:0] value. The DP83856B latches data prior to terminating -SOE. 23 www.national.com 5.2.8 SRAM Write Timing T42 -SCS T44 T43 SR-W -SOE T46 SA[12:0] Addr.1 T45 SD[15:0] te Min (ns) 30 10 35 25 15 15 ol e Description -SCS low to SA[12:0] valid SA[12:0] valid to SR-W low SR-W width SD[15:0] valid to SR-W high SR-W high to SA[12:0] invalid SR-W high to SD[15:0] invalid Typ (ns) Max (ns) - O bs T42 T43 T44 T45 T46 T47 T47 Data1 24 www.national.com 5.2.9 Test Mode Timing LC T48 T49 -TSTATE T56 T50 T51 T59 T60 T52 -TEST_EN T57 T58 T53 -TEST_H_L te T54 Group 1 Outputs T55 ol e Group 2 Outputs Min (ns) 20 20 - T59 Description -TSTATE low to Group 1 Outputs Hi-Z -TSTATE low to Group 2 Outputs Hi-Z -TSTATE high to Group 1 Outputs driven -TSTATE high to Group 2 Outputs driven -TEST_EN low setup to LC rising edge -TEST_H_L low setup to LC rising edge -TEST_EN, -TEST_H_L low to Group 1 Outputs high -TEST_EN, -TEST_H_L low to Group 2 Outputs low -TEST_H_L high setup to LC rising edge -TEST_EN low, -TEST_H_L high to Group 1 Outputs low -TEST_EN low, -TEST_H_L high to Group 2 Outputs high -TEST_EN high to Group 1 Outputs undefined T60 -TEST_EN high to Group 2 Outputs undefined - bs T48 T49 T50 T51 T52 T53 T54 T55 T56 T57 O T58 20 - Typ (ns) Max (ns) 25 25 25 25 2 * LC + 0ns 2 * LC + 0ns 2 * LC + 0ns 2 * LC + 0ns 2 * LC + 0ns 2 * LC + 0ns Group 1 output pin numbers are: 21, 23, 27, 31, 35, 37, 39, 43, 61, 64, 68, 70, 72, 74, 78, 80, 82, 87, 89, 90, 92, 96, 98, 100, 104, 108, 113, 115. Group 2 output pin numbers are: 20, 22, 24, 30, 34, 36, 38, 42, 44, 65, 69, 71, 73, 75, 79, 81, 83, 88, 91, 93, 97, 99, 103, 105, 114, 116. 25 www.national.com IEEE 802.3 clause 30 states: "Increment counter by one for each CarrierEvent that meets one of the following two conditions. Only one test need be made. (1) The Activity Duration is greater than ShortEventMaxTime and less than ValidPacketMinTime and the CollisionEvent signal is deasserted (10 Mb operation) or the Collision Count Increment state of the partition state diagram (figure 27-8) has not been entered (100 Mb operation). (2) The OctetCount is less than 64, the ActivityDuration is greater than ShortEventMaxTime and the CollisionEvent signal is deasserted (10 Mb operation) or the Collision Count Increment state of the partition state diagram (figure 27-8) has not been entered (100 Mb operation). ValidPacketMinTime is greater than or equal to 552 bit times and less than 565 bit times. ..." 6.0 System Considerations The following section provides descriptions of issues that should be considered during the design of a DP83856B based system. Please contact your National Semiconductor representative for any questions or concerns regarding these issues. If users have configured the DP83856B Interrupt Register (02h) to enable MII_RD_ERR_STS, and are polling the Interrupt Register after starting an MII register access for this bit to go valid, then it is possible for the event to come in and be cleared prior to the CPU seeing the event. In other words, the clear function can beat the set function, with the result being a lost event. The DP83856B uses definition (1) by setting the upper limit on runts to 564 bits or 141 nibbles. Therefore if the packet activity is greater than 141 nibbles, the DP83856B does not log the activity as a runt. This opens a window for events which are not logged either as a runt or a good/fcs frame. Including 8 octets of preamble/sfd, a minimum size good packet is 72 bytes (8 + 64), or 144 nibbles. Thus, if the frame length is 142 or 143 nibbles (63 bytes + 8 bytes of preamble/SFD), the packet will not be logged. ol e Users often want to check this status bit when an MII register access has completed to ensure the addressed device has responded and the data returned is valid. te 6.1 Lost MII Read Error Status Events bs The solution to this issue is simple, and adds MINIMAL overhead and complexity to the software implementation. Instead of polling the MII_RD_ERR_STS bit in the Interrupt register (02h), poll the MII_ACC bit (bit D0) in the Configuration Register (00h) for MII access completion. MII_ACC will be a 0 when the MII access is complete. Once the MII access is complete, then the Interrupt Register can be read to obtain the status of the MII_RD_ERR_STS bit. O The only overhead involved is performing one extra read to the Interrupt Register after the polling cycle is complete. MII accesses take on the order of 12.8 us per access, and this workaround only adds one more ~300 ns read to complete the operation: not a large overhead. 6.3 Initial Packet Logging When activity occurs while the DP83856B is not in management mode, certain counters and flags are activated. When the device is placed into management mode they are not reset. This potentially causes the first packet received to be flagged as a collision or other sort of error condition even though it may have been a valid packet. The anomaly occurs most frequently at power up. At power up, the device has not yet been placed in management mode and activity (noise) is present on the network. This causes the counters and/or flags to be set. 6.2 Sixty-Three Byte Packet Counting Any packet received on a repeater port that is managed by the DP83856B, which has a frame length of 142 or 143 nibbles (63 bytes + 8 bytes of preamble/sfd) will not be logged as a Runt packet. 26 www.national.com The anomaly can also occur if the device is run through the following sequence of events: 6.4 Random Activity On Management Interface When a twisted-pair cable is removed from a port, the DP83850 (100RIC) may assert -M_DV without TX_RDY and send activity on M_CK. Under these conditions, when the next packet is received, even if it is a valid packet, an inappropriate device ID may be latched from Management Data (MD[3:0]). Depending on the actual device ID latched, the DP83856B may either not log the packet in the correct location or may not log the packet at all. 1. The device is removed from management mode, 2. A collision packet is received, 3. The device is placed back into management mode 4. Finally, a valid packet is received. The counters will log all subsequent packets correctly but not this initial valid packet. 6.5 Symbol Error During Packet Count IEEE 802.3u Clause 30.4.3.1.17 defines SymbolErrorDuringPacket as “a count of the number of times when a valid length packet was received at the port and there was at least one occurrence of an invalid data symbol...”. ol e For other cases, ensure that there is no network activity while the device is not in management mode. This is generally of little consequence as well, because most systems are expected to keep the device either in or out of management mode for extended network activity periods and not toggle modes frequently with respect to packet activity. te There is no workaround for the case of power up. While this anomaly may cause the count of valid packets received to by off by 1, most networks have orders of magnitude more packet activity such that this is of no consequence. To avoid the possibility of not counting a packet after random invalid management bus activity, use external logic to ensure that -M_DV is asserted only when TX_RDY is also asserted. There is no workaround required. The DP83856B’s implementation is actually more robust because it will flag symbol errors contained in FrameTooLong packets and Jabber packets as well as valid length packets. O bs The DP83856B’s Invalid Symbol Count increments for valid size and oversize packets which contain at least one occurrence of an invalid data symbol. 27 www.national.com te ol e bs DP83856B 100 Mb/s Repeater Information Base 7.0 Physical Dimensions inches (millimeters) unless otherwise noted 132-Lead Molded Plastic Quad Flat Package, JEDEC Order Number DP83856BVF NS Package Number VF132A LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR COPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support device or system whose failure to which, (a) are intended for surgical implant into the perform can be reasonably expected to cause body, or (b) support or sustain life, and whose failure to the failure of the life support device or system, perform, when properly used in accordance with or to affect its safety or effectiveness. instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. National Semiconductor Corporation Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: [email protected] Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 National Semiconductor Asia Pacific Customer Response Group Tel: (852) 2737-1600 Fax: (852) 2736-9960 Email: sea [email protected] National Semiconductor Japan Ltd. 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