TI DAC5674IPHPG4

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8
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
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FEATURES
D Differential Scalable Current Outputs: 2 mA to
D 200-MSPS Maximum Input Data Rate
D 400-MSPS Maximum Update Rate DAC
D 76-dBc SFDR Over Full First Nyquist Zone
D On-Chip 1.2-V Reference
D 1.8-V Digital and 3.3-V Analog Supply
With Single Tone Input Signal (Fout = 21 MHz)
D 74-dBc ACPR W-CDMA at 15.36 MHz IF
D 69-dBc ACPR W-CDMA at 30.72 MHz IF
D Selectable 2y or 4y Interpolation Filter
−
−
−
−
−
Linear Phase
0.05-dB Pass-Band Ripple
80-dB Stop-Band Attenuation
Stop-Band Transition 0.4−0.6 Fdata
Interpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For
Selection High-Order Images
D On-Chip 2y/4y PLL Clock Multiplier, PLL
Bypass Mode
20 mA
D
D
D
Operation
1.8/3.3-V CMOS Compatible Interface
Power Dissipation: 435 mW at 400 MSPS
Package: 48-Pin TQFP
APPLICATIONS
D Cellular Base Transceiver Station Transmit
D
D
D
Channel
− CDMA: W-CDMA, CDMA2000, IS-95
− TDMA: GSM, IS-136, EDGE/UWC-136
Test and Measurement: Arbitrary Waveform
Generation
Direct Digital Synthesis (DDS)
Cable Modem Termination System
DESCRIPTION
The DAC5674 is a 14-bit resolution, high-speed, digital-to-analog converter (DAC) with integrated
4× interpolation filter, onboard clock multiplier, and on-chip voltage reference. The device has been designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.
The 4× interpolation filter is implemented as a cascade of two 2× interpolation filters, each of which can be
configured for either low-pass or high-pass response. This enables the user to select one of the higher order
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and
costs.
In 4× interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter
requirements by filtering out the images in the adjacent Nyquist zones.
The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excel is a trademark of Microsoft Corporation.
CommsDAC and PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
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Copyright  2005, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital
I/Os are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions.
The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended
and differential applications. The output current can be directly fed to the load with no additional external output
buffer required. The device has been specifically designed for a differential transformer coupled output with a
50-Ω doubly terminated load. For a 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (−2-dBm output power) are supported. The latter
configuration is preferred for optimum performance at high output frequencies and update rates.
An accurate on-chip 1.2-V temperature compensated band-gap reference and control amplifier allows the user
to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control
capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device
features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the
power consumption for the system’s need.
The DAC5674 is available in a 48-pin HTQFP PowerPAD plastic quad flatpack package. The device is
characterized for operation over the industrial temperature range of −40°C to 85°C.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
48-HTQFP PowerPAD Plastic Quad Flatpack
DAC5674IPHP
−40°C
−40
C to 85
85°C
C
DAC5674IPHPR
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage range
AVDD(2), CLKVDD(2), IOVDD(2), PLLVDD(2)
DVDD(3)
Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND
D[13..0](3), HP1, HP2, DIV0(3), DIV1(3), PLLLOCK(3), RESET(3), X4(3)
Supply voltage range
IOUT1, IOUT2(2)
EXTIO(2), EXTLO(2), BIASJ(2), SLEEP(2), CLK(2), CLKC(2), LPF(2)
−0.5 V to 4 V
−0.5 V to 2.3 V
−0.5 V to 0.5 V
−0.5 V to IOVDD + 0.5 V
−1 V to AVDD + 0.5 V
−0.5 V to AVDD + 0.5 V
Peak input current (any input)
20 mA
Peak total input current (all inputs)
−30 mA
Operating free-air temperature range, TA: DAC5674I
−40°C to 85°C
Storage temperature range
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND.
(3) Measured with respect to DGND.
2
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DC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 kΩ, internal reference, unless otherwise noted
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP
MAX
UNIT
14
Bits
DC ACCURACY(1)
INL
Integral nonlinearity
DNL
Differential nonlinearity
1 LSB = IOUTFS/214, TMIN to TMAX
Monotonicity
−3.5
3.5
−2.14e−4
2.14e−4
LSB
−2
2
IOUTFS
LSB
−1.22e−4
1.22e−4
IOUTFS
Montonic to 12 bits
ANALOG OUTPUT
Offset error
Gain error
0.02
Without internal reference
2.3
With internal reference
1.3
FSR
%FSR
Minimum full-scale output
current(2)
2
mA
Maximum full-scale output
current(2)
20
mA
Output compliance range(3)
IOUTFS = 20 mA
−1
Output resistance
Output capacitance
1.25
V
300
kΩ
5
pF
REFERENCE OUTPUT
Reference voltage
1.14
Reference output current(4)
1.2
1.26
100
V
nA
REFERENCE INPUT
VEXTIO
Input voltage range
0.1
Input resistance
1.25
V
1
MΩ
Small signal bandwidth
1.4
MHz
Input capacitance
100
pF
TEMPERATURE COEFFICIENTS
Offset drift
Without internal reference
0
ppm of
FSR/°C
±50
ppm of
FSR/°C
±100
ppm of
FSR/°C
±50
ppm/°C
Gain drift
With internal reference
Reference voltage drift
POWER SUPPLY
AVDD
Analog supply voltage
DVDD
Digital supply voltage
CLKVDD
Clock supply voltage
IOVDD
I/O supply voltage
PLLVDD
PLL supply voltage
IAVDD
Analog supply current
3
3.3
3.6
V
1.65
1.8
1.95
V
3
3.3
3.6
V
3.6
V
3.3
3.6
V
41
55
mA
1.65
3
Including output current through the load
resistor, AVDD = 3.3 V, DVDD = 1.8 V, 4×
interpolation, PLL on, 9-MHz IF, 400 MSPS
Specifications subject to change without notice.
(1) Measured differentially across IOUT1 and IOUT2 into 50 Ω.
(2) Nominal full-scale current, IOUTFS, equals 32× the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting
in reduced reliability of the DAC5674 device. The upper limit of the output compliance is determined by the load resistors and full-scale output
current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high impedance input to drive any external load.
3
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DC ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 kΩ, internal reference, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY (CONTINUED)
IDVDD
Digital supply current
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
ISLEEP3.3
ISLEEP1.8
Sleep mode
Sleep mode
IPLLVDD
107
140
mA
Sleep mode, supply current 3.3 V
6
12
mA
Sleep mode, supply current 1.8 V
0.5
3
mA
PLL supply current(1)
Fdata = 100 MSPS, Fupdate = 400 MSPS,
DIV[1:0] = ’00’, AVDD = 3.3 V, DVDD = 1.8 V, 4×
interpolation, PLL on, 9-MHz IF, 400 MSPS
23
35
mA
IIOVDD
Buffer supply current
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
4
10
mA
ICLKVDD
Clock supply current(1)
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
6
10
mA
PD
Power dissipation
AVDD = 3.3 V, DVDD = 1.8 V, 4× interpolation,
PLL on, 9-MHz IF, 400 MSPS
435
550
mW
APSRR
Power supply rejection ratio
−0.2
0.2
DPSRR
−0.2
0.2
Operating range
−40
85
%FSR/V
°C
Specifications subject to change without notice.
(1) PLL enabled
AC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
fCLK
ts(DAC)
Maximum output update rate
tr(IOUT)
tf(IOUT)
Output rise time 10% to 90%(1)
Output fall time 90% to 10%(1)
Output settling time to 0.1%
Output noise
400
Midscale transition
IOUTFS = 20 mA
IOUTFS = 2 mA
MSPS
20
ns
1.4
ns
1.5
ns
55
30
pA/√HZ
AC LINEARITY 1:1 IMPEDANCE RATIO TRANSFORMER (ALL AC MEASUREMENTS PLLVDD = 0 V)
SFDR
Spurious free dynamic range (First
Nyquist zone < fDATA/2) X4 LL-mode
SNR
Signal-to-noise ratio (First Nyquist
zone < fDATA/2) X4 LL-mode
ACPR
Adjacent channel power ratio
W-CDMA signal with 3.84-MHz BW
5-MHz channel spacing
IMD3
IMD
Third-order, two-tone intermodulation
(each tone at −6 dBFS)
Four-tone Intermodulation to Nyquist
(each tone at –12 dBFS)
(1) Measured single-ended into 50-Ω load.
4
fDATA = 52 MSPS, fOUT = 14 MHz, TA = 25_C
fDATA = 100 MSPS, fOUT = 21 MHz, TMIN to TMAX
85
fDATA = 100 MSPS, fOUT = 41 MHz, TMIN to TMAX
fDATA = 78 MSPS, fOUT = 20 MHz, TMIN to TMAX
71
fDATA = 100 MSPS, fOUT = 20 MHz, TMIN to TMAX
70
fDATA = 61.44 MSPS, IF = 15.360 MHz, X4 LL-mode
74
fDATA = 122.88 MSPS, IF = 30.72 MHz, X2 L-mode
69
fDATA = 61.44 MSPS, fOUT = 45.4 and 46.4 MHz,
X4 HL-mode
68
fDATA = 61.44 MSPS, fOUT = 15.1 and 16.1 MHz,
X4 LL-mode
82
fDATA = 78 MSPS fOUT = 15.6 MHz, 15.8 MHz,
16.2 MHz, 16.4 MHz, X4 LL-mode
76
fDATA = 52 MSPS fOUT = 68.8 MHz, 69.6 MHz,
71.2 MHz, 72 MHz, X4 HH-mode
64
76
dBc
71
dB
dB
dBc
dBc
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS INTERFACE
VIH
VIL
High-level input voltage for SLEEP and EXTLO
0.7 AVDD
Low-level input voltage for SLEEP and EXTLO
0
VIH
VIL
High-level input voltage other digital inputs
0.7 IOVDD
Low-level input voltage other digital inputs
0
0.3 IOVDD
IIH
IIL
High-level input current
10
30
µA
Low-level input current
−1
10
µA
1
5
pF
Input capacitance
V
0.3 AVDD
V
V
V
TIMING INTERNAL CLOCK MODE
tSU
tH
Input setup time
0.6
Input hold time
0.6
tLPH
tlat_2x
Input latch pulse high time
ns
ns
2
ns
Data in to DAC out latency − 2× interpolation
26
clk
tlat_4x
Data in to DAC out latency − 4× interpolation
TIMING − EXTERNAL CLOCK MODE
35
clk
tsu
th
Input setup time
5
tlph
td_clk
Input latch pulse high time
Clock delay time
3.6
ns
tlat_2x
tlat_4x
Data in to DAC out latency − 2× interpolation
26
clk
Data in to DAC out latency − 4× interpolation
35
clk
Input hold time
ns
−1.75
ns
2
ns
PLL
Input data rate supported
Phase noise
5
200
At 600-kHz offset
−124
At 6-MHz offset
−134
MSPS
dBc/Hz
DIGITAL FILTER SPECIFICATIONS
fDATA
Input data rate
FIR1 and FIR2 DIGITAL FILTER CHARACTERISTICS
200
0.005 db
Pass-band width
MSPS
0.407
0.01 dB
0.41
0.1 dB
0.427
3 dB
0.481
fOUT/
fDATA
5
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
PINOUT DIAGRAM
DVDD
DVDD
AVDD
AVDD
AGND
IOUT1
IOUT2
AGND
BIASJ
EXTIO
EXTLO
AGND
PHP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DGND
DGND
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
D3
D2
D1
D0
HP1
HP2
DGND
IOGND
DVDD
IODVDD
X4
DGND
13 14 15 16 17 18 19 20 21 22 23 24
6
SLEEP
LPF
PLLVDD
PLLGND
CLKVDD
CLKGND
CLKC
CLK
DIV0
DIV1
RESET
PLLLOCK
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
Terminal Functions
TERMINAL
NAME
NO.
AGND
37, 41, 44
AVDD
BIASJ
I/O
DESCRIPTION
I
Analog ground return
45, 46
I
Analog supply voltage
40
O
Full-scale output current bias
CLK
29
I
External clock input
CLKC
30
I
Complementary external clock input
CLKGND
31
I
Ground return for internal clock buffer
CLKVDD
32
I
Internal clock buffer supply voltage
D[13..0]
3−16
I
Data bits 0 through 13
D13 is most significant data bit (MSB)
D0 is least significant data bit (MSB)
DIV[1..0]
27,28
I
PLL prescaler divide ratio settings
DGND
1, 2, 19, 24
I
Digital ground return
DVDD
21, 47, 48
I
Digital supply voltage
EXTIO
39
I/O
EXTLO
38
I
For internal reference connect to AGND. Connect to AVDD to disable the internal reference
HP1
17
I
Filter 1 high-pass setting. Active high
HP2
18
I
Filter 2 high-pass setting. Active high
IOGND
20
I
Input digital ground return
IODVDD
22
I
Input digital supply voltage
IOUT1
43
O
DAC current output. Full scale when all input bits are set 1
IOUT2
42
O
DAC complementary current output. Full scale when all input bits are 0
LPF
35
I
PLL loop filter connection
PLLGND
33
I
Ground return for internal PLL
PLLLOCK
25
O
PLL lock status bit. PLL is locked to input clock when high. Provides output clock equal to the data rate
when the PLL is disabled.
PLLVDD
34
I
Internal PLL supply voltage. Connect to PLLGND to disable PLL clock multiplier.
RESET
26
I
Reset internal registers. Active high
SLEEP
36
I
Asynchronous hardware power-down input. Active high. Internally pull down.
X4
23
I
4× interpolation mode. Active high. Filter 1 is bypassed when connected to DGND
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to AGND
when used as reference output
7
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
FUNCTIONAL BLOCK DIAGRAM
CLKVDD
CLKGND
CLK
PLLLOCK
LPF
PLLGND
PLLVDD
DIV[1:0]
HP1
PLL Clock
Multiplier
CLKC
HP2
X4
48-Pin TQFP
SLEEP
AVDD (2y)
AGND (3y)
Clock Generation / Mode Select
HP1
IODVDD
X4
HP2
IOGND
BIASJ
..., 1, −1,...
D[13:0]
y2
..., 1, −1,...
1
1
y2
0
EdgeTriggered
Input
Latches
IOUT2
FIR2
1.2-V
Reference
DVDD (3y)
DGND (4y)
Figure 1. Block Diagram
8
14-BIt DAC
0
0
FIR1
IOUT1
1
EXTIO
EXTLO
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
TYPICAL CHARACTERISTICS
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
INPUT CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
VCC = 3.3 V
IOUTfS = 20 mA
0
2000
4000
6000
8000
10000
12000
14000
16000
14000
16000
Input Code
Figure 2
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
VCC = 3.3 V
IOUTfS = 20 mA
0
2000
4000
6000
8000
10000
12000
Input Code
Figure 3
9
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
90
VCC = 3.3 V
fS = 50 MSPS
IOUTfS = 20 mA
4y LL-Mode
85
80
SFDR − Spurious-Free Dynamic Range − dBc
SFDR − Spurious-Free Dynamic Range − dBc
90
−3 dBfS
75
0 dBfS
70
−6 dBfS
65
60
55
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4y LL-Mode
85
80
0 dBfS
75
70
−6 dBfS
−3 dBfS
65
60
55
50
50
0
3
6
9
12
15
0
18
5
10
Figure 4
Power − dBm
−40
−50
−60
−70
−80
−90
−100
25
50
75
100
125
f − Frequency − MHz
Figure 6
NOTE: All measurements made with PLL off.
10
150
175
200
SFDR − In-Band Spurious-Free Dynamic Range − dBc
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4y LL-Mode
Fout = 10 MHz
0
30
35
IN-BAND
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
0
−30
25
Figure 5
POWER
vs
FREQUENCY
−20
20
fO − Output Frequency − MHz
fO − Output Frequency − MHz
−10
15
90
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4y LL-Mode
In Band = 0 − 50 MHz
85
80
0 dBfS
75
−6 dBfS
70
−12 dBfS
65
60
55
50
0
5
10
15
20
25
30
35
fO − Output Frequency − MHz
Figure 7
40
45
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OUT-OF-BAND
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
POWER
vs
FREQUENCY
−20
80
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4y LL-Mode
Out-of-Band = 50 − 100 MHz
75
70
65
60
55
−6 dBfS
50
−12 dBfS
0 dBfS
45
VCC = 3.3 V
fS = 61.44 MSPS
fcarrier = 15.36 MHz
IOUTfS = 20 mA
ACPR = 73.25 dB
4y LL-Mode
−40
P − Power − dBm
SFDR − Out-of-Band Spurious-Free Dynamic Range − dBc
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
−60
−80
−100
40
35
−120
30
0
5
10
15
20
25
30
35
40
6
45
9
12
Figure 8
24
−20
VCC = 3.3 V
fS =76.80 MSPS
fcarrier = 19.20 MHz
VCC = 3.3 V
fS = 122.88 MSPS
fcarrier = 30.72 MHz
IOUTfS = 20 mA
ACPR = 70.23 dB
2y L-Mode
IOUTfS = 20 mA
ACPR = 70.22 dB
4y LL-Mode
−40
P − Power − dBm
P − Power − dBm
21
POWER
vs
FREQUENCY
−20
−60
−80
−60
−80
−100
−100
−120
17
18
Figure 9
POWER
vs
FREQUENCY
−40
15
f − Frequency − MHz
fO − Output Frequency − MHz
−120
21
25
29
33
37
f − Frequency − MHz
Figure 10
41
45
8
12
16
20
24
28
f − Frequency − MHz
Figure 11
NOTE: All measurements made with PLL off.
11
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POWER
vs
FREQUENCY
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
−20
85
80
Two-Tone IMD3 − dBc
P − Power − dBm
−40
90
VCC = 3.3 V
fS = 61.44 MSPS
fcarrier = 15.36 MHz
IOUTfS = 20 mA
ACPR = 69.73 dB
4y LH-Mode
−60
−80
75
70
65
VCC = 3.3 V
fS = 78 MSPS
fout1 = fout
fout2 = fout + 1 MHz
IOUTfS = 20 mA
4y LL-Mode
60
−100
55
−120
32
50
36
40
44
48
52
56
60
0
5
f − Frequency − MHz
10
Figure 13
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
90
85
Two-Tone IMD3 − dBc
80
75
70
65
VCC = 3.3 V
fS = 78 MSPS
fout1 = fout
fout2 = fout + 4 MHz
IOUTfS = 20 mA
4y LL-Mode
60
55
50
0
5
10
15
20
25
fO − Output Frequency − MHz
Figure 14
NOTE: All measurements made with PLL off.
20
25
fO − Output Frequency − MHz
Figure 12
12
15
30
35
30
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
DETAILED DESCRIPTION
Figure 1 shows a simplified block diagram of the DAC5674. The CMOS device consists of a segmented array
of PMOS current sources, capable of delivering a full-scale output current up to 20 mA. Differential current
switches direct the current of each current source to either one of the complementary output nodes IOUT1 or
IOUT2. The complementary output currents thus enable differential operation, canceling out common mode
noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, even-order distortion components, and
increase signal output power by a factor of two.
The full-scale output current is set using an external resistor RBIAS in combination with an on-chip band-gap
voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted
from 20 mA down to 2 mA.
Interpolation Filter
The interpolation filters FIR1 and FIR2 can be configured for either low-pass or high-pass response. In this way,
higher order images can be selected. Table 1 shows the DAC IF output range for the different filter response
combinations, for both the first and second Nyquist zone (after interpolation). Table 2 lists the DAC IF output
ranges for two popular GSM data rates. Table 3 shows the W-CDMA IF carrier center frequency for an input
data rate of 61.44 MSPS and a fundamental input IF of 15.36 MHz. Figure 15 shows the spectral response;
the corresponding nonzero tap weights are:
D [5, −20, 50, −108, 206, −361, 597, −947, 1467, −2267, 3633, −6617, 20746, 32768]
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0.005
−50
Amplitude − dB
Amplitude − dB
0
0.000
−100
−150
0.0
0.2
0.4
0.6
0.8
1.0
−0.005
0.0
0.2
f / fin
0.4
0.6
0.8
1.0
f / fin
Figure 15. FIR1 and FIR2 Magnitude Spectrum
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
Table 1. Interpolation Filters Configuration
FILTER 1
CONFIGURATION
FILTER 2
CONFIGURATION
Low pass
Low pass
Low pass
High pass
High pass
Low pass
High pass
High pass
IF OUTPUT RANGE 1
(FIRST NYQUIST ZONE)
IF OUTPUT RANGE 2
(SECOND NYQUIST ZONE)
FREQUENCY
SINX/X ATT. [dB]
FREQUENCY
SINX/X ATT. [dB]
0…0.4Fdata
1.6…2Fdata
0…0.14
2.42…3.92
3.6…4Fdata
2…2.4Fdata
3.92…5.94
0.6…0.8Fdata
1.2…1.4Fdata
0.32…0.58
1.33…1.83
19.2…∞
3.2…3.4Fdata
2.6…2.8Fdata
12.6…15.4
7.20…8.69
Table 2. Interpolation Filters Configuration: Example Frequencies GSM
FILTER 1
CONFIGURATION
FILTER 2
CONFIGURATION
IF OUTPUT RANGE 1
(FIRST NYQUIST ZONE)
IF FREQUENCY [MHz]
IF OUTPUT RANGE 2
(SECOND NYQUIST ZONE)
IF FREQUENCY [MHz]
Low pass
Low pass
Fdata = 52 MSPS
0…20.8
Fdata = 78 MSPS
0…31.2
Fdata = 52 MSPS
187.2…208
Fdata = 78 MSPS
280.8…312
Low pass
High pass
83.2…108
124.8…156
104…124.8
156…187.2
High pass
Low pass
31.2…41.6
46.8…62.4
166.4…176.8
249.6…265.2
High pass
High pass
62.4…72.8
93.6…109.2
135.2…145.6
202.8…218.4
Table 3. Interpolation Filters Configuration: Example Frequencies W-CDMA, IF = Fdata/4, FDATA = 61.44
MSPS: Fupdate = 245.76 MSPS
14
IF FREQUENCY [MHZ]
(FIRST NYQUIST ZONE)
IF FREQUENCY [MHZ]
(SECOND NYQUIST ZONE)
FILTER 1
CONFIGURATION
FILTER 2
CONFIGURATION
IF CENTER [MHz]
SINX/X ATT. [dB]
IF CENTER [MHz]
SINX/X ATT. [dB]
Low pass
Low pass
15.36
0.05
230.4
23.6
Low pass
High pass
107.52
2.93
138.24
5.11
High pass
Low pass
46.08
0.51
199.68
13.2
High pass
High pass
76.8
1.44
168.96
8.29
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Low-Pass/Low-Pass 4y Interpolation Filter Operation
Figure 16 shows the low-pass/low-pass interpolation operation where the 4× FIR filter is implemented as a
cascade of two 2× interpolation filters with the input signal coming from a digital signal source such as an FPGA
or digital upconverter (DUC). Users can place their IF signal at a maximum of 0.4 times the FIR filter input (i.e.,
DAC5674 input) data rate. For a 100-MSPS data rate, this would translate into a pass band extending to 40
MHz.
Input Spectrum
Output of DUC
Fdata
1st 2x
interpolation
filter
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
80 dB of
attenuation
Fdata
Spectrum after
2x interpolation
2nd LPF removes
interpolation images
2nd 2x
interpolation
filter
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
=
Fdac
Spectrum after
4x interpolation
Figure 16. Low-Pass/Low-Pass 4y Interpolation Filter Operation
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
Low-Pass/High-Pass 4y Interpolation Filter Operation
By configuring the low-pass filters as high-pass filters, the user can select one of the images present at multiples
of the clock. Figure 17 shows the low-pass/high-pass filter response. After digital filtering, the DAC transmits
at 2Fdata − IF and 2Fdata + IF. This configuration is equivalent to sub-sampling receiver systems where a
high-speed analog-to-digital converter samples high IF frequencies with relatively low sample rates, resulting
in low (output) data rates.
The placement of the IF in the first Nyquist zone combined with the DAC5674 input data determines the final
output signal frequency. For Fdata = 100 MSPS and a fundamental IF of 0.4 × Fdata = 40 MHz, this would translate
into images located at 160 MHz and 240 MHz. Note that this is the equivalent of mixing a 40-MHz analog IF
signal with a 200-MHz sine wave. By doing this, the first mixer in the total transmission chain is eliminated.
Input Spectrum
Output of DUC
Fdata
1st 2x
interpolation
filter
Fdata
Fdata
Fdata
80 dB of
Attenuation
Spectrum after
2x interpolation
Fdata
2nd 2x
interpolation
filter
Fdata
Fdata
HPF filters out
unwanted
image
Fdata
HPF filters out
unwanted
image
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
=
Fdac
Spectrum after
4x interpolation
Figure 17. Low-Pass/High-Pass 4y Interpolation Filter Operation
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High-Pass/Low-Pass 4y Interpolation Filter Operation
Figure 18 shows the high-pass/low-pass filter configuration. Images at Fdata − IF and 3Fdata + IF can be
selected. Note that the latter image severely attenuates by the sinx/x response. The transition bandwidths of
filter 1 and filter 2 occupy 0.2Fdata. The combination of these transition bands results in an output IF between
0.6…0.8Fdata.
Input Spectrum
Output of DUC
Fdata
1st 2x
interpolation
filter
80 dB of
attenuation
Fdata
Fdata
Fdata
80 dB of
attenuation
80 dB of
attenuation
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Spectrum after
2x interpolation
Unwanted images
removed by LPF
2nd 2x
interpolation
filter
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
=
Fdac
Spectrum after
4x interpolation
Figure 18. High-Pass/Low-Pass 4y Interpolation Filter Operation
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High-Pass/High-Pass 4y Interpolation Filter Operation
Figure 19 shows the high-pass/high-pass filter configuration. The transition bands of filter 1 and filter 2 allow
for the placement of the fundamental IF between 0.2…0.4Fdata. In this configuration, the user can select the
images at Fdata + IF and 3Fdata – IF. For Fdata = 100 MSPS and a fundamental IF of 0.4 × Fdata = 40 MHz, this
would translate into images located at 140 MHz and 260 MHz. Note that this is the equivalent of mixing a 60-MHz
analog IF signal with a 200-MHz sine wave.
Input Spectrum
Output of DUC
Fdata
1st 2x
interpolation
filter
80 dB of
attenuation
Fdata
Fdata
Fdata
80 dB of
attenuation
80 dB of
attenuation
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Spectrum after
2x interpolation
2nd 2x
interpolation
filter
Unwanted images
removed by HPF
Unwanted images
removed by HPF
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
Fdata
=
Fdac
Spectrum after
4x interpolation
Figure 19. High-Pass/High-Pass 4y Interpolation Filter Operation
DAC Sinx/x Output Attenuation
The output frequency spectrum of the DACs shows some inherent attenuation due to their sample-and-hold
nature. The output of the DAC is normally seen as the signal sample held over the sampling time in a stair-step
manner. In the time domain, this step-like output can be thought of as an impulse sample of some value
convolved with a unit-square pulse with a duration of the sampling time. In the frequency domain, this translates
to the frequency response of the discretely sampled signal multiplied by the sinx/x frequency response function
of the square pulse. The sinx/x function has a null at every integer multiple of the sampling rate.
This is shown in Figure 20 for various data rates at 4× interpolation.
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
*1.83 dB
”Sinx/x”
Attenuation
*7.2 dB
Fupdate+65 MSPS
0
IF=26
65
91
130
*1.83 dB
169
195
”Sinx/x”
Attenuation
*7.2 dB
Fupdate+80 MSPS
0
IF=32
80
112
160
*1.83 dB
208
240
IF=40
100
140
200
260
320
”Sinx/x”
Attenuation
*7.2 dB
Fupdate+100 MSPS
0
260
300
400
Figure 20. High-Pass 4y Interpolation Filter Operation: Example Frequencies
Clock Generation Function
An internal phase-locked loop (PLL) or external clock can be used to derive the internal clocks (1×, 2×, and 4×)
for the logic, FIR interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal
PLL blocks (PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and
CLKGND), thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock
mode: when PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode
is active.
In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes
the 4× clock and is twice divided down to generate the 2× and 1× clocks. The 2× or 1× clock is multiplexed out
on the PLLLOCK pin to allow for external clock synchronization.
In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four
phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and
drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing
the VCO output by 1×, 2×, 4×, or 8×, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the
4× clock, and is divided down twice to generate the 2× and 1× clocks. Pin X4 selects the 1× or 2× clock to clock
in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an
output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user
at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the
clock configurations with corresponding data rate ranges.
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
LPF
DIV[1:0]
PLLVDD
DAC5674
CLK
Charge
Pump
PFD
CLKC
/1
/2
/4
/8
VCO
Clk_4y
Clk
Buffer
PLLVDD
PLLGND
0
0
/2
Clk_2y
1
s
/2
Clk_1y
CLKVDD
1
s
CLKGND
PLLLOCK
PLLVDD
Data
D[13:0]
X4
Figure 21. Clock Generation Functional Diagram
Table 4. Clock Mode Configuration
CLOCK MODE
PLLVDD
DIV[1:0]
X4
DATA RANGE (MHz)
PLLLOCK PIN FUNCTION
External 2×
0V
XX
0
DC to 200
External clock/2
External 4×
0V
XX
1
DC to 100
External clock/4
Internal 2×
3.3 V
00
0
100 to 200
Internal PLL lock indicator
Internal 2×
3.3 V
01
0
50 to 100
Internal PLL lock indicator
Internal 2×
3.3 V
10
0
25 to 50
Internal PLL lock indicator
Internal 2×
3.3 V
11
0
12 to 25
Internal PLL lock indicator
Internal 4×
3.3 V
00
1
50 to 100
Internal PLL lock indicator
Internal 4×
3.3 V
01
1
25 to 50
Internal PLL lock indicator
Internal 4×
3.3 V
10
1
12 to 25
Internal PLL lock indicator
Internal 4×
3.3 V
11
1
5 to 12
Internal PLL lock indicator
Low-Pass Filter
The PLL consists of a type four phase-frequency detector (PFD), charge pump, external low-pass loop filter,
voltage to current converter, and current controlled oscillator (ICO) as shown in Figure 22. The DAC5674
evaluation board comes with component values R = 200, C1 = 0.01 µF, and C2 = 100 pF. These values have
been designed to give the phase margins and loop bandwidths listed in Table 5 for the five divide down factors
of prescaling and interpolation. Note that the values derived were based on a charge pump current output of
1 mA and a VCO gain of 300 MHz/V (nominal at Fvco = 400 MHz). With this filter, the settling time from a phase
or frequency disturbance is about 2.5 µs. If different PLL dynamics are required, DAC5674 users can design
a second order filter for their application; see the Designing the PLL Loop Filter section of this data sheet.
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
DAC5674
LPF
Fref
PFD
Fvco
R
C2
PN
C1
ICO
ref
External Loop Filter
Figure 22. PLL Functional Block Diagram
Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters
N(1)
PHASE MARGIN (DEGREES)
BANDWIDTH (MHZ)
2
60
1.6
4
71
1.4
8
77
1
16
78
0.7
32
74
0.4
(1) N is the VCO divide-down factor from prescale and interpolation.
Non-Harmonic Clock-Related Spurious Signals
In interpolating DACs, imperfect isolation between the digital and DAC clock circuits generates spurious signals
at frequencies related to the DAC clock rate. The digital interpolation filters in these DACs run at subharmonic
frequencies of the output rate clock, where these frequencies are fDAC/2 , N = 1,2. For example, for 2×
interpolation only one interpolation filter runs at fDAC/2; for 4× interpolation, on the other hand, two interpolation
filters run at fDAC/2 and fDAC/4. These lower-speed clocks for the interpolation filter mix with the DAC clock
circuit and create spurious images of the wanted signal and second Nyquist-zone image at offsets of fDAC/2N.
Figure 23 shows the location of the largest spurious signals for 4× interpolation for a real signal. With a real
output signal, there is no distinction between negative and positive frequencies, and therefore the signals that
appear at negative frequencies wrap and potentially fall near the wanted signal. In particular, at IFs near fDAC/8,
fDAC/4, and fDAC × 3/4 (50 MHz, 100 MHz, and 150 MHz in this example), the mixing effect results in spurious
signals falling near the wanted signal, which may present a problem depending on the system application. For
a frequency-symmetric signal (such as a single WCDMA or CDMA carrier), operating at exactly fDAC/8, fDAC/4
and fDAC × 3/4, the spurious signal falls completely inside the wanted signal, which produces a clean spectrum
but may result in degradation of the signal quality.
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
0.500
Spur Frequency / DAC Frequency
Output IF
0.375
IF − 3fDAC/4
IF + fDAC/4
0.250
0.125
IF − fDAC/4
IF − fDAC/2
0.000
0.000
0.125
0.250
0.375
0.500
Output Frequency / DAC Frequency
Figure 23. Location of Clock Mixing Spurs vs IF for 4y Mode
The offset between wanted and spurious signals is maximized at low IFs (< fDAC/8) and at fDAC × 3/16,
fDAC × 5/16, and fDAC × 7/16. For example, with fDATA = 100 MSPS and 4× interpolation, operating with
IF = fDAC × 5/16 = 125 MHz results in spurious signals at offsets of ±50 MHz from the wanted signal.
Figure 24a shows the amplitude of each spurious signal as a function of IF in external-clock mode. The
dominant spurious signal is IF − fDAC/2. The amplitudes of the IF + fDAC/4 and IF − fDAC/4 are the next-highest
spurious signals and are approximately at the same amplitude. Finally, at IF frequencies greater than 100 MHz,
small spurious signals at IF − fDAC × 3/4 are measurable.
0
0
−10
−10
IF − FDAC/2
IF − FDAC/2
−20
Amplitude of Spurs − dBc
Amplitude of Spurs − dBc
Figure 24b shows the amplitude of each spurious signal as a function of IF in PLL clock mode. Generating the
DAC clock with the onboard PLL/VCO increases the IF − fDAC/2 by 3 dB. The amplitude of the IF ± fDAC/4 and
IF − fDAC × 3/4 remain at about the same level as in the external-clock mode.
IF − FDAC/4
−30
−40
IF − 3FDAC/4
−50
−20
IF − FDAC/4
−30
−40
IF − 3FDAC/4
−50
IF + FDAC/4
IF + FDAC/4
−60
−60
−70
−70
0
50
100
150
200
0
50
150
fsig − Output Frequency − MHz
a. External Clock Mode
b. PLL Mode
Figure 24. External Clock Mode and PLL Mode
22
100
fsig − Output Frequency − MHz
200
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
The amplitudes in Figure 24 are typical values and vary by a few dB across different parts, supply voltages,
and temperatures. Figure 23 and Figure 24 can be used to estimate the non-harmonic clock-related spurious
signals. Take the example for using the DAC5674 in external-clock mode, fDAC = 400 MHz, 4× interpolation,
and IF = 30 MHz. Figure 23 and Figure 24a predict the spurious signals shown in Table 6. The resulting spurs
are at 170 MHz at −38 dBc, 130 MHz at −45 dBc, and 70 MHz at −43 dBc.
Table 6. Predicted Frequency and Amplitude for FDAC − 400 MHz, 4y Interpolation
SPURIOUS COMPONENT
SPURIOUS FREQUENCY
AMPLITUDE dBc
IF – fDAC/2
170 MHz
–38
IF + fDAC/4
130 MHz
–45
IF – fDAC/4
70 MHz
–43
IF – 3fDAC/4
>200 MHz
N/A
Figure 25 shows the DAC5674 output spectrum for the preceding example. The amplitudes of the clock-related
spurs agree quite well with the predicted amplitudes in Table 6.
10
IF
0
Amplitude − dBc
−10
−20
−30
IF − fDAC/4
−40
IF − 3fDAC/4
IF + fDAC/4
−50
−60
−70
−80
0
25
50
75
100
125
150
175
200
Frequency − MHz
Figure 25. DAC Output Spectrum With FDAC = 400 MSPS, 4y Interpolation, IF=30 MHz, External Clock
Digital Inputs
Figure 26 shows a schematic of the equivalent CMOS digital inputs of the DAC5674. The CMOS-compatible
inputs have logic thresholds of IOVDD/2 ±20%. The 14-bit digital data input follows the offset positive binary
coding scheme.
IOVDD (AVDD for SLEEP and EXTLO)
D[13:0]
SLEEP
EXTLO
DIV[1:0]
RESET
HP1, HP2
X4
Internal
Digital In
IOGND
Figure 26. CMOS/TTL Digital Equivalent Input
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
Clock Input and Timing
Figure 27 shows the clock and data input timing diagram for internal and external clock modes, respectively.
Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 27
also shows the delay (td) of the 1×/2× data clock (PLLLOCK) from CLK in external clock mode (typical td = 4.1
ns). The latency from data to DAC is defined by Figure 28. The DAC5674 features a differential clock input.
In internal clock mode, the internal data clock is a divided down version of the PLL clock (/2 or /4), depending
on the level of interpolation (2× or 4×). In external mode, the internal data clock is a divided down version of
the input CLK (/2 or /4), depending on the level of interpolation (2× or 4×). Internal edge-triggered flip-flops latch
the input word on the rising edge of the positive data clock.
D[13:0]
Valid Data
tsu
D[13:0]
th
Valid Data
tsu
PLLLOCK
th
td_clk
tlph
CLK
CLK
CLKC
CLKC
Figure 27. Internal (Left) and External (Right) Clock Mode Timing
tlat_nx
2x Interpolation
DAC
D[13:0] 0
0
2000
3FFF
2000
0
0
4x Interpolation
DAC
Typical tsu = 0.5 ns, th = 0.1 ns
Figure 28. Data to DAC Latency
24
Typical tsu = 2.9 ns, th = −2.3 ns, td = 3.6 ns
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
Figure 29 shows an equivalent circuit for the clock input.
AVDD
CLKVDD
R1
10 kΩ
AVDD
R1
10 kΩ
Internal
Digital In
CLK
CLKC
R2
10 kΩ
R2
10 kΩ
CLKGND
Figure 29. Clock Input Equivalent Circuit
Figure 30, Figure 31, Figure 32, and Figure 33 show various input configurations for driving the differential
clock input (CLK/CLKC).
Optional, May Be Bypassed
for Sine Wave Input
Swing Limitation
CAC
0.1 µF
1:4
CLK
RT
200 Ω
CLKC
Termination Resistor
Figure 30. Preferred Clock Input Configuration
Ropt
22 Ω
TTL/CMOS
Source
Optional, Reduces
Clock Feedthrough
CAC
0.01 µF
1:1
Ropt
22 Ω
CLK
CLKC
TTL/CMOS
Source
0.01 µF
CLK
CLKC
Node CLKC
Internally Biased
to IVDDń2
Figure 31. Driving the DAC5674 With a Single-Ended TTL/CMOS Clock Source
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SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
CAC
0.01 µF
+
Differential
ECL
or
(LV)PECL
Source
CLK
CAC
0.01 µF
−
CLKC
RT
50 Ω
RT
50 Ω
VTT
Figure 32. Driving the DAC5674 With Differential ECL/PECL Clock Source
Single-Ended
ECL
or
(LV)PECL
Source
ECL/PECL
Gate
CAC
0.01 µF
CLK
CAC
0.01 µF
CLKC
RT
50 Ω
RT
50 Ω
VTT
Figure 33. Driving the DAC5674 With a Single-Ended ECL/PECL Clock Source
Supply Inputs
The DAC5674 comprises separate analog and digital supplies at AVDD, DVDD, and IOVDD. These supplies
can range from 3 V to 3.6 V for AVDD, 1.65 to 1.95 V for DVDD, and 1.65 to 3.6 for IOVDD.
DAC Transfer Function
The DAC5674 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binary
coding, with D13 being the MSB and D0 the LSB. Output current IOUT1 equals the approximate full-scale output
current when all input bits are set high, i.e., the binary input word has the decimal representation 16383.
Full-scale output current flows through terminal IOUT2 when all input bits are set low (mode 0, straight binary
input). The relation between IOUT1 and IOUT2 can thus be expressed as:
N
IOUT1 + 2 * 1 IOUT FS * IOUT2
2N
Where IOUTFS is the full-scale output current, N = 14 bits. The output currents can be expressed as:
IOUT1 + IOUT
FS
CODE
16384
IOUT2 + IOUT
FS
16383 * CODE
16384
Where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2
drive resistor loads (RL) or a transformer with equivalent input load resistance (RL). This would translate into
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
26
www.ti.com
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
VOUT1 + IOUT1
RL + IOUT FS
CODE
16384
VOUT2 + IOUT2
RL + IOUT FS
16383 * CODE
16384
RL
RL
The differential output voltage VOUTDIFF can thus be expressed as:
VOUT DIFF + VOUT1 * VOUT2 + IOUT FS
2CODE * 16383
16384
RL
The latter equation shows that applying the differential output results in doubling of the signal power delivered
to the load. Because the output currents IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Note that care should be taken not to exceed the compliance voltages at node IOUT1
and IOUT2, which would lead to increased signal distortion.
Reference Operation
The DAC5674 comprises a band-gap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor
RBIAS is defined by the on-chip band-gap reference voltage and control amplifier. The full-scale output current
equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as:
IOUT
FS
+ 32
I
BIAS
+
32
V
R
EXTIO
BIAS
where VEXTIO is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage
of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference
can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the band-gap load current to a maximum of 100 nA. The internal
reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. In this case,
capacitor CEXT can be omitted. Terminal EXTIO serves as either input or output node.
The full-scale output current can be adjusted from 20 mA to 2 mA by varying resistor RBIAS or changing the
externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 mA.
Analog Current Outputs
Figure 34 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual PMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack
of the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance
of 5 pF.
The external output resistors are referred to an external ground. The minimum output compliance at nodes
IOUT1 and IOUT2 is limited to −1 V, determined by the CMOS process. Beyond this value, transistor breakdown
may occur resulting in reduced reliability of the DAC5674 device. The maximum output compliance voltage at
nodes IOUT1 and IOUT2 equals 1.25 V. Exceeding the maximum output compliance voltage adversely affects
distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V.
27
www.ti.com
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
AVDD
S(1)
S(1)C
IOUT1
S(2)
S(2)C
S(N)C
Current Source Array
IOUT2
RLOAD
S(N)
RLOAD
Figure 34. Equivalent Analog Current Output
The DAC5674 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF
transformer. Figure 35 and Figure 36 show the 50-Ω doubly terminated transformer configuration with 1:1 and
4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be
grounded to enable a dc current flow. Applying a 20-mA full-scale output current would lead to a 0.5 VPP for
a 1:1 transformer and a 1 VPP output for a 4:1 transformer.
Figure 37 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 should be connected to AGND or terminated with a resistor of 25 Ω to
AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA
full-scale output current.
50 Ω
1:1
IOUT1
100 Ω
AGND
RLOAD
50 Ω
IOUT2
50 Ω
Figure 35. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
28
www.ti.com
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
100 Ω
4:1
IOUT1
RLOAD
50 Ω
AGND
IOUT2
100 Ω
Figure 36. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
IOUT1
RLOAD
50 Ω
IOUT2
25 Ω
50 Ω
AGND
Figure 37. Driving a Doubly Terminated 50-Ω Cable Using Single-Ended Output
Sleep Mode
The DAC5674 features a power-down mode that turns off the output current and reduces the supply current
to less than 5 mA over the supply range of 3 V to 3.6 V and temperature range. The power-down mode is
activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the DAC5674 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node EXTIO. For a nominal
capacitor value of 0.1-µF power-down takes less than 5 µs, and power-up takes approximately 3 ms. With
external reference, power up takes 10 µs; power down remains the same.
DAC5674 Evaluation Board
A combo EVM board is available for the DAC5674 digital-to-analog converter for evaluation. This board allows
the user the flexibility to operate the DAC5674 in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital
inputs are designed to interface with a TMS320 DSP SDK or to be driven directly from various pattern
generators with the onboard option to add a resistor network for proper load termination. See the DAC5674 EVM
User’s Guide (SWRU007) for more information.
29
www.ti.com
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
DESIGNING THE PLL LOOP FILTER
The DAC5674 contains an external loop filter to set the bandwidth and phase margin of the PLL. For the external
second-order filter shown in Figure 38, the components R1, C1, and C2 are set by the user to optimize the PLL
for the application. The resistance R3 = 200 Ω. and the capacitance C3 = 8 pF are internal to the DAC5674.
Note that R1 and C1 can be reversed.
External
Internal
R3
C1
C2
C3
R1
Figure 38. DAC5674 Loop Filter
Typical DAC5674 Gvco at 255C
500
450
VCO Gain − MHz
400
350
300
250
200
150
100
50
0
0
100
200
300
Frequency − MHz
400
500
600
Figure 39. Typical VCO Gain vs VCO Frequency at 25°C
The typical VCO gain (Gvco) (the slope of VCO frequency vs voltage) as a function of VCO frequency for the
DAC5674 is shown in Figure 39. For the lowest possible phase noise, the VCO frequency should be chosen
so Gvco is minimized, where
Fvco = Fdata × Interpolation × PLL Divider:
For example, if Fdata = 100 MSPS and 2× interpolation is used, the PLL divider should be set to 2 to lock the
VCO at 400 MHz for a typical Gvco of 210 MHz/V. Note that the maximum specified VCO frequency range is
160 MHz to 400 MHz.
30
www.ti.com
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
The external loop filter components C1, C2, and R1 are given by choosing Gvco, N = Fvco/Fdata, the loop
phase margin φd and the loop bandwidth ωd. Except for applications where abrupt clock frequency changes
require a fast PLL lock time, it is suggested that φd be set to at least 80 degrees for stable locking and
suppression of the phase noise side lobes. Phase margins of 60 degrees or less have occasionally been
sensitive to board layout and decoupling details.
The optimum loop bandwidth ωd depends on both the VCO phase noise, which is largely a function of Gvco,
and the application. For the foregoing example with Gvco = 210 MHz/V, an ωd = 1 MHz would be typical, but
lower and higher loop bandwidths may provide better phase-noise characteristics. For a higher Gvco, for
example Gvco = 400 MHz/V, a ωd ≈ 7 MHz would be typical. However, it is suggested that the customer
experiment with varying the loop bandwidth by at least 1/2× through 2× to verify the optimum setting.
C1, C2, and R1 are then calculated by the following equations:
ǒ
Ǔ
C1 + t1 1– t2
t3
C2 + t1–t2
t3
R1 +
t3 2
t1(t3 * t2)
where
ǒ
K Kvco
tan f d ) secf d
t1 + d
w2
Ǔ
t2 +
d
ǒ
1
w d tan f d ) secf d
Ǔ
t3 +
tan f d ) secf d
wd
and
charge pump current:
iqp = 1 mA
vco gain:
Kvco = 2π × Gvco rad/V
Fvco/Fdata:
N = {2, 4, 8, 16, 32}
phase detector gain:
Kd = iqp × (2πN)−1 A/rad
An Excel spreadsheet is provided by TI for automatically calculating the values for C1, C2, and R.
Completing the preceding example with
PARAMETER
VALUE
UNIT
Gvco
2.10E+02
MHz/V
ωd
1.00E+00
MHz
N
4
φd
80
degrees
the component values are
C1 (F)
C2 (F)
R (W)
1.51E−08
1.16E−10
1.21E+02
As the PLL characteristics are not sensitive to these components, the closest 20% tolerance capacitor and 1%
tolerance resistor values can be used. If the calculation results in a negative value for C2 or an unrealistically
large value for C1, then the phase margin may need to be reduced slightly.
USING PowerPAD DEVICES
A thermal land should be placed on the top and bottom layers of the circuit board. The recommended thermal
land size for this package is 5 mm × 5 mm, with top and bottom layers connected by 9 vias. A thermal land size
of 3,8 mm × 3,8 mm (as used on the DAC5674 EVM) is adequate for this device.
31
www.ti.com
SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005
REVISION HISTORY
DATE
REV
PAGE
Aug. 2005
A
10–12
32
SECTION
Typical Characteristics
DESCRIPTION
Added a note that ac measurements are taken with the PLL off
15
Low-Pass/Low-Pass 4× Interpolation
Filter Operation
16
Low-Pass/High-Pass 4× Interpolation
Filter Operation
17
High-Pass/Low-Pass 4× Interpolation
Filter Operation
18
High-Pass/High-Pass 4× Interpolation
Filter Operation
18
DAC Sinx/x Output Attenuation
Added this new section
26
DAC Transfer Function
Updated DAC transfer equation with a more-accurate model
29
Sleep Mode
Corrected a word and added a sentence
30
PLL Loop Filter Components
Replaced with a new section, Designing the PLL Loop Filter
Updated the filter mode diagrams with more-realistic response
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC5674IPHP
ACTIVE
HTQFP
PHP
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC5674IPHPG4
ACTIVE
HTQFP
PHP
48
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC5674IPHPR
ACTIVE
HTQFP
PHP
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC5674IPHPRG4
ACTIVE
HTQFP
PHP
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC5674IPHPR
Package Package Pins
Type Drawing
HTQFP
PHP
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC5674IPHPR
HTQFP
PHP
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
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