1*WCMA2016U4B WCMA2016U4B 128K x 16 Static RAM be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15 ) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Features • High Speed — 55ns and 70ns speed availability • Low Voltage range: — 2.7V-3.3V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1MHz — Typical active current: 7 mA @ f = fmax Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power Functional Description The WCMA2016U4B is a high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This device is ideal for portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also Logic Block Diagram DATA IN DRIVERS A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SENSE AMPS RO W DE CO DER 1 0 128K x 16 RAM Array 2048 x 1024 I/O0 – I/O7 I/O8 – I/O15 A 11 A 12 A 13 A 14 A 15 COLUMN DECODER Powe r -Down Circuit BHE WE CE OE BLE A 16 • • • • Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE ) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A 0 through A16 ). If Byte High Enable (BHE ) is LOW, then data from I/O pins (I/O8 through I/O15 ) is written into the location specified on the address pins (A 0 through A16 ). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE ) is LOW, then data from memory will appear on I/O8 to I/O15 . See the truth table at the back of this data sheet for a complete description of read and write modes. The WCMA2016U4B is available in a 48-ball FBGA package. CE BHE BLE WCMA2016U4B Pin Configuration [1, 2] FBGA (Top View) 3 4 5 1 2 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 I/O3 V CC D VCC I/O12 DNU A16 I/O4 V SS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage to Ground Potential ... –0.5V to Vccmax + 0.5V Operating Range DC Voltage Applied to Outputs in High Z State [3] ....................................–0.5V to VCC + 0.5V Device Range WCMA2016U4B Industrial Ambient Temperature VCC –40°C to +85°C 2.7V to 3.3V DC Input Voltage [3] .................................-0.5V to VCC + 0.5V Product Portfolio Power Dissipation (Industrial) VCC Range(V) Product Speed (ns) VCC(min.) VCC(typ.)[4] VCC(max.) WCMA2016U4B 2.7 3.0 3.3 70 Operating, I CC (mA) f = 1 MHz f = fmax Standby, ISB2 (µA) Typ.[4] Max. Typ.[4] Max. Typ. [4] Max. 1.5 2 7 15 2 10 55 Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or Vss to ensure proper application. 3. VIL(min.) = –2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.) , T A = 25°C. 2 WCMA2016U4B Electrical Characteristics Over the Operating Range WCMA2016U4B-55 Parameter Description Test Conditions Min. Typ. [4] Max. VOH Output HIGH Voltage I OH = –1.0 mA VCC = 2.7V VO L Output LOW Voltage I O L = 2.1mA VCC = 2.7V VIH Input HIGH Voltage 2.2 VCC + 0.5V VIL Input LOW Voltage –0.3 I IX Input Leakage Current GND < VI < VCC I OZ Output Leakage Current GND < V O < VCC , Output Disabled I CC I SB1 VCC Operating Supply Current Automatic CE Power-Down Current— CMOS Inputs f = f MAX = 1/tRC f = 1 MHz 2.4 WCMA2016U4B-70 Min. Typ. [4] Max. 2.4 V 0.4 0.4 V 2.2 VCC + 0.5V V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA mA VCC = 3.3V IOUT = 0 mA CMOS Levels CE > V CC – 0.2V VIN > V CC – 0.2V or VIN < 0.2V, 7 15 7 15 1.5 3 1.5 3 2 10 2 10 µA f = fmax (Address and Data Only), f=0 (OE,WE,BHE and BLE) I SB2 Automatic CE Power-Down Current— CMOS Inputs CE > V CC – 0.2V VIN > V CC – 0.2V or VIN < 0.2V, f = 0, Vcc=3.3V Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF T A = 25°C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Symbol BGA Units Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance (Junction to Case)[5] Note: 5. Tested initially and after any design or process changes that may affect these parameters. 3 Unit WCMA2016U4B AC Test Loads and Waveforms R1 V CC ALL INPUT PULSES VCC Typ OUTPUT 10% GND Rise TIme: 1 V/ns R2 30 pF 90% 10% 90% Fall Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RT H OUTPUT V TH Parameters R1 3.0V 1.105 Unit KOhms R2 1.550 KOhms RTH VTH 0.645 1.75 KOhms Volts Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min. Typ.[4] 1.5 Max. Unit Vccmax V 7.5 µA VDR VCC for Data Retention I CCDR Data Retention Current t CDR[5] Chip Deselect to Data Retention Time 0 ns t R[6] Operation Recovery Time 70 ns VCC= 1.5V CE > VCC – 0.2V, VIN > VCC – 0.2V or V IN < 0.2V 0.5 Data Retention Waveform[7] DATA RETENTION MODE VCC VCC(min) VDR > 1.5 V tCDR VCC(min) tR CE or BHE .BLE Note: 6. Full Device AC operation requires linear VC C ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 7. BHE.BLE is the AND of both BHE and BLE . Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE . 4 WCMA2016U4B Switching Characteristics Over the Operating Range [8] 55ns Parameter Description Min 70 ns Max Min Max Unit READ CYCLE t RC Read Cycle Time t AA Address to Data Valid 55 t OHA Data Hold from Address Change t ACE CE LOW to Data Valid t DOE OE LOW to Data Valid t LZOE OE LOW to Low Z [9] 10 25 CE LOW to Low Z 10 [9, 11] t HZCE CE HIGH to High Z t PU CE LOW to Power-Up t PD CE HIGH to Power-Down t DBE BHE / BLE LOW to Data Valid [9] BHE / BLE LOW to Low Z t HZBE BHE / BLE HIGH to High Z[9, 11] ns 35 ns ns 25 25 t LZBE[10] 70 10 0 ns ns 5 25 [9] t LZCE 10 5 OE HIGH to High Z ns 70 55 [9, 11] t HZOE 70 55 ns ns 25 0 ns ns 55 70 ns 55 70 ns 5 5 25 ns 25 ns [12] WRITE CYCLE t WC Write Cycle Time 55 70 ns t SCE CE LOW to Write End 45 60 ns t AW Address Set-Up to Write End 45 60 ns t HA Address Hold from Write End 0 0 ns t SA Address Set-Up to Write Start 0 0 ns t PWE WE Pulse Width 40 50 ns t BW BHE / BLE Pulse Width 50 60 ns t SD Data Set-Up to Write End 25 30 ns t HD Data Hold from Write End 0 0 ns [9, 11] t HZWE WE LOW to High Z t LZWE WE HIGH to Low Z[9] 20 5 25 10 ns ns Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to V CC(typ.), and output loading of the specified IOL /I O H and 30 pF load capacitance. 9. At any given temperature and voltage condition, t HZCE is less than tLZCE , tHZBE is less than tLZBE, t HZOE is less than t LZOE, and t HZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10ns 11. t HZOE, t HZCE, t HZBE, and t HZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL , BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.. 5 WCMA2016U4B Switching Waveforms Read Cycle No. 1 (Address Transistion Controlled) [13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) DATA VALID [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE t DOE BHE/BLE ttLZOE LZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes: 13. Device is continuously selected. OE, CE = VIL, BHE, BLE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE, BHE, BLE transition LOW. 6 WCMA2016U4B Switching Waveforms (continued) Write Cycle No. 1(WE Controlled) [12, 16, 17] tWC ADDRESS tS C E CE tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 18 tHZOE Write Cycle No. 2 (CE Controlled) [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O DATAIN VALID NOTE 18 tHZOE Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period, the I/Os are in output state and input signals should not be applied. 7 tHD WCMA2016U4B Switching Waveforms (continued) [17] Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tS C E CE tBW BHE /BLE tAW tHA tSA tPWE WE tSD DATA I/O NOTE 18 tH D DATA IN VALID tLZWE tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17] tWC ADDRESS CE tS C E tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O DATAIN VALID NOTE 18 8 tHD WCMA2016U4B Typical DC and AC Parameters (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = V CC (typ.), TA = 25°C) Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 14.0 Access Time vs. Supply Voltage 12.0 60 10.0 10.0 (f = f max) 50 8.0 40 6.0 TAA (ns ) 8.0 ISB (µA) ICC (mA) 12.0 6.0 4.0 4.0 2.0 0 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) 20 10 2.0 (f = 1 MHz) 30 0 3.0 2.7 3.3 2.7 SUPPLY VOLTAGE (V) 3.0 3.3 SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE H X X X L Inputs/Outputs X X X High Z Deselect/Power-Down Standby (I SB) X H H High Z Deselect/Power-Down Standby (I SB) H L L L Data Out (I/OO –I/O1 5) Read Active (ICC) L H L H L Data Out (I/OO –I/O7 ); I/O 8–I/O 15 in High Z Read Active (ICC) L H L L H Data Out (I/O8 –I/O15 ); I/O 0–I/O 7 in High Z Read Active (ICC) L H H L L High Z Output Disabled Active (ICC) L H H H L High Z Output Disabled Active (ICC) L H H L H High Z Output Disabled Active (ICC) L L X L L Data In (I/O O–I/O15 ) Write Active (ICC) L L X H L Data In (I/O O–I/O7); I/O 8–I/O 15 in High Z Write Active (ICC) L L X L H Data In (I/O 8–I/O 15 ); I/O 0–I/O 7 in High Z Write Active (ICC) 9 Mode Power WCMA2016U4B Ordering Information Speed (ns) Ordering Code 70 WCMA2016U4B-FF70 55 WCMA2016U4B-FF55 Package Name Package Type FB48A 48-Ball Fine Pitch BGA 10 . Operating Range Industrial WCMA2016U4B Package Diagrams 48-Ball (6.0 mm x 8.0 mm x 1.0 mm) Fine Pitch BGA, FB48A Top View Bottom View 11 WCMA2016U4B Document Title: WCMA2016U4B, 128K x 16 STATIC RAM REV. Spec # ECN # Issue Date Orig. of Change ** 38-05320 117494 7/19/02 CBD 12 Description of Change New Datasheet