WINBOND W29GL064CT7A

W29GL064C
64M-BIT
3.0-VOLT PARALLEL FLASH MEMORY WITH
PAGE MODE
Publication Release Date: October 18, 2011
Preliminary - Revision E
BLANK
W29GL064C
Table of Contents
1
2
3
4
5
6
7
GENERAL DESCRIPTION ......................................................................................................... 1
FEATURES ................................................................................................................................. 1
PIN CONFIGURATIONS ............................................................................................................. 2
BLOCK DIAGRAM ...................................................................................................................... 3
PIN DESCRIPTION ..................................................................................................................... 3
ARRAY ARCHITECTURE ........................................................................................................... 4
6.1
H/L Sector Address Table ............................................................................................... 4
6.2
Top Sector Address Table .............................................................................................. 4
6.3
Bottom Sector Address Table ......................................................................................... 4
FUNCTIONAL DESCRIPTION.................................................................................................... 5
7.1
Device Bus Operation ..................................................................................................... 5
7.2
Instruction Definitions...................................................................................................... 6
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.19
7.2.20
7.2.21
7.2.22
7.2.23
7.3
Enhanced Sector Protect/Un-protect ............................................................................ 15
7.3.1
7.3.2
7.4
Lock Register .................................................................................................................. 16
Individual (Non-Volatile) Protection Mode ....................................................................... 17
Security Sector Flash Memory Region ......................................................................... 20
7.4.1
7.4.2
7.5
Reading Array Data .......................................................................................................... 6
Page Mode Read .............................................................................................................. 6
Device Reset Operation .................................................................................................... 7
Standby Mode ................................................................................................................... 7
Output Disable Mode ........................................................................................................ 7
Write Operation ................................................................................................................. 7
Byte/Word Selection ......................................................................................................... 8
Automatic Programming of the Memory Array .................................................................. 8
Erasing the Memory Array ................................................................................................ 9
Erase Suspend/Resume ............................................................................................... 10
Sector Erase Resume ................................................................................................... 10
Program Suspend/Resume ........................................................................................... 11
Program Resume .......................................................................................................... 11
Programming Operation ................................................................................................ 11
Buffer Write Abort ......................................................................................................... 12
Accelerated Programming Operation ............................................................................ 12
Automatic Select Bus Operation ................................................................................... 12
Automatic Select Operations......................................................................................... 13
Automatic Select Instruction Sequence ........................................................................ 13
Enhanced Variable IO (EVIO) Control .......................................................................... 14
Hardware Data Protection Options ............................................................................... 14
Inherent Data Protection ............................................................................................... 14
Power Supply Decoupling ............................................................................................. 14
Factory Locked: Security Sector Programmed and Protected at factory......................... 20
Customer Lockable: Security Sector Not Programmed or Protected .............................. 20
Instruction Definition Tables ......................................................................................... 21
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Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
7.6
Common Flash Memory Interface (CFI) Mode ............................................................. 25
7.6.1
8
8.4.1
8.5
8.6
11
Instruction Write Operation ............................................................................................. 33
Read / Reset Operation .................................................................................................. 34
Erase/Program Operation ............................................................................................... 36
Write Operation Status .................................................................................................... 45
WORD/BYTE CONFIGURATION (#BYTE)..................................................................... 49
DEEP POWER DOWN MODE........................................................................................ 51
WRITE BUFFER PROGRAM.......................................................................................... 51
Recommended Operating Conditions ........................................................................... 52
8.6.1
10
Switching Test Waveform ............................................................................................... 31
AC Characteristics ........................................................................................................ 32
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
9
Query Instruction and Common Flash memory Interface (CFI) Mode ............................. 25
ELECTRICAL CHARACTERISTICS ......................................................................................... 29
8.1
Absolute Maximum Stress Ratings ............................................................................... 29
8.2
Operating Temperature and Voltage ............................................................................ 29
8.3
DC Characteristics ........................................................................................................ 30
8.4
Switching Test Circuits.................................................................................................. 31
At Device Power-up ........................................................................................................ 52
8.7
Erase and Programming Performance ......................................................................... 53
8.8
Data Retention .............................................................................................................. 53
8.9
Latch-up Characteristics ............................................................................................... 53
8.10 Pin Capacitance ............................................................................................................ 53
PACKAGE DIMENSIONS ......................................................................................................... 54
9.1
TSOP 48-pin 12x20mm ................................................................................................ 54
9.2
TSOP 56-pin 14x20mm ................................................................................................ 55
9.3
Low-Profile Fine-Pitch Ball Grid Array, 64-ball 11x13mm (LFBGA64) ......................... 56
2
9.4
Thin & Fine-Pitch Ball Grid Array, 6x8 mm , ball pitch: 0.8 mm, ∅=0.4mm (TFBGA48)
57
ORDERING INFORMATION ..................................................................................................... 58
10.1 Ordering Part Number Definitions ................................................................................. 58
10.2 Valid Part Numbers and Top Side Marking .................................................................. 59
HISTORY .................................................................................................................................. 60
List of Figures
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 4-1
Figure 7-1
Figure 7-2
Figure 7-3
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
LFBGA64 TOP VIEW (FACE DOWN) ........................................................................... 2
56-PIN STANDARD TSOP (TOP VIEW) ........................................................................ 2
TFBGA48 TOP VIEW (FACE DOWN) ............................................................................ 2
48-PIN STANDARD TSOP (TOP VIEW) ........................................................................ 2
Block Diagram ................................................................................................................. 3
Enhanced Sector Protect/Un-protect IPB Program Algorithm ...................................... 15
Lock Register Program Algorithm ................................................................................. 16
IPB Program Algorithm ................................................................................................. 18
Maximum Negative Overshoot ..................................................................................... 29
Maximum Positive Overshoot ....................................................................................... 29
Switch Test Circuit ........................................................................................................ 31
Switching Test Waveform ............................................................................................. 31
ii
W29GL064C
Figure 8-5
Figure 8-6
Figure 8-7
Figure 8-8
Figure 8-9
Figure 8-10
Figure 8-11
Figure 8-12
Figure 8-13
Figure 8-14
Figure 8-15
Figure 8-16
Figure 8-17
Figure 8-18
Figure 8-19
Figure 8-20
Figure 8-21
Figure 8-22
Figure 8-23
Figure 8-24
Figure 8-25
Figure 8-26
Figure 8-27
Figure 9-1
Figure 9-2
Figure 9-3
Figure 9-4
Figure 10-1
Instruction Write Operation Waveform.......................................................................... 33
Read Timing Waveform ................................................................................................ 34
#RESET Timing Waveform ........................................................................................... 35
Automatic Chip Erase Timing Waveform ...................................................................... 36
Automatic Chip Erase Algorithm Flowchart .................................................................. 37
Automatic Sector Erase Timing Waveform ................................................................... 38
Automatic Sector Erase Algorithm Flowchart ............................................................... 39
Erase Suspend/Resume Flowchart .............................................................................. 40
Automatic Program Timing Waveform .......................................................................... 41
Accelerated Program Timing Waveform ....................................................................... 41
CE# Controlled Write Timing Waveform ....................................................................... 42
Automatic Programming Algorithm Flowchart .............................................................. 43
Silicon ID Read Timing Waveform ................................................................................ 44
Data# Polling Timing Waveform (During Automatic Algorithms) .................................. 45
Status Polling for Word Programming/Erase ................................................................ 46
Status Polling for Write Buffer Program Flowchart ....................................................... 47
Toggling Bit Timing Waveform (During Automatic Algorithms) .................................... 48
Toggle Bit Algorithm...................................................................................................... 49
#BYTE Timing Waveform For Read operations ........................................................... 50
Page Read Timing Waveform ....................................................................................... 50
Deep Power Down mode Waveform ............................................................................ 51
Write Buffer Program Flowchart ................................................................................... 51
AC Timing at Device Power-Up .................................................................................... 52
TSOP 48-pin 12x20mm ................................................................................................ 54
TSOP 56-pin 14x20mm ................................................................................................ 55
LFBGA 64-ball 11x13mm ............................................................................................. 56
TFBGA 48-Ball 6x8mm ................................................................................................. 57
Ordering Part Numbering .............................................................................................. 58
List of Tables
Table 6-1
Table 6-2
Table 6-3
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
High/Low Sector Table.................................................................................................... 4
Top Boot Sector Table .................................................................................................... 4
Bottom Boot Sector Table ............................................................................................... 4
Device Bus Operation ..................................................................................................... 5
Device Bus Operation (continue) .................................................................................... 5
Polling During Embedded Program Operation ............................................................... 8
Polling During Embedded Sector Erase Operation ........................................................ 9
Polling During Embedded Chip Erase Operation ......................................................... 10
Polling During Embedded Erase Suspend ................................................................... 10
Polling During Embedded Program Suspend ............................................................... 11
Polling Buffer Write Abort Flag ..................................................................................... 12
Auto Select for MFR/Device ID/Secure Silicon/Sector Protect Read .......................... 13
Lock Register Bits ......................................................................................................... 16
Sector Protection Status Table ..................................................................................... 19
Factory Locked: Security Sector ................................................................................... 20
ID Reads, Sector Verify, and Security Sector Entry/Exit .............................................. 21
Program, Write Buffer, CFI, Erase and Suspend ......................................................... 22
Deep Power Down ........................................................................................................ 22
Lock Register and Global Non-Volatile ......................................................................... 23
IPB Functions ............................................................................................................... 23
Volatile DPB Functions ................................................................................................. 24
CFI Mode: ID Data Values ............................................................................................ 25
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Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
Table 7-20
Table 7-21
Table 7-22
Table 8-1
Table 8-2
Table 8-3
Table 8-5
Table 8-8
Table 8-10
Table 8-11
Table 8-12
Table 8-13
Table 10-1
Table 11-1
CFI Mode: System Interface Data Values .................................................................... 26
CFI Mode: Device Geometry Data Values.................................................................... 27
CFI mode: Primary Vendor-Specific Extended Query Data Values ............................. 28
Absolute Maximum Stress Ratings ............................................................................... 29
Operating Temperature and Voltage ............................................................................ 29
DC Characteristics ........................................................................................................ 30
AC Characteristics ........................................................................................................ 33
AC Characteristics for Deep Power Down .................................................................... 51
AC Characteristics for Erase and Programming Performance ..................................... 53
Data Retention .............................................................................................................. 53
Latch-up Characteristics ............................................................................................... 53
Pin Capacitance ............................................................................................................ 53
Valid Part Numbers and Markings ................................................................................ 59
Revision History ............................................................................................................ 60
iv
W29GL064C
1
GENERAL DESCRIPTION
The W29GL064C Parallel Flash memory provides a storage solution for embedded system
applications that require better performance, lower power consumption and higher density. This device
has a random access speed of 70 ns and a fast page access speed of 25 ns, as well as, significantly
faster program and erase times than the comparable products available on the market today. The
W29GL064C also offers special features such as Compatible Manufacturer ID that makes the device
industry standard compatible without the need to change firmware.
2
FEATURES
• 32k-Word/64k-Byte uniform sector
architecture
– Total 128 uniform sectors
– Total 127 uniform sectors + eight 4kWord/8k-Byte sectors
• Faster Erase and Program time
– Erase is1.5x faster than industry
standard
– Program is 2x faster than industry
standard
– Allows for improved production
throughput and faster field updates
• 16-Word/32-Byte write buffer
– Reduces total program time for
multiple-word updates
• CFI (Common Flash Interface) support
• 8-Word/16-Byte page read buffer
• Single 3V Read/Program/Erase (2.7 3.6V)
• Secured Silicon Sector area
– Programmed and locked by the
customer or during production
– 128-word/256-byte sector for
permanent, safe identification using an
8-word/16-byte random electronic
serial number
• Enhanced Variable IO control
– All input levels (address, control, and
DQ) and output levels are determined
by voltage on the EVIO input. EVIO
ranges from 1.65 to VCC
• #WP/ACC Input
– Accelerates programming time (when
VHH is applied) for greater throughput
during system production
– Protects first or last sector regardless
of sector protection settings
• Enhanced Sector Protect using
Dynamic and Individual mechanisms
• Polling/Toggling methods are used to
detect the status of program and erase
operation
• Hardware reset input (#reset) resets
device
• Suspend and resume commands used
for program and erase operations
• Ready/#Busy output (RY/#BY) detects
completion of program or erase cycle
• More than 100,000 erase/program
cycles
• Packages
– Uniform Sector (H/L)
56-pin TSOP
64-ball LFBGA
– Boot Sector (T/B)
48-pin TSOP
48-ball TFBGA
64-ball LFBGA
• More than 20-year data retention
• Low power consumption
• Deep power down mode
•
Wide temperature range
• Compatible manufacturer ID for drop-in
replacement
– No firmware change is required
1
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
3
PIN CONFIGURATIONS
A6
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
#BYTE
DQ15/A-1
VSS
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
#WE
#RESET
A21
A19
DQ5
DQ12
VCC
DQ4
A3
B3
RY/#BY #WP/ACC
Figure 3-1
Figure 3-2
LFBGA64 TOP VIEW
(FACE DOWN)
56-PIN STANDARD TSOP
(TOP VIEW)
2
C3
D3
E3
F3
G3
H3
A18
A20
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
#CE
#OE
VSS
Figure 3-3
TFBGA48 TOP VIEW
(FACE DOWN)
Figure 3-4
48-PIN STANDARD TSOP
(TOP VIEW)
W29GL064C
4
BLOCK DIAGRAM
VCC
EVIO
VSS
#CE
#OE
#WE
RY/#BY
#BYTE
CONTROL
OUTPUT
BUFFER
DECODER
MAIN ARRAY
#RESET
#WP/ACC
DQ15/A-1
A0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
A21
Figure 4-1
5
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ15/A-1
Block Diagram
PIN DESCRIPTION
SYMBOL
A0-A21
DQ0-DQ14
DQ15/A-1
#CE
#OE
#WE
#WP/ACC
#BYTE
#RESET
RY/#BY
VCC
EVIO
VSS
NC
Table 5-1
PIN NAME
Address Inputs
Data Inputs/Outputs
Word mode
DQ15 is Data Input/Output
Byte mode
A-1 is Address Input
Chip Enable
Output Enable
Write Enable
Hardware Write Protect/ Acceleration Pin
Byte Enable
Hardware Reset
Ready/Busy Status
Power Supply
Enhanced Variable IO Supply (No connect for top/bottom LFBGA64 configurations)
Ground
No Connection
Pin Description
3
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
ARRAY ARCHITECTURE
6
6.1
H/L Sector Address Table
Sector
Sector Address
A21-A15
Sector Size
(KByte/KWord)
SA00
0000000
64/32
000000h
00FFFFh
000000h
007FFFh
0000001
64/32
.
.
1111110
64/32
1111111
64/32
High/Low Sector Table
010000h
.
7E0000h
7F0000h
01FFFFh
.
7EFFFFh
7FFFFFh
008000h
.
3F0000h
3F8000h
00FFFFh
.
3FFFFFh
3FFFFFh
SA01
.
SA126
SA127
Table 6-1
X8
Start / Finish
X16
Start / Finish
Note: The address range is [A21:A-1] in byte mode (#BYTE = VIL) or [A21:A0] in word mode (#BYTE = VIH)
6.2
Top Sector Address Table
Sector
Sector Address
A21-A12
Sector Size
(KByte/KWord)
SA00
SA01
0000000xxx
0000001xxx
64/32
64/32
000000h
010000h
00FFFFh
01FFFFh
000000h
008000h
007FFFh
00FFFFh
.
.
1111110xxx
64/32
1111111000
8/4
.
.
1111111111
8/4
Top Boot Sector Table
.
7E0000h
7F0000h
.
7FE000h
.
7EFFFFh
7F1FFFh
.
7FFFFFh
.
3F0000h
3F8000h
.
3FF000h
.
3FFFFFh
3F8FFFh
.
3FFFFFh
.
SA126
SA127
.
SA134
Table 6-2
X8
Start / Finish
X16
Start / Finish
Note: The address range is [A21:A-1] in byte mode (#BYTE = VIL) or [A21:A0] in word mode (#BYTE = VIH)
6.3
Bottom Sector Address Table
Sector
Sector Address
A21-A12
Sector Size
(KByte/KWord)
SA00
0000000000
8/4
.
SA07
SA08
.
SA134
Table 6-3
.
.
0000000111
8/4
0000001xxx
64/32
.
.
1111111xxx
64/32
Bottom Boot Sector Table
X8
Start / Finish
X16
Start / Finish
000000h
001FFFh
000000h
000FFFh
.
00E000h
010000h
.
7F0000h
.
00FFFFh
01FFFFh
.
7FFFFFh
.
007000h
008000h
.
3F8000h
.
007FFFh
00FFFFh
.
3FFFFFh
Note: The address range is [A21:A-1] in byte mode (#BYTE = VIL) or [A21:A0] in word mode (#BYTE = VIH)
4
W29GL064C
7
FUNCTIONAL DESCRIPTION
7.1
Device Bus Operation
Mode Select #Reset
Device Reset
#CE
L
#WE #OE Address
X
X
Standby
VCC±0.3V VCC±0.3V X
Mode
Output
H
L
H
Disable
Read Mode
H
L
H
Write
H
L
L
Accelerated
H
L
L
Program
Table 7-1
Device Bus Operation
Notes:
1.
2.
3.
4.
(4)
#BYTE
Data I/O
DQ[7:0]
X
X
High-Z
X
X
High-Z
H
X
High-Z
L
H
AIN
AIN
DOUT
DIN
H
AIN
DIN
VIL
VIH #WP/ACC
Data I/O DQ[15:8]
HighL/H
Z
HighHigh-Z
H
Z
HighHigh-Z
L/H
Z
DOUT
L/H
DQ[14:8]=High(1,2)
DIN Note
Z
DQ15=A-1
DIN
VHH
High-Z
For High/Low configuration, either the first or last sector was protected if #WP/ACC=VIL.
For Top/Bottom Boot configuration, either the top or bottom two sectors are protected if #WP/ACC=VIL.
When #WP/ACC = VIH, the protection conditions of the outmost sector depends on previous protection conditions.
Refer to the enhanced protect feature.
DQ[15:0] are input (DIN) or output (DOUT) pins according to the requests of instruction sequence, sector protection,
or data polling algorithm.
In Word Mode (Byte#=VIH), the addresses are A21 to A0. In Byte Mode (Byte#=VIL), the addresses are A21 to A-1
(DQ15),.
Control Inputs A21
#CE #WE #OE ~12
Description
Device ID
Read Silicon ID MFR
Code
A11
~10
A9
A8
A5
~7 A6 ~4
DQ[7:0]
DQ[15:8]
A3
~2 A1 A0 T/B H/L BYTE WORD
L
H
L
X
X
VHH
X
L
X
Cycle 1
L
H
L
X
X
VHH
X
L
X
Cycle 2
L
H
L
X
X
VHH
X
L
X
Cycle 3
L
H
L
X
X
VHH
X
L
X
H
H
L
H
L
SA
X
VHH
X
L
X
L
Sector Lock Status
(1)
Verification
L
L
L
01
X
00
L
L
H
7E
H
H
L
X
22
10 0C
01(T)
H
01
00(B)
X
22
X
22
H
L
01/00
X
X
Secure Sector (H)
(2)
L
H
L
X
X
VHH
X
L
X
L
H
H
9A/1A
X
X
Secure Sector (L)
(2)
L
H
L
X
X
VHH
X
L
X
L
H
H
8A/0A
X
X
Table 7-2
Notes:
1.
2.
Device Bus Operation (continue)
Sector unprotected code:00h. Sector protected code:01h.
Factory locked code: #WP protects high address sector: 9Ah. #WP protects low address sector: 8Ah. Factory
unlocked code: #WP protects high address sector: 1Ah. #WP protects low address sector: 0Ah
5
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
7.2
Instruction Definitions
The device operation can be initiated by writing specific address and data commands or sequences
into the instruction register. The device will be reset to reading array data when writing incorrect
address and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
7.2.1
Reading Array Data
The default state after power up or a reset operation is the Read mode.
To execute a read operation, the chip is enabled by setting #CE and #OE active and #WE high. At the
same time, the required address or status register location is provided on the address lines. The
system reads the addressed location contents on the Data IO pins after the tCE and tOE timing
requirements have been met. Output data will not be accessible on the Data IO pins if either the
device or it’s outputs are not enabled by #CE or #OE being High, and the outputs will remain in a tristate condition.
When the device completes an embedded memory operation (i.e., Program, automatic Chip Erase or
Sector Erase) successfully, it will return to the Read mode and from any address in the memory array
the data can be read. However, If the embedded operation fails to complete, by verifying the status
register bit DQ5 (exceeds time limit flag) going high during the operations, at this time system should
execute a Reset operation causing the device to return to Read mode.
Some operating states require a reset operation to return to Read mode such as:
•
•
Time-out condition during a program or erase failed condition, indicated by the status register
bit DQ5 going High during the operation. Failure during either of these states will prevent the
device from automatically returning to Read mode.
During device Auto Select mode or CFI mode, a reset operation is required to terminate their
operation.
In the above two situations, the device will not return to the Read mode unless a reset operation is
executed (either hardware reset or software reset instruction) or the system will not be able to read
array data.
The device will enter Erase-Suspended Read mode if the device receives an Erase Suspend
instruction while in the Sector Erase state. The erase operation will pause (after a time delay not
exceeding 20µs) prior to entering Erase-Suspend Read mode. At this time data can be programmed
or read from any sector that is not being erased. Another way to verify device status is to read the
addresses inside the sectors being erased. This will only provide the contents of the status register.
Program operation during Erase-Suspend Read mode of valid sector(s) will automatically return to the
Erase-Suspend Read mode upon successful completion of the program operation.
An Erase Resume instruction must be executed to exit the Erase-Suspended Read mode, at which
time suspended erase operations will resume. Erase operation will resume where it left off and
continue until successful completion unless another Erase Suspend instruction is received.
7.2.2
Page Mode Read
The Page Mode Read has page sizes of 16 bytes or 8 words. The higher addresses A[21:3] accesses
the desired page. To access a particular word or byte in a page, it is selected by A[2:0] for word mode
and A[2:0,A-1] for byte mode. Page mode can be turned on by keeping “page-read address” constant
and changing the “intra-read page” addresses. The page access time is tAA or tCE, followed by tPA for
the page read time. When #CE toggles, access time is tAA or tCE.
6
W29GL064C
7.2.3
Device Reset Operation
Pulling the #RESET pin Low for a period equal to or greater than tRP will return the device to Read
mode. If the device is performing a program or erase operation, the reset operation will take at most a
period of tREADY1 before the device returns to Read mode. The RY/#BY pin will remain Low (Busy
Status) until the device returns to Read mode.
Note, the device draws larger current if the #RESET pin is held at voltages greater that GND+0.3V
and less than or equal to VIL. When the #RESET pin is held a GND±0.3V, the device only consumes
Reset (ICC5) current.
It is recommended to tie the system reset signal to the #RESET pin of the flash memory. This allows
the device to be reset with the system and puts it in a state where the system can immediately begin
reading boot code from it.
Executing the Reset instruction will reset the device back to the Read mode in the following situations:
•
During an erase instruction sequence, before the full instruction set is completed.
•
Sector erase time-out period
•
Erase failed, while DQ5 is High.
•
During program instruction sequence, before the full instruction set is completed, including the
erase-suspended program instruction.
•
Program failed, while DQ5 is High as well as the erase-suspended program failure.
•
Auto-select mode
•
CFI mode
•
The user must issue a reset instruction to reset the device back to the Read mode when the
device is in Auto-Select mode or CFI mode, or when there is a program or erase failure (DQ5
is High).
•
When the device is performing a Programming (not program fail) or Erasing (Not erase fail)
function, the device will ignore reset commands.
7.2.4
Standby Mode
Standby mode is entered when both #RESET and #CE are driven to VCC ±300mV (inactive state).
(Note, if both pins are not within the EVIO ±0.3V, but at VIH, standby current will be greater.) At this
time output pins are placed in the high impedance state regardless of the state of the #WE or #OE
pins and the device will draw minimal standby current (ICC4). If the device is deselected during erase
or program operation, the device will draw active current until the operation is completed.
7.2.5
Output Disable Mode
The #OE pin controls the state of the Data IO pins. If #OE is driven High (VIH), all Data IO pins will
remain at high impedance and if driven Low, the Data IO pins will drive data ( #OE has no affect on
the RY/BY# output pin).
7.2.6
Write Operation
To execute a write operation, Chip Enable (#CE) pin is driven Low and the Output Enable (#OE) is
pulled high to disable the Data IO pins to a high impedance state. The desired address and data
should be present on the appropriate pins. Addresses are latched on the falling edge of either #WE or
#CE and Data is latched on the rising edge or either #CE or #WE. To see an example, please refer to
timing diagrams in Figure 8-5 and Figure 8-15. If an invalid write instruction, not defined in this
datasheet is written to the device, it may put the device in an undefined state.
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Preliminary - Revision E
W29GL064C
7.2.7
Byte/Word Selection
To choose between the Byte or Word mode, the #BYTE input pin is used to select how the data is
input/output on the Data IO pins and the organization of the array data. If the #BYTE pin is driven
High, Word mode will be selected and all 16 Data IO pins will be active. If the #BYTE is pulled Low,
Byte mode will be active and only Data IO DQ[7:0] will be active. The remaining Data IO pins
(DQ[14:8]) will be in a high impedance state and DQ15 becomes the A-1 address input pin.
7.2.8
Automatic Programming of the Memory Array
To program the memory array in Byte or Word mode, refer to the Instruction Definition Tables for
correct cycle defined instructions that include the 2 unlocking instruction cycles, the A0h program cycle
instruction and subsequent cycles containing the specified address location and the byte or word
desired data content, followed by the start of the embedded algorithm to automatically program the
array.
Once the program instruction sequence has been executed, the internal state machine commences
execution of the algorithms and timing necessary for programming and cell verification. Included in this
operation is generating suitable program pulses, checking cell threshold voltage (VT) margins, and if
any cells do not pass verification or have acceptable margins, repetitive program pulse sequence will
be cycled again. The internal process mechanisms will protect cells that do pass margin and
verification tests from being over-programmed by prohibiting further program pulses to passing cells
as failing cells continue to be run through the internal programming sequence until the pass.
This feature allows the user to only perform the auto-programming sequence once and the device
state machine takes care of the program and verification process.
Array bits during programming can only change a bit status of “1” (erase state) to a “0” (programmed
state). It is not possible to do the reverse with a programming operation. This can only be done by first
performing an erase operation. Keep in mind, the internal write verification only checks and detects
errors in cases where a “1” is not successfully programmed to “0”.
During the embedded programming algorithm process any commands written to the device will be
ignored, except hardware reset or programs suspend instruction. Hardware reset will terminate the
program operation after a period of time, not to exceed 10µs. If in the case a Program Suspend was
executed, the device will enter the program suspend read mode. When the embedded program
algorithm is completed or the program is terminated by a hardware reset, the device will return to
Read mode.
The user can check for completion by reading the following bits in the status register, once the
embedded program operation has started:
Status
DQ7
DQ6
DQ5
In progress
DQ7#
Toggling
0
Exceeded time
DQ7#
Toggling
1
limit
Table 7-3
Polling During Embedded Program Operation
Note:
1.
DQ1
0
N/A
RY/#BY
0
0
1
RY/#BY is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
8
W29GL064C
7.2.9
Erasing the Memory Array
Sector Erase and Chip Erase are the two possible types of operations executed on the memory array.
Sector Erase operation erases one or more selected sectors and this can be simultaneous. Chip
Erase operation erases the entire memory array, except for any protected sectors.
7.2.9.1
Sector Erase
The sector erase operation returns all selected sectors in memory to the “1” state, effectively clearing
all data. This action requires six instruction cycles to commence the erase operation. The unlock
sequence is the first two cycles, followed by the configuration cycle, the fourth and fifth are
also ”unlock cycles”, and the Sector Erase instruction is the sixth cycle. An internal 50µs time-out
counter is started once the sector erase instruction sequence has been completed. During this time,
additional sector addresses and Sector Erase commands may be issued, thus allowing for multiple
sectors to be selected and erased simultaneously. Once the 50µs time-out counter has reached its
limit, no additional command instructions will be accepted and the embedded sector erase algorithm
will commence.
Note, that the 50µs time-out counter restarts after every sector erase instruction sequence. The device
will abort and return to Read mode, if any instruction other than Sector Erase or Erase Suspend is
attempted during the time-out period.
Once the embedded sector erase algorithm begins, all instructions except Erase Suspend or
Hardware Reset will be ignored. The hardware reset will abort the erase operation and return the
device to the Read mode.
The embedded sector erase algorithm status can be verified by the following:
Status
DQ7
DQ6
DQ5
Time-out period
0
Toggling
0
0
In progress
0
Toggling
0
1
Exceeded time limit
0
Toggling
1
1
Table 7-4
Polling During Embedded Sector Erase Operation
Note:
1.
2.
3.
4.
1
DQ3
DQ2
RY/#BY
Toggling
Toggling
Toggling
0
0
0
2
The DQ3 status bit is the 50µs time-out indicator. When DQ3=0, the 50µs time-out counter has not yet reached zero
and the new Sector Erase instruction maybe issued to specify the address of another sector to be erased. When
DQ3=1, the 50µs time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend is
the only valid instruction that maybe issued once the embedded erase operation is underway.
RY/#BY is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
When an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any data
changes in the protected sector(s). DQ7 will output “0” and DQ6 will toggle briefly (100µs or less) before aborting and
returning the device to Read mode. If unprotected sectors are also specified, however, they will be erased normally
and the protected sector(s) will remain unchanged.
DQ2 is a localized indicator showing a specified sector is undergoing erase operation or not. DQ2 toggles when user
reads at the addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase
suspend mode).
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Preliminary - Revision E
W29GL064C
7.2.9.2
Chip Erase
The Chip Erase operation returns all memory locations containing a bit state of “0” to the “1” state,
effectively clearing all data. This action requires six instruction cycles to commence the erase
operation. The unlock sequence is the first two cycles, followed by the configuration cycle, the fourth
and fifth are also ”unlock cycles”, and the sixth cycle initiates the chip erase operation.
Once the chip erase algorithm begins, no other instruction will be accepted. However, if a hardware
reset is executed or the operating voltage is below acceptable levels, the chip erase operation will be
terminated and automatically returns to Read mode.
The embedded chip erase algorithm status can be verified by the following:
Status
DQ7
DQ6
DQ5
In progress
0
Toggling
0
Exceeded time limit
0
Toggling
1
Table 7-5
Polling During Embedded Chip Erase Operation
Note:
1.
7.2.10
DQ2
RY/#BY
Toggling
Toggling
0
0
1
RY/#BY is an open drain pin and should be connected to VCC through a high value pull-up resistor.
Erase Suspend/Resume
If there is a sector erase operation in progress, an Erase Suspend instruction is the only valid
instruction that may be issued. Once the Erase Suspend instruction is executed during the 50µs timeout period following a Sector Erase instruction, the time-out period will terminate right away and the
device will enter Erase-Suspend Read mode. If an Erase Suspend instruction is executed after the
sector erase operation has started, the device will not enter Erase-Suspended Read mode until
approximately 20µs (5µs typical) time has elapsed. To determine the device has entered the EraseSuspend Read mode, use DQ6, DQ7 and RY/#BY status to verify the state of the device.
Once the device has entered Erase-Suspended Read mode, it is possible to read or program any
sector(s) except those being erased by the erase operation. Only the contents of the status register is
present when attempting to read a sector that has been scheduled to erase or be programmed when
in the suspend mode. A resume instruction must be executed and recommend checking DQ6 toggle
bit status, before issuing another erase instruction.
The status register bits can be verified to determine the current status of the device:
Status
DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/#BY
Erase suspend read in erase suspended sector
1 No toggle 0 N/A Toggle N/A
1
Erase suspend read in non-erase suspended sector
Data Data Data Data Data Data
1
Erase suspend program in non-erase suspended sector DQ7# Toggle 0 N/A N/A N/A
0
Table 7-6
Polling During Embedded Erase Suspend
Instruction sets such as read silicon ID, sector protect verify, program, CFI query and erase resume
can also be executed during Erase-Suspend mode, except sector and chip erase.
7.2.11 Sector Erase Resume
Only in the Erase-Suspended Read mode can the Sector Erase Resume instruction be a valid
command. Once erase resumes, another Erase Suspend instruction can be executed, but allow a
400µs interval between Erase Resume and the next Erase Suspend instruction.
10
W29GL064C
7.2.12 Program Suspend/Resume
Once a program operation is in progress, a Program Suspend is the only valid instruction that maybe
executed. Verifying if the device has entered the Program-Suspend Read mode after executing the
Program-Suspend instruction, can be done by checking the RY/#BY and DQ6. Programming should
halt within 15µs maximum (5µs typical).
Any sector(s) can be read except those being program suspended. Trying to read a sector being
program suspended is invalid. Before another program operation can be executed, a Resume
instruction must be performed and DQ6 toggling bit status has to be verified. Use the status register
bits shown in the following table to determine the current state of the device:
Status
DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/#BY
Program suspend read in program suspended sector
Invalid
Program suspend read in non-program suspended sector Data Data Data Data Data Data
Table 7-7
Polling During Embedded Program Suspend
1
1
Instruction sets such as read silicon ID, sector protect verify, program, CFI query can also be executed
during Program/Erase-Suspend mode.
7.2.13 Program Resume
The program Resume instruction is valid only when the device is in Program-Suspended mode. Once
the program resumes, another Program Suspend instruction can be executed. Insure there is at least
a 5µs interval between Program Resume and the next Suspend instruction.
7.2.14 Programming Operation
Write Buffer Programming Operation, programs 32-bytes or 16-words in a two step programming
operation. To begin execution of the Write Buffer Programming, start with the first two unlock cycles,
the third cycle writes the programming Sector Address destination followed by the Write Buffer Load
Instruction (25h). The fourth cycle repeats the Sector Address, while the write data is the number of
intended word locations to be written minus one. (Example, if the number of word locations to be
th
written is 9, then the value would be 8h.) The 5 cycle is the first starting address/data set. This will be
the first pair to be programmed and consequentially, sets the “write-buffer-page” address. Repeat
Cycle 5 format for each additional address/data sets to be written to the buffer. Keep in mind all sets
must remain within the write buffer page address range. If not, operation will ABORT.
The “write-buffer-page” is selected by choosing address A[21:5].
The second step will be to program the contents of the write buffer page. This is done with one cycle,
containing the sector address that was used in step one and the “Write to Buffer Program Confirm”
instruction (29h).
Standard suspend/resume commands can be used during the operation of the write-buffer. Also, once
the write buffer programming operation is finished, it’ll return to the normal READ mode.
Write buffer programming can be conducted in any sequence. However the CFI functions, autoselect,
Secured Silicon sector are not functional when program operation is in progress. Multiple write buffer
programming operations on the same write buffer address range without intervention erase is
accessible. Any bit in a write buffer address range cannot be programmed from 0 back to 1.
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W29GL064C
7.2.15 Buffer Write Abort
Write Buffer Programming Sequence will ABORT, if the following condition takes place:
•
The word count minus one loaded is bigger than the page buffer size (32) during, “Number of
Locations to Program.”
•
Sector Address written is not the same as the one specified during the Write-Buffer-Load
instruction.
•
If the Address/Data set is not inside the Write Buffer Page range which was set during cycle
5’s first initial write-buffer-page select address/data set.
•
No “Program Confirm Instruction” after the assigned number of “data load” cycles.
After Write Buffer Abort, the status register will be DQ1=1, DQ7 = DATA# (last address loaded),
DQ6=toggle, DQ5=0. This status represents a Write Buffer Programming Operation was ABORTED. A
Write-to-Buffer-Abort Reset instruction sequence has to be written to reset the device back to the read
array mode.
DQ1 is the bit for Buffer Write Abort. When DQ1=1, the device will abort from buffer write operation
and go back to read status register shown in the following table:
Status
DQ7
DQ6
Buffer Write Busy
DQ7#
Toggle
Buffer Write Abort
DQ7#
Toggle
Buffer Write Exceeded Time Limit
DQ7#
Toggle
Table 7-8
Polling Buffer Write Abort Flag
DQ5
DQ3
DQ2
DQ1
RY/#BY
0
0
1
N/A
N/A
N/A
N/A
N/A
N/A
0
1
0
0
0
0
7.2.16 Accelerated Programming Operation
The device will enter the Accelerated Programming mode by applying high voltage (VHH) to the
#WP/ACC pin. Accelerated Programming mode allows the system to skip the normal unlock
sequences instruction and program byte/word locations directly. The current drawn from the #WP/ACC
pin during accelerated programming is no more than IACC1. Important Note: Do not exceed 10
accelerated programs per sector. (#WP/ACC should not be held at VHH for any other function except
for programming or damage to the device may occur.)
7.2.17 Automatic Select Bus Operation
There are basically two methods to access Automatic Selection Operations; Automatic Select
Instructions through software commands and High Voltage applied to A9. See Automatic Select
Instruction Sequence later on in this section for details of equivalent instruction operations that do not
require the use of VHH. The following five bus operations require A9 to be raised to VHH.
7.2.17.1
Sector Lock Status Verification
To verify the protected state of any sector using bus operations, execute a Read Operation with VHH
applied to A9, the sector address present on address pins A[21:12], address pins A6, A3, A2, and A0
held Low, and address pins A1 held High. If DQ0 is Low, the sector is considered not protected, and if
DQ0 is High, the sector is considered to be protected.
7.2.17.2
Read Silicon Manufacturer ID Code
Winbond’s 29GL family of Parallel Flash memories features an Industry Standard compatible
Manufacturer ID code of 01h. To verify the Silicon Manufacturer ID code, execute a Read Operation
with VHH applied to the A9 pin and address pins A6, A3, A2, A1 and A0 are held Low. The ID code
can then be read on data bits DQ[7:0].
12
W29GL064C
7.2.17.3
Read Silicon Device ID Code
To verify the Silicon Device ID Codes, execute a Read Operation with VHH applied to the A9 pin and
address pins A6, A3, A2, A1, and A0 have several bit combinations to return the Winbond Device ID
codes of 7Eh, 21h or 01h, which is shown on the data bits DQ[7:0]. See Table 7-2.
7.2.17.4
Read Indicator Bit DQ7 for Security Sector High and Low Address
To verify that the Security Sector has been factory locked, execute a Read Operation with VHH applied
to A9, address pins A6, A3, and A2 are held Low, and address pins A1 and A0 are held High. If the
Security Sector has been factory locked, the code 9Ah(Highest Address Sector) or 8Ah(Lowest
Address Sector) will be shown on the data bits DQ[7:0]. Otherwise, the factory unlocked code of
1Ah(H)/0A(L) will be shown.
7.2.18 Automatic Select Operations
The Automatic Select instruction show in Table 7-13 can be executed if the device is in one of the
following modes; Read, Program Suspended, Erase-Suspended Read, or CFI. At which time the user
can issue (two unlock cycles followed by the Automatic Select instruction 90h) to enter Automatic
Select mode. Once in the Automatic Select mode, the user can query the Manufacturer ID, Device ID,
Security Sector locked status, or Sector protected status multiple times without executing the unlock
cycles and a Automatic Select instruction (90h) again.
Once in Automatic Select mode, executing a Reset instruction (F0h) will return the device back to the
valid mode from which it left when the Automatic Select mode was first executed.
Another way previously mentioned to enter Automatic Select mode is to use one of the bus operation
shown Table 7-2 in Device Bus Operation. Once the high voltage (VHH) is removed from the A9 pin,
the device will return back to the valid mode from which it left when the Automatic Select mode was
first executed.
7.2.19
Automatic Select Instruction Sequence
Accessing the manufacturer ID, device ID, and verifying whether or not secured silicon is locked and
whether or not a sector protected is the purpose of Automatic Select mode. There are four instruction
cycles that comprise the Automatic Select mode. The first two cycles are write unlock commands,
followed by the Automatic Select instruction (90h). The fourth cycle is a read cycle, and the user may
read at any address any number of times without entering another instruction sequence. To exit the
Automatic Select mode and back to read array, the Reset instruction is necessary. No other
instructions are allowed except the Reset Instruction once Automatic Select mode has been selected.
Refer to the following table for more detailed information.
Data (hex)
Representation
01
01
227E/220C/2201
7E/0C/01
227E/2210/2201(T)/2200(B)
7E/10/01(T)/00(B)
9A/1A(H)
Word
X03
Factory locked/unlocked
8A/0A(L)
Secure Silicon
9A/1A(H)
Byte
X06
Factory locked/unlocked
8A/0A(L)
Word (Sector address) X02
00/01
Unprotected/protected
Sector Protect Verify
Byte Sector address) X04
00/01
Unprotected/protected
Table 7-9
Auto Select for MFR/Device ID/Secure Silicon/Sector Protect Read
Word
Manufacturer ID
Byte
Word
H/L
Byte
Device ID
Word
T/B
Byte
Address
X00
X00
X01/0E/0F
X02/1C/1E
X01/0E/0F
X02/1C/1E
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W29GL064C
7.2.20
Enhanced Variable IO (EVIO) Control
The Enhanced Variable IO (EVIO) control allows the host system to set the voltage levels that the
device generates and tolerates on all inputs and outputs (address, control, and DQ signals). EVIO
range is 1.65 to VCC.
For example, a EVIO of 1.65-3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving
signals to and from other 1.8 or 3 V devices on the same data bus.
7.2.21 Hardware Data Protection Options
Hardware Data Protection is the second of the two main sector protections offered by the W29GL064.
7.2.21.1
#WP/ACC Option
By setting the #WP/ACC pin to VIL, the highest or lowest sector (device specific) is protected from all
erase/program operations. If #WP/ACC is set High, the highest and Lowest sector revert back to the
previous protected/unprotected state.
Note: The max input load current can increase, if #WP/ACC pin is at VIH when the device is put into
standby mode.
7.2.21.2
VCC Write Protect
This device will not accept any write instructions when VCC is less that VWPT (VCC Write Protect
Threshold)). This prevents data from inadvertently being altered during power-up, power-down, a
temporary power loss or to the low level of VCC. If VCC is lower that VWPT, the device automatically
resets itself and will ignore write cycles until VCC is greater than VWPT. Once VCC rises above VWPT,
insure that the proper signals are on the control pins to avoid unexpected program or erase operations.
7.2.21.3
Write Pulse “Glitch” Protection
Pulses less than 5ns are viewed as glitches for control signals #CE, #WE, and #OE and will not be
considered for valid write cycles.
7.2.21.4
Power-up Write Inhibit
The device ignores the first instruction on the rising edge of #WE, if upon powering up the device,
#WE and #CE are set at VIL and #OE is set at VIH.
7.2.21.5
Logical Inhibit
A write cycle is ignored when either #CE is at VIH, #WE is at VIH, or #OE is at VIL. A valid write cycle
requires both #CE and #WE are at VIL with #OE at VIH.
7.2.22 Inherent Data Protection
The device built-in mechanism will reset to Read mode during power up to avoid accidental erasure or
programming.
7.2.22.1
Instruction Completion
Invalid instruction sets will result in the memory returning to read mode. Only upon a successful
completion of a valid instruction set will the device begin its erase or program operation..
7.2.22.2
Power-up Sequence
The device is placed in Read mode, during power-up sequence.
7.2.23 Power Supply Decoupling
To reduce noise effects, a 0.1µF capacitor is recommended to be connected between VCC and GND.
14
W29GL064C
7.3
Enhanced Sector Protect/Un-protect
This device is set from the factory in the Individual Protection mode of the Enhanced Sector Protect
scheme. The user can disable or enable the programming or erasing operation to any individual sector
or whole chip. The figure below helps describe an overview of these methods.
The device defaults to the Individual mode and all sectors are unprotected when shipped from the
factory.
The following flow chart shows the detailed algorithm of Enhanced Sector Protect:
Start
Individual Protection
Mode
(Default)
Set IPB
Lock Bit
IPB=0
IPB lock Bit locked
All IPB not changeable
IPB=1
IPB Lock bit Unlocked
IPB is Changeable
Dynamic Write Protect bit
(DPB)
Sector Array
DPB=0 Sector Protect
DPB=1 Sector Unprotect
Figure 7-1
Individual Protect bit
(IPB)
IPB=0 Sector Protect
IPB=1 Sector Unprotect
DPB 0
SA 0
IPB 0
DPB 1
SA 1
IPB 1
DPB 2
SA 2
IPB 2
.
.
.
.
.
.
.
.
.
.
.
.
DPB + n
SA + n
IPB + n
Enhanced Sector Protect/Un-protect IPB Program Algorithm
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Preliminary - Revision E
W29GL064C
7.3.1
Lock Register
User can choose Secured Silicon Sector Protection Bit for security sector protection method via setting
the Lock Register bit, DQ0. Lock Register is a 16-bit one time programmable register. Once
programmed DQ0, will be locked in that mode permanently.
Once the Instruction Set Entry instruction sequence for the Lock Register Bits is issued, all sectors
read and write functions are disabled until Lock Register Exit sequence has been executed.
The memory sectors and extended memory sector protection is configured using the Lock Register.
DQ[15:1]
Table 7-10
DQ0
Don’t Care
Lock Register Bits
Secured Silicon Sector Protection Bit
Start
Write Data AAh, Address 555h
Lock Register instruction set entry
Write Data 55h, Address2AAh
Write Data 40h, Address 555h
Write Data A0h, Address don’t care
Lock Register data program
Write Program Data, Address don’t care
Data # Polling Algorithm
Done
YES
NO
NO
Pass
DQ5=1
YES
Exit lock Register instruction
Fail
Reset instruction
Figure 7-2
Lock Register Program Algorithm
16
W29GL064C
7.3.2
7.3.2.1
Individual (Non-Volatile) Protection Mode
Individual Protection Bits (IPB)
The Individual Protection Bit (IPB) is a nonvolatile bit, one bit per sector, with endurance equal to that
of the Flash memory array. Before erasing, IPB preprogramming and verification is managed by the
device, so no monitoring is necessary.
The Individual Protection Bits are set sector by sector by the IPB program instruction. Once a IPB is
set to “0”, the linked sector is protected, blocking any program and/or erase functions on that sector.
The IPB cannot be erased individually, but executing the “All IPB Erase” instruction will erase all IPB
simultaneously. Read and write functions are disabled when IPB programming is going on for all
sectors until this mode exits.
In case one of the protected sectors need to be unprotected, first, the IPB Lock Bit must be set to “1”
by performing one of the following: power-cycle the device or perform a hardware reset. Second, an
“All IPB Erase instruction needs to be performed. Third, Individual Protection Bits need to be set once
again to reflect the desired settings and finally, the IPB Lock Bit needs to be set once again which
locks the Individual Protection Bits and the device functions normally once again.
Executing an IPB Read instruction to the device is required to verify the programming state of the IPB
for any given sector. Refer to the IPB Program Algorithm flow chart below for details.
Note that
•
While IPB Lock Bit is set, Program and/or erase instructions will not be executed and times
out without programming and/or erasing the IPB.
•
For best protection results, it is recommended to execute the IPB Lock Bit Set instruction early
on in the boot code. Also, protect the boot code by holding WP#/ACC = VIL. Note that the IPB
and DPB bits perform the same when WP#/ACC = VHH, and when WP#/ACC =VIH.
•
While in the IPB command mode, read within that sector will bring the IPB status back for that
sector. All Read must be executed by the read mode.
•
Issuing the IPB Instruction Set Exit will reset the device to normal read mode enabling reads
and writes for the array.
7.3.2.2
Dynamic Protection Bits (DPB)
Dynamic Protection allows the software applications to easily protect sectors against unintentional
changes, although, the protection can be readily disabled when changes are needed.
All Dynamic Protection Bits (DPB) are individually linked to their associated sectors and these volatile
bits can be modified individually (set or cleared). The DPB provide protection schemes for only
unprotected sectors that have their associated IPB cleared. To change a DPB, the “DPB Instruction
Set Entry” must be executed first and then either the DPB Set (programmed to “0”) or DPB Clear
(erased to “1”) commands have to be executed. This places each sector in the protected or
unprotected state separately. To exit the DPB mode, execute the “DPB Instruction Set Exit” instruction.
Note that
•
When the parts are first shipped, the IPB are cleared (erased to “1”) and upon power up or
reset, the DPB can be set or cleared.
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W29GL064C
IPB instruction set entry
Program IPB
Read DQ[7:0] twice
NO
DQ6=Toggle?
YES
DQ5=1?
NO
Wait 500µs
YES
Read DQ[7:0] twice
NO
Read DQ[7:0] twice
DQ6=Toggle?
YES
DQ0=
‘1’ (Erase) or
‘0’ (Program)
NO
YES
Pass
Program Fail Write Reset CMD
IPB instruction set Exit
Figure 7-3
Note:
1.
7.3.2.3
IPB Program Algorithm
IPB program/erase status polling flowchart: Check DQ6 toggle, when DQ6 stop toggle, the read status is 00h/01h
(00h for program and 01h for erase, otherwise the status is “fail’ and “exit”.
Individual Protection Bit Lock Bit
The Individual Protection Bit Lock Bit (IPBLK) is a global lock bit to control all IPB states. It is a
singular volatile bit. If the IPBLK is set (“0”), all IPB are locked and all sectors are protected or
unprotected according to their individual IPB. When IPBLK=1 (cleared), all IPB are unlocked and
allowed to be set or cleared.
To clear the IPB Lock Bit, a hardware reset or a power-up cycle must be executed.
.
18
W29GL064C
Sector Protection Status
DPB
IPBLK
IPB
clear
clear
clear
clear
clear
set
clear
set
clear
Sector Status
Unprotect, DPB and IPB are changeable
Protect, DPB and IPB are changeable
Unprotect, DPB is changeable
clear
set
set
Protect, DPB is changeable
set
clear
clear
Protect, DPB and IPB are changeable
set
clear
set
Protect, DPB and IPB are changeable
set
set
clear
Protect, DPB is changeable
set
set
set
Protect, DPB is changeable
Table 7-11
Sector Protection Status Table
19
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
7.4
Security Sector Flash Memory Region
An extra memory space length of 128 words is used as the Security Sector Region which can be
factory locked or customer lockable. To enquire about the lock status of the device, the customer can
issue a Security Sector Protect Verify or Security Sector Factory Protect Verify using Automatic Select
Address 03h and DQ7.
The security sector region is unprotected when shipped from factory and the security silicon indicator
bit (DQ7) is set to "0" for a customer lockable device. The security sector region is protected when
shipped from factory and the security silicon sector indicator bit is set to "1" for a factory-locked device.
7.4.1
Factory Locked: Security Sector Programmed and Protected at factory
In a factory locked device, the Security Sector is permanently locked prior to factory shipment The
ESN occupies addresses 00000h to 00007h in word mode for all configurations since the device has a
16-byte (8-word) ESN(Electronic Serial Number) in the security region.
Security Silicon Sector
Address Range
Standard Factory
Locked
000000h-000007h
ESN
000008h-00007Fh
Inaccessible
Table 7-12
Factory Locked: Security Sector
7.4.2
Express Flash Factory Customer
Locked
Lockable
ESN or Determined by
Determined by
Customer
Customer
Determined by Customer
Customer Lockable: Security Sector Not Programmed or Protected
Important Notice; Once the security silicon sector is protected (Lock Register OTP DQ0 = “0”, Security
Sector indicator DQ7 bit=”0”), there is no way to unprotect the security silicon sector and the contents
of the memory region can no longer be programmed.
Once the security silicon is locked and verified, an Exit Security Sector Region instruction must be
executed to get back to the Read Array mode. A power cycle, or a hardware reset will also return the
device to read array mode.
This region can act as extra memory space when this security feature is not utilized. It is important to
note, the security sector region is a One Time Programmable (OTP) region. You can overwrite a
WORD, but you cannot change the state of a programmed cell.
20
W29GL064C
7.5
Instruction Definition Tables
1st Bus
Cycle
Instruction
Read Mode
Reset Mode
Automatic Select
Silicon ID
Device ID
Factory Protect
Verify
Sector Protect
Verify
Security Sector
Region
Exit Security Sector
Table 7-13
2nd Bus
Cycle
3rd Bus
Cycle
ADD DATA ADD DATA ADD DATA
WORD Add
Data
BYTE
Data
Add
4th Bus Cycle
ADD
DATA
01
5th Bus
Cycle
ADD DATA
6th Bus Cycle
ADD
DATA
WORD XXX
F0
BYTE XXX
F0
WORD 555
AA
2AA
55
555
90
X00
BYTE AAA
AA
555
55
AAA
90
X00
01
WORD 555
AA
2AA
55
555
90
X01
ID1
X0E
ID2
X0F
ID3
BYTE AAA
AA
555
55
AAA
90
X02
ID1
X1C
ID2
X1E
ID3
WORD 555
AA
2AA
55
555
90
X03
9A/1A(H)
8A/0A(L)
BYTE AAA
AA
555
55
AAA
90
X06
9A/1A(H)
8A/0A(L)
WORD 555
AA
2AA
55
555
90
(SA)X02
00/01
(SA)X04
00/01
BYTE AAA
AA
555
55
AAA
90
WORD 555
AA
2AA
55
555
88
BYTE AAA
AA
555
55
AAA
88
WORD 555
AA
2AA
55
555
90
XXX
00
BYTE AAA
AA
555
55
AAA
90
XXX
00
ID Reads, Sector Verify, and Security Sector Entry/Exit
21
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
1st Bus
Cycle
Instruction
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA
6th Bus Cycle
ADD
DATA
WORD 555
AA
2AA
55
555
A0
Add
Data
BYTE AAA
AA
555
55
AAA
A0
Add
Data
WORD 555
AA
2AA
55
SA
25
SA
N-1
WA
WD
WBL
WD
BYTE AAA
AA
555
55
SA
25
SA
N-1
WA
WD
WBL
WD
Write to Buffer Program
Abort Reset
WORD 555
AA
2AA
55
555
F0
BYTE AAA
AA
555
55
AAA
F0
Write to Buffer Program
Confirm
WORD SA
29
Program
Write to Buffer Program
Chip Erase
Sector Erase
CFI Read
Program/Erase Suspend
Program/Erase Resume
Table 7-14
BYTE
SA
29
WORD 555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
BYTE AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
WORD 555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
BYTE AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
WORD
55
98
BYTE
AA
98
WORD XXX
B0
BYTE XXX
B0
WORD XXX
30
BYTE XXX
30
Program, Write Buffer, CFI, Erase and Suspend
WA=WRITE ADDRESS, WD=WRITE DATA, SA=SECTOR ADDRESS, N-1=WORD COUNT, WBL=WRITEBUFFER LOCATION, ID1/ID2/ID3: REFER TO Table 7-2 FOR
DETAIL ID.
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD
555
AA
2AA
55
XXX
B9
BYTE
555
55
XXX
B9
Deep Power
Down
Instruction
Table 7-15
ENTER
EXIT
AAA
AA
WORD XXX
AB
BYTE
AB
XXX
Deep Power Down
22
DATA
DATA
W29GL064C
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD
555
AA
2AA
55
555
40
BYTE
AAA
AA
555
55
AAA
40
WORD XXX
A0
XXX
DATA
A0
XXX
DATA
Lock Register
Instruction
Lock Register
Instruction Set
Entry
Program
Read
DATA
BYTE
DATA
90
XXX
00
XXX
90
XXX
00
IPB Instruction Set WORD 555
Entry
BYTE AAA
AA
2AA
55
555
C0
AA
555
55
AAA
C0
WORD XXX
A0
SA
00
BYTE
XXX
A0
SA
00
WORD XXX
80
00
30
00
30
IPB Program
All IPB Erase
IPB Status Read
BYTE
XXX
80
WORD
SA
00/01
BYTE
SA
00/01
DATA
Lock Register and Global Non-Volatile
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
DATA
ADD
DATA
ADD
DATA
ADD
ADD
WORD XXX
90
XXX
00
BYTE
XXX
90
XXX
00
IPB Instruction Set WORD 555
Entry
BYTE AAA
AA
2AA
55
555
50
AA
555
55
AAA
50
WORD XXX
A0
XXX
00
A0
XXX
00
90
XXX
00
90
XXX
00
Instruction
Global NonVolatile
XXX
BYTE
Table 7-16
Global Volatile Freeze
XXX
WORD XXX
Lock Register
Instruction Exit
Global Non-Volatile
BYTE
WORD XXX
DATA
IPB Instruction Set
Exit
IPB Lock Set
IPB Lock Status
Read
BYTE
XXX
WORD XXX
00/01
BYTE
00/01
XXX
IPB Lock Instruction WORD XXX
Set Exit
BYTE XXX
Table 7-17
DATA
DATA
IPB Functions
23
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
Instruction
DPB Instruction Set
Entry
Volatile
DPB Set
DPB Clear
DPB Status READ
DPB Instruction Set
Exit
Table 7-18
Notes:
1.
2.
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
ADD
ADD
ADD
ADD
ADD
DATA
DATA
DATA
WORD
555
AA
2AA
55
555
E0
BYTE
AAA
E0
AAA
AA
555
55
WORD XXX
A0
SA
00
BYTE
XXX
A0
SA
00
WORD XXX
A0
SA
01
BYTE
XXX
A0
SA
01
WORD
SA
00/01
BYTE
SA
DATA
00/01
WORD XXX
90
XXX
00
BYTE
90
XXX
00
XXX
DATA
Volatile DPB Functions
It is not recommended to use any other code that is not in the instruction definition table which can potentially enter
the hidden mode.
For the IPB Lock and DPB Status Read "00" represents lock (protect), "01" represents unlock (unprotect).
24
W29GL064C
7.6
Common Flash Memory Interface (CFI) Mode
7.6.1
Query Instruction and Common Flash memory Interface (CFI) Mode
Through Common Flash Interface (CFI) operations it is possible to access the operating
characteristics, structure and vendor specific information, such as identifying information, memory size,
byte/word configuration, operating voltages and timing information of this device. From the Read array
mode writing CFI Read instruction 98h to the address "55h"/"AAh" (Word/Byte, respectively), the
device will gain access to the CFI Query Mode. Once in the CFI mode data can be read using the
addresses given in Table 7-19 thru 7-22.
A reset instruction must be executed to exit CFI mode and the device will return to read array mode.
CFI mode: Identification Data Values (All Values in these tables are hexadecimal)
Description
Query-unique ASII string “QRY”
Primary vendor instruction set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor instruction set and control interface ID code
Address for alternate algorithm extended query table
Table 7-19
Address
(Word Mode)
Data
Address
(Byte Mode)
10h
11h
12h
13h
14h
15h
0051h
0052h
0059h
0002h
0000h
0040h
20h
22h
24h
26h
28h
2Ah
16h
17h
18h
19h
1Ah
0000h
0000h
0000h
0000h
0000h
2Ch
2Eh
30h
32h
34h
CFI Mode: ID Data Values
25
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
CFI mode: System Interface Data Values
Description
VCC supply minimum program/erase voltage
VCC supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
n
Typical timeout per single word/byte write, 2 µs
n
Typical timeout for maximum-size buffer write, 2 µs (00h,
not support)
n
Typical timeout per individual block erase, 2 ms
n
Typical timeout for full chip erase, 2 ms (00h, not support)
n
Maximum timeout for word/byte write, 2 times typical
n
Maximum timeout for buffer write, 2 times typical
n
Maximum timeout per individual block erase, 2 times
typical
n
Maximum timeout for chip erase, 2 times typical (00h, not
support)
Table 7-20
CFI Mode: System Interface Data Values
26
Address
(Word Mode)
Data
Address
(Byte Mode)
1Bh
1Ch
1Dh
1Eh
1Fh
0027h
0036h
0000h
0000h
0003h
36h
38h
3Ah
3Ch
3Eh
20h
0004h
40h
21h
22h
23h
24h
0008h
000Eh
0003h
0005h
42h
44h
46h
48h
25h
0003h
4Ah
26h
0003h
4Ch
W29GL064C
CFI mode: Device Geometry Data Values
Description
n
Device size = 2 in number of bytes (17h=64Mb)
Flash device interface description (02=asynchronous
x8/x16)
n
Maximum number of bytes in buffer write = 2 (00h, not
support)
Number of erase regions within device
H/L = 01h:uniform
T/B = 02h:boot)
Index for Erase Bank Area 1:
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256K-bytes
T/B = 0007, 0000, 0020, 0000
H/L = 007F, 0000, 0000, 0001
Index for Erase Bank Area 2
T/B = 007E, 0000, 0000, 0001
H/L = 0000, 0000, 0000, 0000
Index for Erase Bank Area 3
Index for Erase Bank Area 4
Table 7-21
Address
(Word Mode)
Data
Address
(Byte Mode)
27h
28h
29h
2Ah
2Bh
0017h
0002h
0000h
0005h
0000h
4Eh
50h
52h
54h
56h
2Ch
00xxh
58h
2Dh
00xxh
5Ah
2Eh
2Fh
0000h
00xxh
5Ch
5Eh
30h
00xxh
60h
31h
32h
33h
34h
00xxh
0000h
0000h
00xxh
62h
64h
66h
68h
35h
36h
37h
38h
39h
3Ah
3Bh
0000h
0000h
0000h
0000h
0000h
0000h
0000h
6Ah
6Ch
6Eh
70h
72h
74h
76h
3Ch
0000h
78h
CFI Mode: Device Geometry Data Values
27
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
CFI mode: Primary Vendor-Specific Extended Query Data Values
Address
(Word Mode)
Data
Address
(Byte Mode)
Major version number, ASCII
Minor version number, ASCII
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0033h
80h
82h
84h
86h
88h
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
45h
46h
47h
48h
49h
4Ah
000Ch
0002h
0001h
0000h
0008h
0000h
8Ah
8Ch
8Eh
90h
92h
94h
Burst mode (0=not supported)
4Bh
0000h
Page mode (0=not supported, 01 = 4 word page, 02 = 8 word
4Ch
0002h
page)
Minimum ACC(acceleration) supply (0= not supported),
4Dh
0095h
[D7:D4] for volt, [D3:D0] for 100mV
Maximum ACC(acceleration) supply (0= not supported),
4Eh
00A5h
[D7:D4] for volt, [D3:D0] for 100mV
WP# Protection
02=Bottom boot sectors #WP Protect
4Fh
00xxh
03=Top boot sectors #WP Protected
04=Uniform sectors bottom #WP protect
05=Uniform sectors top #WP protect
Program Suspend (0=not supported, 1=supported)
50h
0001h
Table 7-22
CFI mode: Primary Vendor-Specific Extended Query Data Values
96h
Description
Query - Primary extended table, unique ASCII string, PRI
28
98h
9Ah
9Ch
9Eh
A0h
W29GL064C
ELECTRICAL CHARACTERISTICS(1)
8
8.1
Absolute Maximum Stress Ratings
Surrounding Temperature with Bias
-65°C to +125°C
Storage Temperature
VCC Voltage Range
EVIO Voltage Range
A9, #WP/ACC Voltage Range
Other Pins Voltage Range
Output Short Circuit Current (less than one second)
Table 8-1
Absolute Maximum Stress Ratings
8.2
-65°C to +150°C
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to +10.5V
-0.5V to VCC +0.5V
200 mA
Operating Temperature and Voltage
Industrial (I) Grade Surrounding Temperature (TA)
Full VCC Range Supply Voltage
Regulated VCC Range Supply Voltage
EVIO Range Supply Voltage
Table 8-2
Operating Temperature and Voltage
NOTE:
1.
2.
3.
4.
-40°C to +85°C
+2.7V to 3.6V
+3.0V to 3.6V
1.65V to VCC
Specification for the W29GL064C is preliminary. See preliminary designation at the end of this document.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification are not implied. Exposure to
absolute maximum rating conditions for extended period may affect reliability.
Specifications contained within the following tables are subject to change.
During voltage transitions, all pins may overshoot VSS to -2.0V and VCC to +2.0V for periods up to 20ns, see below
Figure.
20ns
20ns
20ns
Vss
Vcc +2.0V
Vss -2.0V
Vcc
20ns
Figure 8-1
20ns
Maximum Negative Overshoot Figure 8-2
29
20ns
Maximum Positive Overshoot
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
8.3
DC Characteristics
DESCRIPTION
SYMBOL
Input Leak
ILI
A9 Leak
Output Leak
ILIT
ILO
Read Current
VCC Page Read
Current
ICC1
ICC2
EVIO Non-active
Current
Write Current
ICC3
Standby Current
ICC4
Reset Current
ICC5
Sleep Mode Current
ICC6
Others
WP#/ACC
A9=10.5V
Conditions
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=1MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=5MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=10MHz,
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=10MHz
#CE=VIL, #OE=VIH,
VCC=VCCmax:f=33MHz,
IIO
#CE=VIL, #OE=VIH, VCC=VCCmax
VCC=VCCmax, EVIO=VCC, #OE=VIH,
(#CE, #RESET)=VSS ±0.3V, VIL=
(VSS+0.3V/-0.1V)
VCC=VCCmax, #RESET enabled,
other pins disabled
VCC=VCCmax, VIH=VCC ±0.3,
VIL=VSS +(0.3v/-0.1v),
#WP/ACC=VIH
VCC deep power down
IDPD
current
#CE=VIL, #OE=VIH
Accelerated Pgm
IACC1
Current, WP#/ACC,
pin(Word/Byte)
Accelerated Pgm
#CE=VIL, #OE=VIH
Current, VCC pin,
IACC2
(Word/Byte)
Input Low Voltage
VIL
Input High Voltage
VIH
Very High Voltage for
Auto Select/
VHH
Accelerated Program
Output Low Voltage
VOL
IOL=100µA
Output High Voltage
VOH
IOH=-100µA
VCC Write Protect
VWPT
Threshold
Table 8-3
DC Characteristics
Note:
1.
MIN
Sleep mode enable the lower power when address remain stable for tAA+30ns
30
-0.1
0.7xEVIO
9.5
TYP.
MAX
±2.0
±5.0
35
±1.0
Unit
µA
µA
µA
µA
6
20
mA
20
30
mA
45
55
mA
7
15
mA
15
25
mA
0.2
10
mA
20
30
mA
10
20
µA
10
20
µA
10
20
µA
1
5
µA
5
10
mA
20
30
mA
0.3xEVIO V
EVIO+0.3 V
10.5
0.45
V
V
2.5
V
0.85xEVIO
2.3
W29GL064C
8.4
Switching Test Circuits
3.3V
2.7KΩ
DEVICE UNDER
TEST
CL
Figure 8-3
6.2KΩ
Switch Test Circuit
Test Condition
Output Load
Output Load Capacitance
Rise/Fall Times
Input Pulse levels
Input timing measurement reference level (If EVIO<VCC, the reference level
is 0.5 EVIO)
Output timing measurement reference levels
Table 8-4
Test Specification
8.4.1
All Speeds
1TTL gate
30
5
0.0 - EVIO
Unit
pF
ns
V
0.5EVIO
V
0.5EVIO
V
Switching Test Waveform
EVIO
EVIO / 2
0.0V
Figure 8-4
EVIO / 2
Test Points
OUTPUT
INPUT
Switching Test Waveform
31
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
8.5
AC Characteristics
Description
EVIO=VCC
EVIO=1.65V to VCC
EVIO=VCC
Page Access Time
EVIO=1.65V to VCC
EVIO=VCC
Valid data output after #CE
low
EVIO=1.65V to VCC
EVIO=VCC
Valid data output after #OE
low
EVIO=1.65V to VCC
EVIO=VCC
Read Period Time
EVIO=1.65V to VCC
Data Output High Impedance after #OE high
Data Output High Impedance after #CE high
Output Hold Time from the earliest rising edge of
address, #CE, #OE
Write Period Time
Command write period time
Address Setup Time
Address Setup Time to #OE low during Toggle
Bit Polling
Address Hold Time
Address Hold Time from #CE or #OE High during
Toggle Bit Polling
Data Setup Time
Data Hold Time
VCC Setup Time
Chip enable Setup Time
Chip enable Hold Time
Output enable Setup Time
Read
Output enable Hold
Toggle & Data#
Time
Polling
#WE Setup Time
#WE Hold Time
#CE Pulse Width
#CE Pulse With High
#WE Pulse Width
#WE Pulse Width High
EVIO=VCC
Program/Erase active time
by RY/#BY
EVIO=1.65V to VCC
Read Recover Time before Write (#OE High to
#WE Low)
Read Recover Time before Write (#OE High to
#CE Low)
16-Word Write Buffer Program Operation
Effective Write Buffer
Word
Program Operation
Accelerated Effective Write
Per Word
Buffer Operation
Valid Data Output after
Address
32
Symbol
ALT
STD
tACC
tAA
tPACC
tPA
Min
tCE
tOE
tRC
tDF
tDF
tOH
0
tWC
tCWC
tAS
70
70
0
tASO
15
tAH
45
tAHT
0
tDS
tDH
tVCS
tCS
tCH
tOES
30
0
35
0
0
0
0
10
ns
ns
µs
ns
ns
ns
ns
ns
0
0
35
30
35
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOEH
tCP
tCPH
70
80
VCC=2.7V~3.6V
Typ Max
Units
70
ns
80
ns
25
ns
35
ns
70
ns
80
ns
25
ns
35
ns
ns
ns
20
ns
20
ns
ns
tWS
tWH
tCEPW
tCEPWH
tWP
tWPH
ns
ns
ns
ns
ns
ns
70
80
tBUSY
tGHWL
0
tGHEL
0
tWHWH1
tWHWH1
tWHWH1
ns
96
6
4.8
µs
µs
µs
W29GL064C
Symbol
ALT
STD
tWHWH1
tWHWH1
tWHWH1
tWHWH2
tSEA
tRDP
Description
Program Operation
Byte
Program Operation
Word
ACC 16-Word Program Operation
Sector Erase Operation
Sector Erase Timeout
Release from Deep Power Down mode
Table 8-5
AC Characteristics
8.5.1
Min
100
VCC=2.7V~3.6V
Typ Max
Units
6
200
µs
6
200
µs
77
µs
0.15
2
Sec
50
µs
200
µs
Instruction Write Operation
tCWC
#CE
VIH
VIL
#WE
tCS
tCH
VIH
VIL
tOES
#OE
tWPH
tWP
VIH
VIL
Addresses
VIH
VALID
VIL
ADDRESS
tAH
tAS
tDH
tDS
Data
Figure 8-5
VIH
VIL
DATA IN
Instruction Write Operation Waveform
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Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
8.5.2
Read / Reset Operation
#CE
tCE
VIH
VIL
VIH
#WE
#OE
VIL
tOEH
tDF
tOE
VIH
VIL
tOH
tAA
tRC
Addresses
Outputs
VIH
ADD Valid
VIL
VOH
HIGH Z
HIGH Z
DATA Valid
VOL
Figure 8-6
8.5.2.1
Read Timing Waveform
AC Characteristics
Description
Symbol Setup Speed Unit
#RESET Pulse Width (During Automatic Algorithm)
tRP1
#RESET Pulse Width (NOT During Automatic Algorithm)
#RESET High Time Before Read
RY/#BY Recovery Time (to #CE, #OE goes low)
RY/#BY Recovery Time (to #WE goes low)
#RESET Low (During Automatic Algorithm) to Read or Write
#RESET Low (Not During Automatic Algorithm) to Read or Write
Table 8-6
AC Characteristics #RESET and RY/#BY
tRP2
tRH
tRB1
tRB2
34
MIN
10
µs
MIN
MIN
MIN
MIN
tREADY1 MAX
tREADY2 MAX
500
200
0
50
20
500
ns
ns
ns
ns
µs
ns
W29GL064C
tRB1
≈
#CE, #OE
tRB2
≈
#WE
tREADY1
≈
RY/#BY
≈
#RESET
tRP1
Reset Timing during Automatic Algorithms
#CE, #OE
tRH
RY/#BY
#RESET
tRP2
tREADY2
Reset Timing NOT during Automatic Algorithms
Figure 8-7
#RESET Timing Waveform
35
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
8.5.3
Erase/Program Operation
≈
#CE
tCH
tWHWH2
tWP
≈
#WE
tWPH
tCS
tGHWL
≈
#OE
Last 2 Erase Command Cycles
tWC
Read Status
tAH
tAS
≈
2AAh
555h
tDS
In
Progress Complete
tDH
55h
10h
tBUSY
tRB
RY/#BY
≈
Figure 8-8
V. Add
≈
Data
Valid Address
≈
Address
Automatic Chip Erase Timing Waveform
36
W29GL064C
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 80h Address 555h
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 10h Address 555h
Data# Polling Algorithm or
Toggle Bit Algorithm
No
Data = FFh?
Yes
Auto Chip Erase Completed
Figure 8-9
Automatic Chip Erase Algorithm Flowchart
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Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
Read Status
≈
#CE
tCH
tWHWH2
tWP
≈
#WE
tCS
tWPH
tGHWL
≈
#OE
tSEA
Last 2 Erase Command Cycle
tWC
Sector
ADD 1
tAH
55h
30h
30h
tBUSY
Valid Address
V. ADD.
≈
Automatic Sector Erase Timing Waveform
38
30h
tRB
RY/#BY
Figure 8-10
Sector
ADD n
In
Progress Completed
≈
tDS tDH
≈
Data
Sector
ADD 0
2AAh
≈
Address
tAS
W29GL064C
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 80h Address 555h
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 30h Sector Address
Last
Sector to
Erase
NO
YES
Data# Polling Algorithm or Toggle Bit Algorithm
Data=FFh
NO
YES
Auto Sector Erase
Completed
Figure 8-11
Automatic Sector Erase Algorithm Flowchart
39
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
START
Write Data B0h
Toggle Bit
checking DQ6
not toggled
NO
ERASE SUSPEND
YES
Read Array or
Program
Reading or
Programming
End
NO
YES
Write Data 30h
ERASE RESUME
Continue Erase
Another
Erase
Suspend?
NO
YES
Figure 8-12
Erase Suspend/Resume Flowchart
40
W29GL064C
≈
#CE
tCH
tWHWH1
tWP
≈
#WE
tCS
tWPH
tGHWL
≈
#OE
Last 2 Read Status Cycles
Last 2 Program Command Cycles
tAS
tAH
≈
555h
Program Address
Valid Address
V. Add
≈
Address
tDS tDH
PData
≈
A0h
Data
Status
tBUSY
DOUT
tRB
RY/#BY
≈
Figure 8-13
Automatic Program Timing Waveform
(9.5V ~ 10.5V)
≈
VHH
#WP/ACC
VIL or VIH
VIL or VIH
250ns
250ns
Figure 8-14
Accelerated Program Timing Waveform
41
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
Figure 8-15
CE# Controlled Write Timing Waveform
42
W29GL064C
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data A0h Address 555h
Write Program Data/Address
Data# Polling Algorithm
or
Toggle Bit Algorithm
Next Address
Read Again Data:
Program Data?
NO
YES
NO
Last Word to be
Programmed
YES
Auto Program Completed
Figure 8-16
Automatic Programming Algorithm Flowchart
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Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
VCC
3V
VHH
A9 VIH
VIL
A0
VIH
VIL
tAA
A1
A2
ADD
#CE
tAA
tAA
tAA
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCE
#WE VIH
VIL
#OE
VIH
VIL
VOH
DQ
[15:0] VOL
Figure 8-17
tOE
tDF
tOH
tOH
DATA OUT
DATA OUT
DATA OUT
Manufacturer ID
Device ID
Cycle 1
Device ID
Cycle 2
Silicon ID Read Timing Waveform
44
tOH
tOH
DATA OUT
Device ID
Cycle 3
W29GL064C
8.5.4
Write Operation Status
≈
tCE
#CE
tCH
≈
#WE
≈
tOE
#OE
tOEH
tDF
tRC
≈
Address
VALID ADDRESS
VALID ADDRESS
≈
tAA
tOH
DQ[6-0]
Status Data
Complement
True
VALID DATA
≈
Status Data
≈
DQ7
Complement
True
VALID DATA
High Z
High Z
tBUSY
RY/#BY
≈
Figure 8-18
Data# Polling Timing Waveform (During Automatic Algorithms)
45
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
Start
Read DQ[7:0] at Valid Address (1)
DQ7=Data#?
NO
YES
DQ5=1?
YES
Read DQ[7:0] at Valid Address
DQ7=Data#?(2)
NO
YES
Fail
Figure 8-19
Notes:
1.
2.
Pass
Status Polling for Word Programming/Erase
1. For programming, valid address means program address. For erasing, valid address means erase sectors address.
2. DQ7 should be rechecked even DQ5="1" because DQ7 may change simultaneously with DQ5.
46
W29GL064C
START
Read DQ[7:0] at Last
Write Address(1)
NO
DQ7=Data#?
YES
DQ1=1?
Only for Write Buffer
Program
YES
NO
NO
DQ5=1?
YES
Read DQ[7:0] at Last
Write Address(1)
NO
DQ7=Data#?(2)
YES
Fail
Figure 8-20
Notes:
1.
2.
3.
Pass
Write Buffer
Abort
Status Polling for Write Buffer Program Flowchart
For programming, valid address means program address.
For erasing, valid address means erase sectors address.
DQ7 should be rechecked even DQ5="1" because DQ7 may change simultaneously with DQ5.
47
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
tCE
≈
#CE
tCH
≈
#WE
tOE
≈
#OE
tOEH
tAHT
tASO
≈
Address
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
≈
tAA
tDF
tOH
VALID STATUS
tBUSY
VALID STATUS
(First Read)
≈
DQ6&2
(Second Read)
VALID STATUS
(Stop Toggling)
RY/#BY
≈
Figure 8-21
Toggling Bit Timing Waveform (During Automatic Algorithms)
48
VALID STATUS
W29GL064C
START
Read DQ[7:0] Twice(1)
NO
DQ6 Toggle?
YES
NO
DQ5=1?
YES
Read DQ[7:0] Twice
NO
DQ6 Toggle?
YES
Program/Erase Fail
Write Reset CMD
Figure 8-22
Notes:
1.
2.
Program/Erase
Completed
Toggle Bit Algorithm
Read toggle bit twice to determine whether or not it is toggling.
Recheck toggle bit because it may stop toggling as DQ5 changes to "1".
8.5.5 WORD/BYTE CONFIGURATION (#BYTE)
Description
Symbol
#CE to #BYTE from L/H
#BYTE from L to Output Hiz
tELFL/tELFH
tFLQZ
Test Setup
All Speed options
Unit
MAX.
Max.
5
30
ns
ns
70
ns
#BYTE from H to Output Active
tFHQV
Min.
Table 8-7
AC Characteristics Word/Byte Configuration (#BYTE)
49
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
#CE
#OE
tELFH
#BYTE
DOUT
DQ[14:0]
DOUT
DQ[7:0]
DQ[14:0]
DQ15/A-1
VALID ADDRESS
DOUT
DQ15
tFHQV
Figure 8-23
#BYTE Timing Waveform For Read operations
≈
ADD[22:3]
VALID ADDRESS
≈
≈
1st ADD
2nd ADD
3rd ADD
tPA
tPA
≈
ADD[2:0], A-1
Word, Byte
tAA
≈
DATA[15:0]
DATA 2
DATA 1
DATA 3
≈
#CE/#OE
Figure 8-24
Page Read Timing Waveform
50
W29GL064C
8.5.6 DEEP POWER DOWN MODE
Description
#WE High to release from Deep Power Down Mode
#WE High to Deep Power Down Mode
Table 8-8
AC Characteristics for Deep Power Down
SYMBOL
TYP.
MAX
tRDP
tDP
100µs
10µs
200µs
20µs
#CE
#WE
tDP
Address
55h
Data
2AAh
AAh
tRDP
XXh
55h
XXh (Don’t Care)
B9h
B9h
Standby mode
Figure 8-25
8.5.7
Deep Power Down mode
Standby mode
Deep Power Down mode Waveform
WRITE BUFFER PROGRAM
Write CMD: DATA=29h, ADD=SA
Write CMD: DATA=AAh, ADD=555h
Write CMD: DATA=55h, ADD=2AAh
Polling Status
Write CMD: DATA=25h, ADD=SA
YES
PASS?
Write CMD: DATA=PWC, ADD=SA
NO
Write CMD: DATA=PGM DATA,
ADD=PGM ADD
Return to Read mode
FAIL?
Want to Abort?
PWC=PWC-1
YES
Write a different Sector Address
to cause Abort
NO
NO
SA
PWC
= Sector Address of the Page to be Programmed
= Program Word Count
Figure 8-26
PWC=0?
NO
YES
YES
Write Buffer Abort?
YES
NO
Write Abort Reset CMD
to return to Read mode
Write Reset CMD
to return to Read mode
Write Buffer Program Flowchart
51
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
8.6
8.6.1
Recommended Operating Conditions
At Device Power-up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at
device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VCC
VCC(min)
GND
tVCS
tVR
tCE
tF
#CE
#WE
VIL
VIH
VIL
tF
#OE
DATA
#WP/ACC
Figure 8-27
Description
tOE
tR
VIH
VIL
tAA
tR or tF
ADDRESS
tR
VIH
VIH
VALID ADDRESS
VIL
VOH
tR or tF
High Z
Valid Data
Out
VOL
VIH
VIL
AC Timing at Device Power-Up
SYMBOL
VCC Rise Time
tVR
Input Signal Rise Time
tR
Input Signal Fall Time
tF
VCC Setup Time
tVCS
Table 8-9
AC Characteristics at Device Power Up
52
MIN
MAX
UNIT
20
500,000
20
20
µs/V
µs/V
µs/V
µs
35
W29GL064C
8.7
Erase and Programming Performance
LIMITS
PARAMETER
(1)
MIN
Chip Erase Time
Sector Erase Time
Chip Programming Time
Word Programming Time
Total Write Buffer Time
UNITS
(2)
TYP
MAX
19.2
.15
24
6
96
128
2
112
28
Sec
Sec
Sec
µs
µs
ACC Total Write Buffer Time
77
Erase/Program Cycles
100,000
Table 8-10
AC Characteristics for Erase and Programming Performance
Notes:
1.
2.
3.
4.
8.8
Typical program and erase times assume the following conditions: 25°C, 3.0V VCC. Programming specifications
assume checkerboard data pattern.
Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
Exclude 00h program before erase operation.
Data Retention
PARAMETER
Data Retention
Table 8-11
Data Retention
8.9
µs
Cycles
CONDITION
MIN
55°C
20
MAX
UNIT
Years
Latch-up Characteristics
PARAMETER
MIN
MAX
Input Voltage different with GND on #WP/ACC and A9 pins
-1.0V
10.5V
-1.0V
-100mA
1.5xVCC
+100mA
Input Voltage difference with GND on all normal input pins
VCC Current
All pins included except VCC. Test condition is VCC=3.0V, one pin per test.
Table 8-12
Latch-up Characteristics
8.10 Pin Capacitance
DESCRIPTION
Control Pin Capacitance
Output Capacitance
Input Capacitance
Table 8-13
Pin Capacitance
PARAMETER
TEST SET
TYP.
MAX
UNIT
CIN2
COUT
CIN
VIN=0
VOUT=0
VIN=0
7.5
8.5
6
9
12
7.5
pF
pF
pF
53
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
9
9.1
PACKAGE DIMENSIONS
TSOP 48-pin 12x20mm
1
48
e
E
c
D
HD
θ L
A2
A
A1
L1
Symbol
A
A1
A2
D
HD
E
b
c
e
L
L1
Y
θ
Figure 9-1
b
MIN.
0.05
0.95
18.3
19.8
11.9
0.17
0.10
0.50
0
MILLIMETER
NOM.
1.00
18.4
20.0
12.0
0.22
0.50
0.60
0.80
-
MAX.
1.20
1.05
18.5
20.2
12.1
0.27
0.21
0.70
0.10
5
TSOP 48-pin 12x20mm
54
MIN.
0.002
0.037
0.720
0.780
0.468
0.007
0.004
0.020
0
INCH
NOM.
0.039
0.724
0.787
0.472
0.009
0.020
0.024
0.031
-
MAX.
0.047
0.041
0.728
0.795
0.476
0.011
0.008
0.028
0.004
5
Y
W29GL064C
9.2
TSOP 56-pin 14x20mm
D
D1
0.10 C
1
56
PIN 1
IDENTIFIER
b
E
e
29
28
BOTTOM EJECTOR PIN
CAVITY # MARK
L1
A1
c1
θ
L
0.80 REF
BASE
METAL
b1
Symbol
A
A1
A2
b
b1
c
c1
D
D1
E
L
L1
e
R
θ
Figure 9-2
R
b
WITH PLATING
c
A A2
Dimension in MM
MIN NOM MAX
1.2
0.05
0.15
0.95
1.00
1.05
0.17
0.22
0.27
0.17
0.20
0.23
0.10
0.21
0.10
0.13
0.16
20.00 BSC
18.40 BSC
14.00 BSC
0.50
0.60
0.70
0.25 BSC
0.5 BSC
0.08
0.35
0°
8°
Dimension Inch
MIN
NOM
MAX
0.047
0.002
0.006
0.037 0.039 0.041
0.007 0.009 0.011
0.007 0.008 0.009
0.004
0.008
0.004 0.005 0.006
0.787 BSC
0.724 BSC
0.551 BSC
0.020 0.024 0.028
0.010 BSC
0.020 BSC
0.003
0.008
0°
8°
TSOP 56-pin 14x20mm
55
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
9.3
Low-Profile Fine-Pitch Ball Grid Array, 64-ball 11x13mm (LFBGA64)
D1
D
0.07 C
(2X)
eD
A
H G F E D C B A
E
eE
8
7
6
5
4
3
2
1
SE
E1
Øb
TOP VIEW
PIN A1
CORNER
B
SD
0.07
(2X)
A A2
BOTTOM VIEW
// 0.25 C
A1
C
64X Øb
Ø 0.20 M C A B
Ø 0.10 M C
SYMBOL
A
A1
A2
D
E
D1
E1
n
Øb
eE
eD
SD/SE
Figure 9-3
0.15 C
SIDE VIEW
DIMENSION (MM)
MIN
NOM
MAX
1.40
0.40
0.60
13.00 BSC
11.00 BSC
7.00 BSC
7.00 BSC
64
0.5
0.6
0.7
1.00 BSC
1.00 BSC
0.50 BSC
NONE
NOTE
PROFILE
BALL HEIGHT
BODY THICKNESS
BODY SIZE
BODY SIZE
MATRIX FOOTPRINT
MATRIX FOOTPRINT
BALL COUNT
BALL DIAMETER
BALL PITCH
BALL PITCH
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
LFBGA 64-ball 11x13mm
56
PIN A1
CORNER
W29GL064C
Thin & Fine-Pitch Ball Grid Array, 6x8 mm2, ball pitch: 0.8 mm, ∅=0.4mm
(TFBGA48)
E1
e
5
4
3
2
1
// 0.20 C
A1 INDEX
A1
e
SD
D1
6
A
A1 INDEX
A
A
B
C
D
E
F
G
H
D
9.4
SE
Øb(48x PLACES)
0.15
0.08
M
M
A2
C A B
C
B
0.12 C
E
0.15 (4X)
Note: Ball land:0.45mm. Ball opening:0.35mm. PCB ball land suggest <=0.35mm
SYMBOL
A
A1
A2
b
D
D1
E
E1
SE
SD
e
Figure 9-4
DIMENSION (MM)
MIN
NOM
MAX
1.20
0.27
0.32
0.37
0.79
0.35
0.40
0.45
7.90
8.00
8.10
5.60 BSC
5.90
6.00
6.10
4.00 BSC
0.400 TYP
0.400 TYP
0.80 BSC
DIMENSION (INCH)
MIN
NOM
MAX
0.047
0.011
0.013
0.015
0.031
0.014
0.016
0.018
0.311
0.315
0.319
0.220 BSC
0.232
0.236
0.240
0.157 BSC
0.016 TYP
0.016 TYP
0.031 BSC
TFBGA 48-Ball 6x8mm
57
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
10 ORDERING INFORMATION
10.1 Ordering Part Number Definitions
W 29GL 064 C H 7 T
Winbond Standard Product
W: Winbond
Product Family
29GL: 3V
Density
064:
64Mb
Product Version
C: 90nm
Sector Type
H: EVIO=VCC=2.7~3.6V, Uniform sector, highest address sector protected
EVIO=1.65V to VCC(2.7~3.6V),Uniform sector, highest address sector protected
L: EVIO=VCC=2.7~3.6V,Uniform sector, lowest address sector protected
EVIO=1.65V to VCC(2.7~3.6V),Uniform sector, lowest address sector protected
T: Top boot sector, top two addressed sectors protected
B: Bottom boot sector, bottom two addressed sectors protected
Access Time
7: 70ns
Packages
S: TSOP-48, Industrial (-40°C~+85°C) and Green (RoHS Compliant)
T: TSOP-56, Industrial (-40°C~+85°C) and Green (RoHS Compliant)
A: TFBGA-48, Industrial (-40°C~+85°C) and Green (RoHS Compliant)
B: LFBGA-64, Industrial (-40°C~+85°C) and Green (RoHS Compliant)
Figure 10-1
Notes:
1.
2.
Ordering Part Numbering
Winbond reserves the right to make changes to its products without prior notice.
Contact Winbond Sales for Secured Sector Lock Options.
58
W29GL064C
10.2 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W29GL064C Parallel Flash Memory.
Please contact Winbond for specific availability by density and package type. Winbond Parallel
memories use a 12-digit Product Number for ordering.
PACKAGE TYPE
DENSITY
PRODUCT NUMBER
TOP SIDE MARKING
TSOP-48
64Mb
W29GL064CT7S
W29GL064CT7S
TSOP-48
64Mb
W29GL064CB7S
W29GL064CB7S
TFBGA48
64Mb
W29GL064CT7A
W29GL064CT7A
TFBGA48
64Mb
W29GL064CB7A
W29GL064CB7A
TSOP-56
64Mb
W29GL064CH7T
W29GL064CH7T
TSOP-56
64Mb
W29GL064CL7T
W29GL064CL7T
LFBGA64
64Mb
W29GL064CT7B
W29GL064CT7B
LFBGA64
64Mb
W29GL064CB7B
W29GL064CB7B
LFBGA64
64Mb
W29GL064CH7B
W29GL064CH7B
LFBGA64
64Mb
W29GL064CL7B
W29GL064CL7B
Table 10-1
Valid Part Numbers and Markings
59
Publication Release Date: October 18, 2011
Preliminary - Revision E
W29GL064C
11 HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A
09-08-2010
1
32
Preliminary
Updated Random Access Time
Updated following parameters, tAA, tPA, tCE, tRC,
tWC, tBUSY & tVCS.
Updated tGHEL description & waveform.
Removed Effective Write Buffer Program (Byte)
Updated Effective Write Buffer Program (Word)
Updated Program (Word/Byte) tWHWH1.
Updated tFHQV parameter value.
Updated tVCS value.
Added TSOP 48 Pin POD.
Updated Ordering Part Number Definitions.
Updated Valid Part Numbers
Added TFBGA48 Drawing
VHH vs. ACC PGM warning
Correct TSOP missing E parameter
Correct Parameter Category tRC & Cycling
Corrected miss labeled ball on TFBGA48 diagram
st
Section 7.4.2 1 Paragraph removed ‘erase’
rd
Section 7.4.2 3 Paragraph Add OTP statement.
tCWC added definition to Table 8.5
tWHWH1 & tWHWH2 moved parameter to Typ.
Sector Erase Time 2Sec Max
B
01-18-2011
C
02-16-2011
D
05-31-2011
E
10-18-2011
Table 11-1
Revision History
32 & 42
32
32
32
49
52
54
57
58
57
12
54
32 & 53
2
20
32
32 & 33
33 & 53
Preliminary Designation
The “Preliminary” designation on a Winbond datasheet indicates that the product is not full
characterized. The specifications are subject to change and are not guaranteed. Winbond or an
authorized sales representative should be consulted for current information before using this product.
Trademarks
Winbond is a trademark of Winbond Electronics Corporation. All other marks are the property of their
respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane
or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Furthermore, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to a
situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk
and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document and
the products and services described herein at any time, without notice.
60