0 XC9572XV High-performance CPLD R DS052 (v2.2) August 27, 2001 0 5 Advance Product Specification Features Power Estimation • • Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. • • • • • For a general estimate of ICC, the following equation may be used: ICC (mA) = MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. 90 70 Typical ICC (mA) • 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 100-pin TQFP (72-user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Two separate output banks - Superior pin-locking and routability with FastCONNECT II™ switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V 50 Hig h fo P er Low 30 rm a Pow nce er 10 Description The XC9572XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 4 ns. 0 50 100 150 Clock Frequency (MHz) 200 DS052_01_012501 Figure 1: Typical ICC vs. Frequency for XC9572XV © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS052 (v2.2) August 27, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R XC9572XV High-performance CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 Function Block 1 18 I/O Macrocells 1 to 18 I/O FastCONNECT II Switch Matrix I/O I/O I/O Blocks I/O I/O I/O 54 Function Block 2 18 Macrocells 1 to 18 54 Function Block 3 18 Macrocells 1 to 18 I/O 3 I/O/GCK 54 1 I/O/GTS Function Block 4 Macrocells 1 to 18 18 I/O/GSR 2 DS052_02_041200 Figure 2: XC9572XV Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 www.xilinx.com 1-800-255-7778 DS052 (v2.2) August 27, 2001 Advance Product Specification R XC9572XV High-performance CPLD Absolute Maximum Ratings Symbol Value Units Supply voltage relative to GND –0.5 to 2.7 V VCCIO Supply voltage for output drivers –0.5 to 3.6 V VIN Input voltage relative to GND(1) –0.5 to 3.6 V VTS Voltage applied to 3-state output(1) –0.5 to 3.6 V TSTG Storage temperature (ambient) –65 to +150 oC TSOL Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 oC Junction temperature +150 oC VCC TJ Description Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Min Max Units Commercial TA = 0oC to +70oC 2.37 2.62 V Industrial TA = –40oC to +85oC 2.37 2.62 Supply voltage for output drivers for 3.3V operation 3.13 3.46 V Supply voltage for output drivers for 2.5V operation 2.37 2.62 V Supply voltage for output drivers for 1.8V operation 1.71 1.89 V Supply voltage for internal logic and input buffers VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 1.7 3.6 V VO Output voltage 0 VCCIO V Quality and Reliability Characteristics Symbol Parameter Min Max Units 20 - Years TDR Data retention NPE Program/Erase cycles (endurance) 10,000 - Cycles VESD Electrostatic Discharge (ESD) 2,000 - Volts DS052 (v2.2) August 27, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 3 R XC9572XV High-performance CPLD DC Characteristics (Over Recommended Operating Conditions) Symbol VOH Parameter Test Conditions Min Max Units Output high voltage for 3.3V outputs IOH = –4.0 mA 2.4 - V Output high voltage for 2.5V outputs IOH = –1.0 mA 2.0 - V Output high voltage for 1.8V outputs IOH = –100 µA - V Output low voltage for 3.3V outputs IOL = 8.0 mA 90% VCCIO - 0.4 V Output low voltage for 2.5V outputs IOL = 1.0 mA - 0.4 V Output low voltage for 1.8V outputs IOL = 100 µA - 0.4 V IIL Input leakage low current VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V - 10 µA IIH Input leakagehigh current VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V - 10 µA CIN I/O capacitance VIN = GND f = 1.0 MHz - 10 pF ICC Operating Supply Current (low power mode, active) VI = GND, No load f = 1.0 MHz VOL 14 mA AC Characteristics XC9572XV-4 Symbol Parameter XC9572XV-5 XC9572XV-7 Min Max Min Max Min Max Units - 4.0 - 5.0 - 7.5 ns 2.8 - 3.5 - 4.8 - ns TPD I/O to output valid TSU I/O setup time before GCK TH I/O hold time after GCK 0 - 0 - 0 - ns GCK to output valid - 2.8 - 3.5 - 4.5 ns Multiple FB internal operating frequency - 250.0 - 222.2 - 125.0 MHz TCO fSYSTEM TPSU I/O setup time before p-term clock input 0.8 - 1.0 - 1.6 - ns TPH I/O hold time after p-term clock input 2.0 - 2.5 - 3.2 - ns P-term clock output valid - 4.8 - 6.0 - 7.7 ns TOE GTS to output valid - 3.2 - 4.0 - 5.0 ns TOD GTS to output disable - 3.2 - 4.0 - 5.0 ns TPOE Product term OE to output enabled - 5.6 - 7.0 - 9.5 ns TPOD Product term OE to output disabled - 5.6 - 7.0 - 9.5 ns TAO GSR to output valid - 7.9 - 10.0 - 12.0 ns TPAO P-term S/R to output valid - 8.5 - 10.7 - 12.6 ns TWLH GCK pulse width (High or Low) 2.0 - 2.2 - 4.0 - ns TPLH P-term clock pulse width (High or Low) 5.0 - 5.0 - 6.5 - ns TPCO Advance Information Preliminary Information Notes: 1. Please contact Xilinx for up-to-date information on advance specifications. 4 www.xilinx.com 1-800-255-7778 DS052 (v2.2) August 27, 2001 Advance Product Specification R XC9572XV High-performance CPLD VTEST R1 Output Type Device Output R2 CL VCCIO VTEST R1 R2 CL 3.3V 3.3V 320Ω 360Ω 35 pF 2.5V 2.5V 250Ω 660Ω 35 pF 1.8V 1.8V 10KΩ 14KΩ 35 pF DS051_03_0601000 Figure 3: AC Load Circuit Internal Timing Parameters XC9572XV-4 Symbol Parameter XC9572XV-5 XC9572XV-7 Min Max Min Max Min Max Units Buffer Delays TIN Input buffer delay - 1.6 - 2.0 - 2.3 ns TGCK GCK buffer delay - 1.0 - 1.2 - 1.5 ns TGSR GSR buffer delay - 1.6 - 2.0 - 3.1 ns TGTS GTS buffer delay - 3.2 - 4.0 - 5.0 ns TOUT Output buffer delay - 1.6 - 2.1 - 2.5 ns TEN Output buffer enable/disable delay - 0 - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 1.4 - 1.7 - 2.4 ns TPTSR Product term set/reset delay - 0.6 - 0.7 - 1.4 ns TPTTS Product term 3-state delay - 4.0 - 5.0 - 7.2 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay - 0.2 - 0.2 - 1.3 ns TSUI Register setup time 1.6 - 2.0 - 2.6 - ns THI Register hold time 1.2 - 1.5 - 2.2 - ns TECSU Register clock enable setup time 1.6 - 2.0 - 2.6 - ns TECHO Register clock enable hold time 1.2 - 1.5 - 2.2 - ns TCOI Register clock to output valid time - 0.2 - 0.2 - 0.5 ns TAOI Register async. S/R to output delay - 4.7 - 5.9 - 6.4 ns TRAI Register async. S/R recover before clock TLOGI Internal logic delay - 0.6 - 0.7 - 1.4 ns TLOGILP Internal low power logic delay - 5.6 - 5.7 - 6.4 ns - 1.6 - 1.6 - 3.5 ns 4.0 5.0 7.5 ns Feedback Delays TF FastCONNECT II™ feedback delay Time Adders TPTA Incremental product term allocator delay - 0.6 - 0.7 - 0.8 ns TPTA2 Adjacent macrocell p-term allocator delay - 0.2 - 0.3 - 0.3 ns TSLEW Slew-rate limited delay - 3.0 - 3.0 - 4.0 ns Advance Information Preliminary Information Notes: 1. Please contact Xilinx for up-to-date information on advance specifications. DS052 (v2.2) August 27, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R XC9572XV High-performance CPLD XC9572XV I/O Pins Function MacroBlock cell PC44 VQ44 CS48 TQ100 BScan Order Function MacroBScan Block cell PC44 VQ44 CS48 TQ100 Order 1 1 - - - 16 213 3 1 - - - 41 105 1 2 1 39 D7 13 210 3 2 11 5 B5 32 102 1 3 - - D4 18 207 3 3 - - C4 49 99 1 4 - - - 20 204 3 4 - - - 50 96 1 5 2 40 D6 14 201 3 5 12 6 A4 35 93 1 6 3 41 C7 15 198 3 6 - - - 53 90 1 7 - - - 25 195 3 7 - - - 54 87 1 8 4 42 C6 17 192 3 8 13 7 B4 37 84 1 9 5(1) 43(1) B7(1) 22(1) 189 3 9 14 8 A3 42 81 1 10 - - - 28 186 3 10 - - D3 60 78 1 11 6(1) 44(1) B6(1) 23(1) 183 3 11 18 12 B2 52 75 1 12 - - - 33 180 3 12 - - - 61 72 1 13 - - - 36 177 3 13 - - - 63 69 1 14 7(1) 1(1) A7(1) 27(1) 174 3 14 19 13 B1 55 66 1 15 8 2 A6 29 171 3 15 20 14 C2 56 63 1 16 - - - 39 168 3 16 24 18 D2 64 60 1 17 9 3 C5 30 165 3 17 22 16 C3 58 57 1 18 - - - 40 162 3 18 - - - 59 54 2 1 - - - 87 159 4 1 - - - 65 51 2 2 35 29 F4 94 156 4 2 25 19 E1 67 48 2 3 - - - 91 153 4 3 - - - 71 45 2 4 - - - 93 150 4 4 - - - 72 42 2 5 36 30 G5 95 147 4 5 26 20 E2 68 39 2 6 37 31 F5 96 144 4 6 - - E4 76 36 2 7 - - - 3(2) 141 4 7 - - - 77 33 2 8 38 32 G6 97 138 4 8 27 21 F1 70 30 2 9 39(1) 33(1) G7(1) 99(1) 135 4 9 - - - 66 27 2 10 - - - 1 132 4 10 - - - 81 24 2 11 40(1) 34(1) F6(1) 4(1) 129 4 11 28 22 G1 74 21 2 12 - - - 6 126 4 12 - - - 82 18 2 13 - - - 8 123 4 13 - - - 85 15 2 14 42(3) 36(3) E6(3) 9(3) 120 4 14 29 23 F2 78 12 2 15 43 37 E7 11 117 4 15 33 27 E3 89 9 2 16 - - - 10 114 4 16 - - - 86 6 2 17 44 38 E5 12 111 4 17 34 28 G4 90 3 2 18 - - - 92 108 4 18 - - - 79 0 Notes: 1. Global control pin. 2. GTS1 for TQ100 3. GTS1 for PC44, CS48, VQ44 6 www.xilinx.com 1-800-255-7778 DS052 (v2.2) August 27, 2001 Advance Product Specification R XC9572XV High-performance CPLD XC9572XV Global, JTAG and Power Pins Pin Type PC44 VQ44 CS48 TQ100 I/O/GCK1 5 43 B7 22 I/O/GCK2 6 44 B6 23 I/O/GCK3 7 1 A7 27 I/O/GTS1 42 36 E6 3 I/O/GTS2 40 34 F6 4 I/O/GSR 39 33 G7 99 TCK 17 11 A1 48 TDI 15 9 B3 45 TDO 30 24 G2 83 TMS 16 10 A2 47 VCCINT 2.5V 21, 41 15, 35 C1, F7 5, 57, 98 VCCIO 1.8/2.5V/3.3V 32 26 G3 26, 38, 51, 88 GND 10, 23, 31 4, 17, 25 A5, D1, F3 21, 31, 44, 62, 69, 75, 84, 100 No Connects - - - 2, 7, 19, 24, 34, 43, 46, 73, 80 DS052 (v2.2) August 27, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 7 R XC9572XV High-performance CPLD Ordering Information Example: XC9572XV -7 TQ 100 C Device Type Temperature Range Number of Pins Speed Grade Package Type Device Ordering Options Speed Package Temperature -7 7.5 ns pin-to-pin delay PC44 44-pin Plastic Lead Chip Carrier (PLCC) C = Commercial TA = 0°C to +70°C -5 5 ns pin-to-pin delay VQ44 44-pin Very Thin Quad Flat Pack (VQFP) I = Industrial TA = –40°C to +85°C -4 4 ns pin-to-pin delay CS48 48-ball Chip Scale Package (CSP) TQ100 100-pin Thin Quad Flat Pack (TQFP) Component Availability Pins 44 44 48 100 Type Plastic PLCC Plastic VQFP Plastic CSP Plastic TQFP Code PC44 VQ44 CS48 TQ100 -7 C, I C, I C, I C, I -5 C C C C -4 (C) (C) - (C) XC9572XV Notes: 1. C = Commercial (TA = 0oC to +70oC); I = Industrial (TA = –40oC to +85oC). 2. ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information. Revision History 8 Date Revision No. Description 02/01/00 1.1 Initial Xilinx release. Advance information specification. 01/29/01 2.0 Added -4 performance specification and VQ44 pagkage. Deleted VQ64 package. Updated ICC vs. Frequency Figure 1. 05/15/01 2.1 Updated ICC formula, Recommended Operation Conditions, -4 and -5 AC Characteristics and Internal Timing Parameters 08/27/01 2.2 Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL - added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -5 TAOI from 6.5 to 5.9. www.xilinx.com 1-800-255-7778 DS052 (v2.2) August 27, 2001 Advance Product Specification