0 XC95288 In-System Programmable CPLD September 15, 1999 (Version 4.0) 0 5* Product Specification Features Power Management • • 10 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 352-pin BGA and 208-pin HQFP packages Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. • • • • • • • • • • Description The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen 36V18 Function Blocks, providing 6,400 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview. ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95288 device. 900 ce (700) orman Typical ICC (mA) • • Operating current for each design can be approximated for specific operating conditions using the following equation: 600 erf High P (500) (500) er w Pow Lo 300 0 50 Clock Frequency (MHz) 100 X7131 Figure 1: Typical ICC vs. Frequency For XC95288 September 15, 1999 (Version 4.0) 1 R XC95288 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 Function Block 4 Macrocells 1 to 18 Function Block 16 Macrocells 1 to 18 X5924 Figure 2: XC95288 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly 2 September 15, 1999 (Version 4.0) R XC95288 In-System Programmable CPLD Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value Units -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 V V V °C °C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol 1 Parameter VCCINT Supply voltage for internal logic and input buffer VCCIO Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage VIL VIH VO Min Max Units 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO V V V V V V Min Max Units 20 - Years 10,000 - Cycles 5 Note: 1. Numbers in parenthesis are for industrial-temperature range versions. Endurance Characteristics Symbol Parameter tDR Data Retention NPE Program/Erase Cycles September 15, 1999 (Version 4.0) 3 R XC95288 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Test Conditions Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL Input leakage current IIH I/O high-Z leakage current CIN I/O capacitance ICC Operating Supply Current (low power mode, active) Min IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Max Units 2.4 V 2.4 V 0.5 V 0.4 V ±10.0 µA ±10.0 µA ±10.0 pF 300 (Typ) ma AC Characteristics Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95288-10 XC95288-15 XC95288-20 Min Min Max 10.0 6.0 0.0 111.1 66.7 2.0 4.0 Min 15.0 8.0 0.0 6.0 95.2 55.6 4.0 4.0 Units 20.0 10.0 83.3 50.0 4.0 6.0 12.0 11.0 11.0 14.0 14.0 5.5 Max 10.0 0.0 8.0 10.0 6.0 6.0 10.0 10.0 4.5 Max 16.0 16.0 16.0 18.0 18.0 5.5 ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. 4 September 15, 1999 (Version 4.0) R XC95288 In-System Programmable CPLD VTEST R1 Output Type Device Output R2 VCCIO VTEST R1 R2 CL 5.0 V 5.0 V 160 Ω 120 Ω 35 pF 3.3 V 3.3 V 260 Ω 360 Ω 35 pF CL X5906 Figure 3: AC Load Circuit Internal Timing Parameters Symbol Parameter Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay XC95288-10 XC95288-15 XC95288-20 Min Min Max Max Min Max Units 3.5 2.5 6.0 6.0 3.0 0.0 4.5 3.0 7.5 11.0 4.5 0.0 6.5 3.0 9.5 16.0 6.5 0.0 ns ns ns ns ns ns 3.0 2.5 3.5 2.5 3.0 5.0 2.5 3.0 5.0 ns ns ns 4.0 1.0 2.5 11.0 3.0 11.5 3.0 11.5 ns ns ns ns ns ns ns ns 9.5 3.5 11.0 3.5 13.0 5.0 ns ns 1.0 4.5 1.0 5.0 1.5 5.5 ns ns 2.5 3.5 3.0 3.5 4.5 0.5 7.0 10.0 3.5 6.5 0.5 8.0 10.0 0.5 8.0 10.0 5 Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet. September 15, 1999 (Version 4.0) 5 R XC95288 In-System Programmable CPLD XC95288 I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 28 29 – 30 31 – 32 – 33 – 34 – 35 36 – 37 – – 15 16 – 17 18 – 19 – 20 – 21 – 22 23 – 25 – – N26 P25 – P23 P24 – R26 R25 R24 R23 T26 – T25 T23 – V26 – – K23 K24 – J25 L24 – K25 L25 L26 M23 M24 – M25 M26 – N25 – BScan Notes Order 861 858 855 852 849 846 843 840 837 834 831 828 825 822 819 816 813 810 807 804 801 798 795 792 789 786 783 780 777 774 771 768 765 762 759 756 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 38 39 – 40 41 – 43 – 44 – 45 – 46 47 – 48 – – 3 4 – 5 6 – 7 – 8 – 9 – 10 12 – 14 – – U24 U23 – Y26 W25 – AA26 Y25 Y24 AA25 AB25 – AA24 Y23 – AC26 – – E23 C26 – E24 F24 – E25 D26 G24 F25 F26 – H23 G26 – H25 – BScan Notes Order 753 750 747 744 741 738 735 732 729 726 723 720 717 714 711 708 705 702 699 696 693 690 687 684 681 678 675 672 669 666 663 660 657 654 651 648 [1] [1] [1] [1] [1] [1] Notes: [1] Global control pin Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed. 6 September 15, 1999 (Version 4.0) R XC95288 In-System Programmable CPLD XC95288 I/O Pins (continued) Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Note: Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 49 50 – 51 54 – 55 – 56 – 57 – 58 60 – 61 – – 197 198 – 199 200 – 201 – 202 – 203 – 205 206 – 208 – – AA23 AB24 – AD25 AE24 – AD23 AC22 AF24 AD22 AE23 – AE22 AE21 – AF21 – – C19 D18 – A21 B20 – C20 B21 B22 C21 D20 – B24 C23 – D22 – BScan Notes Order 645 642 639 636 633 630 627 624 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 546 543 540 [1] [1] Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 62 63 – 64 66 – 67 – 69 – 70 – 71 72 – 73 – – 186 187 – 188 189 – 191 – 192 – 193 – 194 195 – 196 – – AC19 AD19 – AE20 AC18 – AD18 AE19 AD17 AE18 AF18 – AE17 AE16 – AF16 – – A15 B15 – C15 D15 – A16 B16 C16 B17 C17 – B18 A20 – B19 – BScan Notes Order 537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432 5 [1] Global control pin September 15, 1999 (Version 4.0) 7 R XC95288 In-System Programmable CPLD XC95288 I/O Pins (continued) Function Block 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 8 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 74 75 – 76 77 – 78 – 80 82 83 – 84 85 – 86 – – 170 171 – 173 174 – 175 – 178 179 180 – 182 183 – 185 – – AE14 AF14 – AE13 AC13 – AD13 AF12 AE12 AD12 AC12 – AF11 AE11 – AE9 – – C10 B9 – A9 D11 – B11 A11 C12 B12 A12 – A13 B14 – C14 – BScan Notes Order 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 Function Block 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 87 88 – 89 90 – 91 – 95 97 99 – 100 101 – 102 – – 158 159 – 160 161 – 162 – 164 165 166 – 167 168 – 169 – – AD9 AC10 – AF7 AE8 – AD8 AE7 AD7 AE5 AC7 – AE3 AD4 – AC5 – – B3 A3 – D6 C6 – B5 A4 B6 A6 D8 – B7 A7 – D9 – BScan Notes Order 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 September 15, 1999 (Version 4.0) R XC95288 In-System Programmable CPLD XC95288 I/O Pins (continued) Function Block 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 103 106 – 107 109 – 110 – 111 112 113 – 114 115 – 116 – – 144 145 – 146 147 – 148 – 149 150 151 – 152 154 – 155 – September 15, 1999 (Version 4.0) – AD3 AD2 – AC3 AD1 – AA4 AA3 AB2 AC1 AA2 – AA1 Y1 – V4 – – K3 G1 – H2 H3 – J4 F1 G2 G3 F2 – E2 D2 – F4 – BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Block 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 – 117 118 – 119 120 – 121 – 122 123 125 – 126 127 – 128 – – 131 133 – 134 135 – 136 – 137 138 139 – 140 142 – 143 – – V3 W2 – U4 U3 – V2 V1 U2 T2 R4 – R3 R2 – R1 – – P1 N2 – N4 N3 – M1 M2 M3 M4 L1 – L2 L3 – J1 – BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 5 9 R XC95288 In-System Programmable CPLD XC95288 Global, JTAG and Power Pins Pin Type HQ208 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V 44 46 55 7 9 3 5 206 98 94 176 96 11, 59, 124, 153, 204 VCCIO 3.3 V/5 V GND No Connects 10 BG352 Y24 AA24 AD23 E25 F26 E23 E24 C23 AD6 AF6 D12 AE6 J23, V24, AF23, AC15, AF15, AD11, AD5, Y3, T1, J3, G4, D5, D10, B13, D17, C22, H24 1, 26, 53, 65, 79, 92, 105, 132, A10, A17, B2, B25, D7, D13, 157, 172, 181, 184 D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 2, 13, 24, 27, 42, 52, 68, 81, 93, A1, A2, A5, A8, A14, A19, A22, 104,1 08, 129, 130, 141, 156, A25, A26, B1, B26, C7, C9, C13, 163, 177, 190, 207 C18, D24, E1, E26, H1, H26, K4, N1, N24, P3, P26, V23, W1, W4, W26, AB1, AB4, AB26, AC9, AD10, AD14, AD15, AD20, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 A18, A23, A24, B4, B8, B10, B23, C1, C2, C3, C4, C5, C8, C11, C24, C25, D1, D3, D4, D14, D16, D21, D23, D25, E3, E4, F3, F23, G25, J2, J24, J26, K2, L4, L23, P2, T3, T4, T24, U25, V25, W3, W24, Y2, AB3, AB23, AC2, AC4, AC6, AC11, AC16, AC17, AC21, AC23, AC24, AC25, AD16, AD21, AD24, AD26, AE2, AE4, AE10, AE15, AF3, AF4, AF9, AF20 September 15, 1999 (Version 4.0) R XC95288 In-System Programmable CPLD Ordering Information XC95288 -10 HQ 208 C Device Type Temperature Range Speed Number of Pins Package Type Packaging Options Speed Options HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP) BG352 352-Pin Plastic Ball Grid Array (BGA) - 20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay Temperature Options C I Commercial 0°C to +70°C Industrial –40°C to +85°C 5 Component Availability Pins Type Code XC95288 –20 –15 –10 208 Plastic HQFP HQ C(I) C(I) C 352 Plastic BGA BG C(I) C(I) C C = Commercial = 0° to +70°C I = Industrial = –40° to +85°C Revision Control Version 3.0 4.0 Date 12/4/98 9/15/99 September 15, 1999 (Version 4.0) Revision Update AC Characteristics and Internal Parameters Add -10 speed grade 11