A4984 DMOS Microstepping Driver with Translator and Overcurrent Protection Features and Benefits Description ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ ▪ The A4984 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. Step modes are selectable by MSx logic inputs. It has an output drive capacity of up to 35 V and ±2 A. The A4984 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Thin profile QFN and TSSOP packages Thermal shutdown circuitry Short-to-ground protection Shorted load protection Low current Sleep mode, < 10 μA No smoke no fire (NSNF) compliance (ET package) Packages: The ET package meets customer requirements for no smoke no fire (NSNF) designs by adding no-connect pins between critical output, sense, and supply pins. So, in the case of a pin-to-adjacent-pin short, the device does not cause smoke or fire. Additionally, the device does not cause smoke or fire when any pin is shorted to ground or left open. 32-contact QFN The translator is the key to the easy implementation of the A4984. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4984 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. 5 mm × 5 mm × 0.90 mm (ET package) During stepping operation, the chopping control in the A4984 automatically selects the current decay mode, Slow or Mixed. 24-pin TSSOP with exposed thermal pad (LP Package) Continued on the next page… Approximate size 24-contact QFN with exposed thermal pad 4 mm × 4 mm × 0.75 mm (ES package) with exposed thermal pad Typical Application Diagram VDD 0.1 μF 0.1 μF 0.22 μF VREG ROSC 0.22 μF CP1 CP2 VCP VDD VBB2 5 kΩ Microcontroller or Controller Logic SLEEP STEP VBB1 OUT1A A4984 OUT1B SENSE1 MS1 MS2 DIR OUT2A ENABLE OUT2B RESET VREF 4984-DS GND GND SENSE2 100 μF DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Description (continued) In Mixed decay mode, the device is set initially to a fast decay for a proportion of the fixed off-time, then to a slow decay for the remainder of the off-time. Mixed decay current control results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4984 is supplied in three surface mount packages: two QFN packages, the 4 mm × 4 mm, 0.75 mm nominal overall height ES package, and the 5 mm × 5 mm × 0.90 mm ET package. The LP package is a 24-pin TSSOP. All three packages have exposed pads for enhanced thermal dissipation, and are lead (Pb) free (suffix –T), with 100% matte tin plated leadframes. Selection Guide Part Number Package Packing A4984SESTR-T 24-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel A4984SETTR-T 32-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel A4984SLPTR-T 24-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage VBB 35 V Output Current IOUT ±2 A Logic Input Voltage VIN –0.3 to 5.5 V Logic Supply Voltage VDD –0.3 to 5.5 V 35 V VSENSE 0.5 V VREF 5.5 V VBBx to OUTx Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature –20 to 85 ºC TJ(max) TA Range S 150 ºC Tstg –55 to 150 ºC Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Functional Block Diagram 0.1 MF 0.22 MF VREG VDD Current Regulator ROSC CP1 CP2 Charge Pump OSC VCP 0.1 MF DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay STEP SENSE1 Gate Drive DIR RESET OCP Translator MS1 Control Logic MS2 PWM Latch Blanking Mixed Decay SLEEP DAC VBB2 RS1 OUT2A OCP ENABLE DMOS Full Bridge OUT2B SENSE2 RS2 VREF Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A4984 DMOS Microstepping Driver with Translator and Overcurrent Protection ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Min. Typ.2 Max. Units 8 0 3.0 – – – – – – – – – – – – – 320 320 – – – – – – – – 35 35 5.5 430 430 1.3 1.3 4 2 10 8 5 10 V V V mΩ mΩ V V mA mA μA mA mA μA VIN(1) VDD0.7 – – V VIN(0) – – V μA Symbol Load Supply Voltage Range VBB Logic Supply Voltage Range VDD Output On Resistance RDSON Body Diode Forward Voltage VF Motor Supply Current IBB Logic Supply Current IDD Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = –1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = –1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis Blank Time IIN(1) IIN(0) RMS1 RMS2 VHYS(IN) tBLANK Fixed Off-Time tOFF Reference Input Voltage Range Reference Input Current VREF IREF Current Trip-Level Error3 errI Crossover Dead Time Protection Overcurrent Protection Threshold4 Thermal Shutdown Temperature Thermal Shutdown Hysteresis VDD Undervoltage Lockout VDD Undervoltage Hysteresis tDT IOCPST TTSD TTSDHYS VDDUVLO VDDUVLOHYS VIN = VDD0.7 VIN = VDD0.3 MS1 pin MS2 pin As a % of VDD OSC = VDD or GND ROSC = 25 kΩ VREF = 2 V, %ITripMAX = 38.27% VREF = 2 V, %ITripMAX = 70.71% VREF = 2 V, %ITripMAX = 100.00% VDD rising –20 <1.0 VDD0.3 20 –20 <1.0 20 μA – – 5 0.7 20 23 0 –3 – – – 100 100 50 11 1 30 30 – 0 – – – 475 – – 19 1.3 40 37 4 3 ±15 ±5 ±5 800 kΩ kΩ % μs μs μs V μA % % % ns 2.1 – – 2.7 – – 165 15 2.8 90 – – – 2.9 – A °C °C V mV 1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/8) – VSENSE] / (VREF/8). 2Typical Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 THERMAL CHARACTERISTICS may require derating at maximum conditions Characteristic Symbol Test Conditions* RθJA Package Thermal Resistance Value Units ES package; estimated, on 4-layer PCB, based on JEDEC standard 37 ºC/W ET package; estimated, on 4-layer PCB, based on JEDEC standard 32 ºC/W LP package; on 4-layer PCB, based on JEDEC standard 28 ºC/W *In still air. Additional thermal information available on Allegro Web site. Maximum Power Dissipation, PD(max) 5.5 5.0 4.5 Power Dissipation, PD (W) 4.0 R QJ 3.5 A = 32 ºC 3.0 R QJ /W A = 28 R 2.5 QJ 2.0 A =3 7º C/ ºC /W W 1.5 1.0 0.5 0.0 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 tA tB STEP tC tD MSx RESET, or DIR Time Duration Symbol Typ. Unit STEP minimum, HIGH pulse width tA 1 μs STEP minimum, LOW pulse width tB 1 μs Setup time, input change to STEP tC 200 ns Hold time, input change to STEP tD 200 ns Figure 1. Logic Interface Timing Diagram Table 1. Microstep Resolution Truth Table MS1 MS2 Microstep Resolution Excitation Mode L L Full Step 2 Phase H L Half Step 1-2 Phase L H Quarter Step W1-2 Phase H H Eighth Step 2W1-2 Phase Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A4984 DMOS Microstepping Driver with Translator and Overcurrent Protection Functional Description Device Operation. The A4984 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 and RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 8 through 11), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of the MSx inputs, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. Microstep Select (MSx). The microstep resolution is set by the voltage on logic inputs MSx, as shown in table 1. The MS1 pin has a 100 kΩ pull-down resistance, and the MS2 pin has a 50 kΩ pull-down resistance. When changing the step mode the change does not take effect until the next STEP rising edge. If the step mode is changed without a translator reset, and absolute position must be maintained, it is important to change the step mode at a step position that is common to both step modes in order to avoid missing steps. When the device is powered down, or reset due to TSD or an over current event the translator is set to the home position which is by default common to all step modes. Mixed Decay Operation. The bridge operates in Mixed decay mode, at power-on and reset, and during normal running according to the ROSC configuration and the step sequence, as shown in figures 8 through 11. During Mixed decay, when the trip point is reached, the A4984 initially goes into a fast decay mode for 31.25% of the off-time, tOFF . After that, it switches to Slow decay mode for the remainder of tOFF. A timing diagram for this feature appears on the next page. Typically, mixed decay is only necessary when the current in the winding is going from a higher value to a lower value as determined by the state of the translator. For most loads automatically-selected mixed decay is convenient because it minimizes ripple when the current is rising and prevents missed steps when the current is falling. For some applications where microstepping at very low speeds is necessary, the lack of back EMF in the winding causes the current to increase in the load quickly, resulting in missed steps. This is shown in figure 2. By pulling the ROSC pin to ground, mixed decay is set to be active 100% of the time, for both rising and falling currents, and prevents missed steps as shown in figure 3. If this is not an issue, it is recommended that automatically-selected mixed decay be used, because it will produce reduced ripple currents. Refer to the Fixed Off-Time section for details. Low Current Microstepping. Intended for applications where the minimum on-time prevents the output current from regulating to the programmed current level at low current steps. To prevent this, the device can be set to operate in Mixed decay mode on both rising and falling portions of the current waveform. This feature is implemented by shorting the ROSC pin to ground. In this state, the off-time is internally set to 30 μs. ¯ ). The ¯R¯¯E¯¯S¯E¯¯T¯ input sets the translator Reset Input (¯R¯¯E¯¯S¯¯E¯¯T to a predefined Home state (shown in figures 8 through 11), and turns off all of the FET outputs. All STEP inputs are ignored until ¯¯S¯E ¯¯T ¯ input is set to high. the ¯R¯¯E Step Input (STEP). A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of the MSx inputs. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Slow Decay Mixed Decay Slow Decay Mixed Decay Slow Decay Mixed Decay Slow Decay Mixed Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. t → , 1 s/div. Figure 2. Missed steps in low-speed microstepping Mixed Decay ILOAD 500 mA/div. Step input 10 V/div. No Missed Steps t → , 1 s/div. Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded) Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Direction Input (DIR). This determines the direction of rota- Blanking. This function blanks the output of the current sense tion of the motor. Changes to this input do not take effect until the next STEP rising edge. comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (μs), is approximately Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off either the source FET (when in Slow decay mode) or the sink and source FETs (when in Mixed decay mode). The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF / ( 8 RS ) where RS is the resistance of the sense resistor (Ω) and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100) × ITripMAX (See table 2 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The off-time, tOFF, is determined by the ROSC terminal. The ROSC terminal has three settings: tBLANK ≈ 1 μs Shorted-Load and Short-to-Ground Protection. If the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the ¯¯L ¯¯E ¯¯E ¯¯P input goes device will remain disabled (latched) until the S high or VDD power is removed. A short-to-ground overcurrent event is shown in figure 4. When the two outputs are shorted together, the current path is through the sense resistor. After the blanking time (≈1 μs) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. This causes the driver to go into a fixed off-time cycle. After the fixed off-time expires the driver turns on again and the process repeats. In this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. This condition is shown in figure 5. If the driver is operating in Mixed decay mode, it is normal for the positive current to spike, due to the bridge going in the forward direction and then in the negative direction, as a result of the direction change implemented by the Mixed decay feature. This is shown in figure 6. In both instances the overcurrent circuitry is protecting the driver and prevents damage to the device. Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 μF ceramic capacitor, should be ▪ ROSC tied to VDD — off-time internally set to 30 μs, decay connected between CP1 and CP2. In addition, a 0.1 μF ceramic mode is automatic Mixed decay except when in full step where capacitor is required between VCP and VBB, to act as a reservoir decay mode is set to Slow decay for operating the high-side FET gates. ▪ ROSC tied directly to ground — off-time internally set to Capacitor values should be Class 2 dielectric ±15% maximum, 30 μs, current decay is set to Mixed decay for both increasing and decreasing currents, except in full step where decay mode or tolerance R, according to EIA (Electronic Industries Alliance) is set to Slow decay. (See Low Current Microstepping section.) specifications. ▪ ROSC through a resistor to ground — off-time is determined VREG (VREG). This internally-generated voltage is used to operby the following formula, the decay mode is automatic Mixed ate the sink-side FET outputs. The VREG pin must be decoupled decay for all step modes. with a 0.22 μF ceramic capacitor to ground. VREG is internally tOFF ≈ ROSC ⁄ 825 monitored. In the case of a fault condition, the FET outputs of the Where tOFF is in μs. A4984 are disabled. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A4984 DMOS Microstepping Driver with Translator and Overcurrent Protection Capacitor values should be Class 2 dielectric ±15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. 5 A / div. Fault latched Enable Input (¯E¯¯N¯¯A¯¯B¯¯L¯¯E¯ ). This input turns on or off all of the FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, and MSx, as well as the internal sequencing logic, all remain active, independent of the ¯E ¯¯N¯¯A¯¯B¯¯L ¯¯E ¯ input state. t→ Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4984 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. Sleep Mode ( ¯S¯¯L¯¯E¯¯E¯¯P¯ ). To minimize power consumption when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, ¯¯L ¯¯E ¯¯E ¯¯P pin puts the A4984 and charge pump. A logic low on the S into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4984 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 8 through 11. As the trip point is reached, the A4984 initially goes into a fast decay mode for 31.25% of the off-time, tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing diagram for this feature appears in figure 7. Figure 4. Short-to-ground event 5 A / div. Fixed off-time t→ Figure 5. Shorted load (OUTxA → OUTxB) in Slow decay mode 5 A / div. Fixed off-time Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed-off time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal of the load current. Fast decay portion (direction change) t→ Figure 6. Shorted load (OUTxA → OUTxB) in Mixed decay mode 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 VSTEP 100.00 70.71 See Enlargement A IOUT 0 –70.71 –100.00 Enlargement A toff IPEAK tFD tSD Slow Decay Mixed Decay IOUT Fa st De ca y t Symbol toff IPEAK Characteristic Device fixed off-time Maximum output current tSD Slow decay interval tFD Fast decay interval IOUT Device output current Figure 7. Current Decay Modes Timing Chart 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Application Layout Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4984 must be soldered directly onto the board. On the underside of the A4984 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A4984, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (C7) should be closer to the pins than the bulk capacitor (C2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components.The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. The SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. Solder A4984 Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) PCB Thermal (2 oz.) OUT2B OUT2A OUT1A OUT1B Thermal Vias GND OUT2B ENABLE OUT1A SENSE1 VBB1 VDD C1 C2 CAPACITANCE VDD SLEEP ROSC ROSC BULK GND A4984 VCP RESET C4 STEP MS2 C4 REF CP2 MS1 C6 C3 DIR GND CP1 VREG C3 GND OUT1B PAD GND C1 OUT2A VBB2 OUT2B U1 SENSE2 C7 GND C7 OUT1B R5 R4 R5 R4 OUT1A OUT2A VBB ES package configuration shown C6 C2 ROSC VDD VBB 12 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 OUT2B C3 U1 GND C6 GND C4 GND C3 OUT2A C5 R4 ROSC R5 C4 C5 OUT1A C1 BULK GND GND CAPACITANCE VDD VBB2 VREG GND ROSC SLEEP REF VDD PAD C6 SENSE2 OUT2A VDD STEP C1 C2 VCP RESET OUT1B GND ENABLE OUT2B CP2 MS1 MS2 GND ROSC GND A4984 CP1 R4 OUT1A SENSE1 VBB1 R5 OUT1B DIR C2 GND VBB VBB LP package typical application and circuit layout 13 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Pin Circuit Diagrams VDD VBB VBB 8V GND GND SENSE GND CP2 GND GND GND GND GND VBB 10 V CP1 40 V PGND VREG VCP VREG DMOS Parasitic GND 8V MSx DIR VREF ROSC SLEEP VBB OUT DMOS Parasitic 8V GND DMOS Parasitic GND GND 14 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 STEP STEP 100.00 100.00 70.71 70.71 Mixed* Slow –100.00 100.00 Phase 2 IOUT2A Direction = H (%) –100.00 100.00 70.71 Slow Mixed* Slow Slow Mixed Phase 2 IOUT2B Direction = H (%) 0.00 Mixed 0.00 –70.71 70.71 Slow Mixed Home Microstep Position –70.71 Home Microstep Position 0.00 Slow Mixed Phase 1 IOUT1A Direction = H (%) Home Microstep Position Slow Home Microstep Position Phase 1 IOUT1A Direction = H (%) Mixed Slow Slow Mixed 0.00 –70.71 –70.71 –100.00 –100.00 *With ROSC pin tied to GND DIR= H DIR= H Figure 8. Decay Mode for Full-Step Increments Figure 9. Decay Modes for Half-Step Increments STEP 100.00 92.39 70.71 Slow –38.27 –70.71 –92.39 –100.00 100.00 92.39 Slow Mixed* 70.71 Phase 2 IOUT2B Direction = H (%) Mixed Slow Mixed 0.00 Home Microstep Position Phase 1 IOUT1A Direction = H (%) Mixed* 38.27 38.27 Slow Mixed Slow Mixed Slow Mixed 0.00 –38.27 –70.71 –92.39 –100.00 *With ROSC pin tied to GND DIR= H Figure 10. Decay Modes for Quarter-Step Increments 15 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 STEP 100.00 92.39 83.15 70.71 55.56 Mixed* 38.27 19.51 Slow –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 100.00 92.39 83.15 70.71 55.56 Phase 2 IOUT2B Direction = H (%) Mixed Slow Mixed Mixed Slow 0.00 Home Microstep Position Phase 1 IOUT1A Direction = H (%) Mixed* 38.27 19.51 0.00 Mixed Slow –19.51 –38.27 –55.56 –70.71 –83.15 –92.39 –100.00 *With ROSC pin tied to GND DIR= H Figure 11. Decay Modes for Eighth-Step Increments 16 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Table 2. Step Sequencing Settings Home microstep position at Step Angle 45º; DIR = H Full Step # Half Step # 1 1/4 Step # 1 1/8 Step # 2 2 3 4 5 6 4 7 8 (%) 100.00 (%) 0.00 9.80 5.6 11.3 95.69 29.03 16.9 92.39 38.27 22.5 88.19 47.14 28.1 83.15 55.56 33.8 77.30 63.44 39.4 5 70.71 70.71 45.0 63.44 77.30 50.6 6 55.56 83.15 56.3 47.14 88.19 61.9 38.27 92.39 67.5 29.03 95.69 73.1 19.51 98.08 78.8 9.80 99.52 84.4 9 0.00 100.00 90.0 –9.80 99.52 95.6 10 –19.51 98.08 101.3 –29.03 95.69 106.9 –38.27 92.39 112.5 –47.14 88.19 118.1 –55.56 83.15 123.8 –63.44 77.30 129.4 13 –70.71 70.71 135.0 –77.30 63.44 140.6 14 –83.15 55.56 146.3 –88.19 47.14 151.9 –92.39 38.27 157.5 –95.69 29.03 163.1 –98.08 19.51 168.8 –99.52 9.80 174.4 3 7 11 12 2 [% ItripMax] 19.51 8 3 [% ItripMax] Step Angle (º) 0.0 99.52 4 1 Phase 2 Current 98.08 2 2 Phase 1 Current 15 16 Full Step # Half Step # 5 1/4 Step # 9 1/8 Step # 17 6 11 12 13 14 8 15 16 Step Angle (%) 0.00 180.0 (%) –100.00 (º) –9.80 185.6 191.3 –95.69 –29.03 196.9 –92.39 –38.27 202.5 –88.19 –47.14 208.1 –83.15 –55.56 213.8 –77.30 –63.44 219.4 21 –70.71 –70.71 225.0 –63.44 –77.30 230.6 22 –55.56 –83.15 236.3 –47.14 –88.19 241.9 –38.27 –92.39 247.5 –29.03 –95.69 253.1 –19.51 –98.08 258.8 –9.80 –99.52 264.4 25 0.00 –100.00 270.0 9.80 –99.52 275.6 26 19.51 –98.08 281.3 29.03 –95.69 286.9 38.27 –92.39 292.5 47.14 –88.19 298.1 55.56 –83.15 303.8 63.44 –77.30 309.4 29 70.71 –70.71 315.0 77.30 –63.44 320.6 30 83.15 –55.56 326.3 88.19 –47.14 331.9 92.39 –38.27 337.5 95.69 –29.03 343.1 98.08 –19.51 348.8 99.52 –9.80 354.4 19 23 27 28 4 [% ItripMax] –19.51 24 7 [% ItripMax] –99.52 20 3 Phase 2 Current –98.08 18 10 Phase 1 Current 31 32 17 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 Pin-out Diagrams 1 18 OUT1B ENABLE 2 17 DIR GND 3 16 GND PAD GND CP1 CP2 1 2 3 4 5 6 7 24 23 22 21 20 19 18 PAD VCP 9 VREG 10 MS1 11 MS2 12 RESET 13 ROSC 14 SLEEP 15 OUT1B NC VBB1 NC CP1 1 24 GND CP2 2 23 ENABLE VCP 3 22 OUT2B 21 VBB2 VREG 4 20 SENSE2 MS1 5 MS2 6 DIR GND REF 17 STEP 8 SLEEP 12 ROSC 11 13 VDD RESET 10 6 9 VCP MS2 14 STEP 8 15 REF 5 7 4 CP2 MS1 CP1 VREG OUT2B NC VBB2 NC ENABLE PAD RESET 7 ROSC 8 SLEEP 9 VDD 10 STEP 11 VDD 16 OUT2B LP Package 28 NC 27 OUT1A 26 NC 25 SENSE1 32 SENSE2 31 NC 30 OUT2A 29 NC ET Package 19 VBB1 20 SENSE1 21 OUT1A 22 OUT2A 23 SENSE2 24 VBB2 ES Package REF 12 19 OUT2A 18 OUT1A 17 SENSE1 16 VBB1 15 OUT1B 14 DIR 13 GND Terminal List Table Number Name Description ES ET* LP CP1 4 7 1 Charge pump capacitor terminal CP2 5 8 2 Charge pump capacitor terminal Logic input DIR 17 20 14 ¯E¯¯N¯¯A ¯¯B¯¯L¯¯E¯ 2 5 23 GND 3, 16 6, 19 13, 24 MS1 8 11 5 Logic input MS2 9 12 6 Logic input NC – 2, 4, 21, 23, 26, 28, 29, 31 – No connection Logic input Ground OUT1A 21 27 18 DMOS Full Bridge 1 Output A OUT1B 18 24 15 DMOS Full Bridge 1 Output B DMOS Full Bridge 2 Output A OUT2A 22 30 19 OUT2B 1 1 22 DMOS Full Bridge 2 Output B REF 15 18 12 Gm reference voltage input ¯R¯¯E¯¯S¯¯E ¯¯T ¯ 10 13 7 Logic input ROSC 11 14 8 Timing set SENSE1 20 25 17 Sense resistor terminal for Bridge 1 SENSE2 23 32 20 Sense resistor terminal for Bridge 2 ¯S¯¯L¯¯E¯¯E ¯¯P¯ 12 15 9 Logic input STEP 14 17 11 Logic input VBB1 19 22 16 Load supply VBB2 24 3 21 Load supply VCP 6 9 3 Reservoir capacitor terminal VDD 13 16 10 Logic supply VREG 7 10 4 Regulator decoupling terminal PAD – – – Exposed pad for enhanced thermal dissipation* *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. 18 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 ES Package, 24-Pin QFN with Exposed Thermal Pad 0.30 4.00 ±0.15 24 1 2 0.50 24 0.95 1 2 A 2.70 4.00 ±0.15 4.10 2.70 4.10 25X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 0.75 ±0.05 0.50 BSC C C PCB Layout Reference View For Reference Only; not for tooling use (reference JEDEC MO-220WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) 0.45 MAX B 2.70 2 1 C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 24 2.70 19 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 ET Package, 32-Contact QFN with Exposed Thermal Pad 0.30 5.00 ±0.15 32 32 1 2 0.50 1.00 1 2 A 5.00 ±0.15 3.40 5.00 1 33X D SEATING PLANE 0.08 C 0.25±0.10 0.90 ±0.10 0.50 BSC 3.40 C 5.00 C PCB Layout Reference View For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-6) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 0.50±0.10 3.40 B 2 1 32 3.40 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-33V6M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 20 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com DMOS Microstepping Driver with Translator and Overcurrent Protection A4984 LP Package, 24-Pin TSSOP with Exposed Thermal Pad 7.80 ±0.10 24 0.65 0.45 4° ±4 +0.05 0.15 –0.06 B 3.00 4.40 ±0.10 6.40 ±0.20 A 1 6.10 (1.00) 2 4.32 0.25 24X SEATING PLANE 0.10 C +0.05 0.25 –0.06 3.00 0.60 ±0.15 0.65 1.20 MAX 0.15 MAX C 1.65 SEATING PLANE GAUGE PLANE 4.32 C PCB Layout Reference View For Reference Only; not for tooling use (reference JEDEC MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Copyright ©2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 21 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com