Plerow APL1983 PLL Module Features Description · +2 dBm Output Level at 1983 MHz The plerowTM PLL synthesizer module was designed for use in wireless and wireline systems in a wide range of frequency from 50 MHz to 6 GHz. ASB’s PLL provides exceptionally low spurious and phase noise performance with fast locking time and low current consumption. All products are available in a surface-mount type package. · Channel Step Size : 25 kHz nd · 2 Harmonic : < -25 dBc · Spurious Level : < -70 dBc · Lock Time : < 10 ms · 35 mA Current Consumption Specifications Parameter Unit Min. Typical Max. Frequency Range MHz 1947 1983 2019 Output Power dBm 0 2 4 V 4.75 5.0 5.25 35 45 Website: www.asb.co.kr E-mail: [email protected] Tel: (82) 42-528-7220 Fax: (82) 42-528-7222 Supply Voltage Current Consumption Channel Step Size mA kHz 25 2 Harmonics dBc -25 -20 Spurious Level dBc -70 -60 Lock Time ms nd Reference Frequency MHz Reference Input Level dBm More Information ASB Inc., 4th Fl. Venture Town Bldg., 367-17 Goijeong-Dong, Seo-Gu, Daejon 302-716, Korea 10 10 -5 0 5 Phase Noise (C / N) @ 1 kHz @ 10 kHz dBc/Hz @ 100 kHz Output Impedance Ω Operating Temp. Range °C Package Type & Size mm -80 -70 -103 -93 -120 -110 50 -40 25 85 SMT, 19.0W×19.0L×5.8H 1) Measurement conditions are as follows: T = 25°C, VCC = 5 V, Freq. = 1983 MHz, 50 ohm system. Outline Drawing Top View Bottom View D A E F I H G C Pin Configuration Dimension (mm) CLOCK A 19.0 B 19.0 C 5.8 D 1.5 E 0.5 F 1.75 G 1.35 H 15.0 I 0.9 Tolerance: ± 0.2 1 2 3 4 9 13 15 16 Others DATA ENABLE OSC IN VCC (VCO) RF OUT VCP (PLL) LOCK DETECT Ground B Side View 1/1 www.asb.co.kr March 2004