Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Applications n Video line drivers n S-Video driver n Video switchers and routers n ADC buffer n Active filters n Cable drivers n Twisted pair driver/receiver General Description The Comlinear CLC2601 (dual), CLC3601 (triple), and CLC4601 (quad) are high-performance, current feedback amplifiers. These amplifiers provide 550MHz unity gain bandwidth, ±0.1dB gain flatness to 120MHz, and 1,500V/μs slew rate, exceeding the requirements of high-definition television (HDTV) and other multimedia applications. These Comlinear high-performance amplifiers also provide ample output current to drive multiple video loads. The Comlinear CLC2601, CLC3601, and CLC4601 are designed to operate from ±5V supplies. They consume only 5.2mA of supply current per channel. The combination of high-speed, low-power, and excellent video performance make these amplifiers well suited for use in many general purpose, highspeed applications including standard definition and high definition video. Typical Application - Driving Dual Video Loads +Vs 75Ω Cable Input 75Ω 75Ω Cable Output A 75Ω 75Ω Rf Rg 75Ω 75Ω Cable Output B 75Ω -Vs Ordering Information Package Pb-Free Operating Temperature Range Packaging Method CLC2601ISO8X SOIC-8 Yes -40°C to +85°C Reel CLC2601ISO8 SOIC-8 Yes -40°C to +85°C Rail CLC3601ISO14X SOIC-14 Yes -40°C to +85°C Reel CLC3601ISO14 SOIC-14 Yes -40°C to +85°C Rail CLC4601ISO14X SOIC-14 Yes -40°C to +85°C Reel CLC4601ISO14 SOIC-14 Yes -40°C to +85°C Rail Rev 1C Part Number Moisture sensitivity level for all parts is MSL-1. ©2008 CADEKA Microcircuits LLC Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers features n 0.1dB gain flatness to 120MHz n 0.01%/0.06˚ differential gain/ phase error n 335MHz -3dB bandwidth at G = 2 n 550MHz -3dB bandwidth at G = 1 n 1,500V/μs slew rate n 52mA output current (sufficient for driving two video loads) n 5.2mA supply current n Fully specified at ±5V supplies n CLC2601: Pb-free SOIC-8 n CLC3601, CLC4601: Pb-free SOIC-14 www.cadeka.com Data Sheet CLC2601 Pin Assignments CLC2601 Pin Configuration Pin Name 1 OUT1 Output, channel 1 OUT2 2 -IN1 Negative input, channel 1 6 -IN2 3 +IN1 Positive input, channel 1 5 +IN2 1 8 +VS -IN1 2 7 +IN1 3 -V S 4 NC 1 14 OUT2 NC 2 13 -IN2 NC 3 12 +IN2 +VS 4 11 -VS +IN1 5 10 +IN3 -IN1 6 9 -IN3 7 8 OUT3 CLC4601 Pin Configuration OUT1 Negative supply Positive input, channel 2 6 -IN2 Negative input, channel 2 7 OUT2 Output, channel 2 8 +VS Positive supply Pin No. Pin Name Description 1 NC No Connect 2 NC No Connect 3 NC No Connect 4 +VS Positive supply 5 +IN1 Positive input, channel 1 6 -IN1 Negative input, channel 1 7 OUT1 Output, channel 1 8 OUT3 Output, channel 3 9 -IN3 Negative input, channel 3 10 +IN3 Positive input, channel 3 11 -VS 12 +IN2 Positive input, channel 2 13 -IN2 Negative input, channel 2 14 OUT2 Output, channel 2 Negative supply Pin Name 1 OUT1 Output, channel 1 -IN4 2 -IN1 Negative input, channel 1 +IN4 3 +IN1 Positive input, channel 1 4 +VS Positive supply 5 +IN2 Positive input, channel 2 +IN3 6 -IN2 Negative input, channel 2 -IN3 7 OUT2 Output, channel 2 8 OUT3 Output, channel 3 9 -IN3 Negative input, channel 3 10 +IN3 Positive input, channel 3 11 -VS 12 +IN4 Positive input, channel 4 13 -IN4 Negative input, channel 4 14 OUT4 Output, channel 4 OUT4 -IN1 2 13 +IN1 3 12 +VS 4 11 -VS +IN2 5 10 -IN2 6 9 8 +IN2 Pin No. 14 7 -VS 5 CLC4601 Pin Assignments 1 OUT2 4 CLC3601 Pin Assignments CLC3601 Pin Configuration OUT1 Description Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Pin No. OUT1 OUT3 Negative supply Rev 1C ©2004-2008 CADEKA Microcircuits LLC Description www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Supply Voltage Input Voltage Range Min Max Unit 0 -Vs -0.5V +14 or ±7 +Vs +0.5V V V Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Parameter Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 8-Lead SOIC 14-Lead SOIC Min Typ -65 Max Unit 150 150 260 °C °C °C 100 88 °C/W °C/W Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air. ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM) SOIC-8 SOIC-14 2.5kV 2kV 2.5kV 2kV Recommended Operating Conditions Parameter Min Operating Temperature Range Supply Voltage Range -40 ±4 Typ Max Unit +85 ±6 °C V Rev 1C ©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Electrical Characteristics TA = 25°C, Vs = ±5V, Rf = 510Ω, RL = 100Ω to GND, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response -3dB Bandwidth G = +1, VOUT = 0.2Vpp, Rf = 1kΩ 550 MHz BWSS BWLS -3dB Bandwidth G = +2, VOUT = 0.2Vpp 335 MHz Large Signal Bandwidth G = +2, VOUT = 4Vpp 200 MHz BW0.1dBSS 0.1dB Gain Flatness G = +2, VOUT = 0.2Vpp (Rf=453Ω for CLC4601) 120 MHz BW0.1dBLS 0.1dB Gain Flatness G = +2, VOUT = 4Vpp 55 MHz Time Domain Response tR, tF Rise and Fall Time VOUT = 2V step; (10% to 90%) 1.4 ns tS Settling Time to 0.1% VOUT = 2V step 20 ns OS Overshoot VOUT = 0.2V step 1.5 % SR Slew Rate VOUT = 4V step 1500 V/µs Distortion/Noise Response HD2 2nd Harmonic Distortion 2Vpp, 1MHz -82 dBc HD3 3rd Harmonic Distortion 2Vpp, 1MHz -83 dBc THD Total Harmonic Distortion 2Vpp, 1MHz -80 dB DG Differential Gain NTSC (3.58MHz), DC-coupled, RL = 150Ω 0.01 % DP Differential Phase NTSC (3.58MHz), DC-coupled, RL = 150Ω 0.06 ° en Input Voltage Noise > 1MHz 7 nV/√Hz in+ Input Current Noise (+) > 1MHz 1.3 pA/√Hz in- Input Current Noise (-) > 1MHz 11 pA/√Hz XTALK Crosstalk Channel-to-channel 5MHz -56 dB DC Performance VIO dVIO Ibn dIbn Ibi dIbni Input Offset Voltage(1) -7.5 Average Drift 2.7 +7.5 15 Input Bias Current Non-inverting(1) -7.0 2.6 -30 7.4 Average Drift 7.0 6 Input Bias Current Inverting(1) Average Drift µA nA/°C 30 15 µA nA/°C PSRR Power Supply Rejection Ratio(1) DC 61 dB ZOL Open-Loop Transimpedance VOUT = VS / 2 420 kΩ CLC2601 Total 10.4 14 mA CLC3601 Total 20.8 28 mA CLC4601 Total 20.8 28 mA Non-inverting 8 MΩ 1 pF IS Supply Current(1) 57 mV µV/°C Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio(1) DC ±2.3 V 50 54 dB -2.6 ±2.95 Output Characteristics RO Output Resistance Output Voltage Swing IOUT Output Current ISC Short-Circuit Output Current RL = 100Ω (1) RL = 1kΩ VOUT = VS / 2 90 mΩ 2.6 V ±3.35 V 52 mA 65 mA Notes: 1. 100% tested at 25°C ©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 4 Rev 1C VOUT Closed Loop, DC Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers UGBW Data Sheet Typical Performance Characteristics TA = 25°C, Vs = ±5V, Rf = 510Ω, RL = 100Ω, G = 2; unless otherwise noted. Inverting Frequency Response 1 0 0 -1 -1 -2 Normalized Gain (dB) 1 G = 10 -3 G=5 -4 G=2 -5 -6 G=1 Rf = 1kΩ VOUT = 0.2Vpp G = -10 -2 G = -5 -3 -4 G = -2 -5 -6 -7 VOUT = 0.2Vpp G = -1 -7 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 1 2 0 1 CL = 1000pF Rs = 5Ω CL = 500pF Rs = 7Ω -2 -3 CL = 100pF Rs = 15Ω -4 CL = 50pF Rs = 20Ω -5 -6 1000 100 1000 RL = 2.5KΩ 0 -1 RL = 1KΩ -2 -3 RL = 150Ω -4 -5 CL = 10pF Rs = 40Ω VOUT = 0.2Vpp VOUT = 0.2Vpp RL = 50Ω -6 -7 0.1 1 10 100 0.1 1000 1 Frequency Response vs. VOUT Frequency Response vs. Temperature 1 0 0 -1 -1 Normalized Gain (dB) 1 -2 VOUT = 4Vpp -3 -4 VOUT = 2Vpp -5 VOUT = 1Vpp -6 10 Frequency (MHz) Frequency (MHz) Normalized Gain (dB) 100 Frequency Response vs. RL Normalized Gain (dB) Normalized Gain (dB) Frequency Response vs. CL -1 10 Frequency (MHz) -2 -3 + 25degC -4 - 40degC -5 + 85degC -6 VOUT = 2Vpp 0.1 1 10 Frequency (MHz) ©2004-2008 CADEKA Microcircuits LLC 100 1000 0.1 1 10 100 1000 Frequency (MHz) www.cadeka.com 5 Rev 1C -7 -7 Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Normalized Gain (dB) Non-Inverting Frequency Response Data Sheet Typical Performance Characteristics - Continued TA = 25°C, Vs = ±5V, Rf = 510Ω, RL = 100Ω, G = 2; unless otherwise noted. Frequency Response vs. Rf at G=1 Frequency Response vs. Rf at G=2 Rf = 510Ω Normalized Gain (dB) Normalized Gain (dB) Rf = 750Ω 1 0 -1 Rf = 1.kΩ -2 -3 Rf = 1.24kΩ G=1 Rf = 250Ω 1 2 0 Rf = 510Ω -1 -2 Rf = 1kΩ -3 -4 Rf = 1.24kΩ -5 G=2 -6 -4 0.1 1 10 100 0.1 1000 1 10 Frequency Response vs. Rf at G=5 0.1 Rf = 200Ω -1 0 Normalized Gain (dB) 0 Normalized Gain (dB) 1000 Gain Flatness 1 Rf = 510Ω -2 -3 Rf = 100Ω -4 -5 -6 -0.1 -0.2 -0.3 -0.4 G=5 -7 VOUT = 0.2Vpp -0.5 0.1 1 10 100 1000 0.1 1 Frequency (MHz) 0 -40 Phase -60 Gain -80 10k -100 1k -120 -140 100 -160 -180 -200 1M 10M Frequency (Hz) ©2004-2008 CADEKA Microcircuits LLC 100M 1G 90 80 70 60 50 40 30 20 10 0 0.001 0.001 0.01 0.1 1 10 Rev 1C 10 100k 1000 100 Transimpedance Phase (°) -20 10k 100 Input Voltage Noise Input Voltage Noise (nV/√Hz) 1M 100k 10 Frequency (MHz) Open Loop Transimpendance Gain/Phase vs. Frequency Transimpedance Gain (Ω) 100 Frequency (MHz) Frequency (MHz) 100 Frequency (MHz) www.cadeka.com Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers 2 3 6 Data Sheet Typical Performance Characteristics - Continued TA = 25°C, Vs = ±5V, Rf = 510Ω, RL = 100Ω, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL -55 -60 RL = 100Ω -70 -75 -80 RL = 1kΩ -85 -90 RL = 100Ω -60 Distortion (dBc) Distortion (dBc) -65 -65 -70 RL = 1kΩ -75 -80 -85 VOUT = 2Vpp -95 VOUT = 2Vpp -90 0 5 10 15 20 0 5 10 Frequency (MHz) 15 20 Frequency (MHz) 2nd Harmonic Distortion vs. VOUT 3rd Harmonic Distortion vs. VOUT -45 -55 -50 20MHz -60 -55 Distortion (dBc) Distortion (dBc) -65 -70 -75 5MHz -80 20MHz -60 -65 5MHz -70 -75 -80 -85 1MHz -85 1MHz -90 -90 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 0.5 0.75 1 Output Amplitude (Vpp) CMRR vs. Frequency 1.5 1.75 2 2.25 2.5 PSRR vs. Frequency 0 -20 -10 -30 -20 -40 PSRR (dB) CMRR (dB) 1.25 Output Amplitude (Vpp) -30 -40 -50 -50 -60 -70 -60 100k 1M Frequency (Hz) ©2004-2008 CADEKA Microcircuits LLC 10M 100M 10k 100k 1M 10M Rev 1C -80 10k 100M Frequency (Hz) www.cadeka.com Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers -50 -55 7 Data Sheet Typical Performance Characteristics - Continued TA = 25°C, Vs = ±5V, Rf = 510Ω, RL = 100Ω, G = 2; unless otherwise noted. Large Signal Pulse Response 2.5 0.100 2.0 0.075 1.5 0.050 1.0 0.025 0.5 Voltage (V) 0.125 0.000 -0.025 0.0 -0.5 -0.050 -1.0 -0.075 -1.5 -0.100 -2.0 -0.125 -2.5 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 Time (ns) 80 100 120 140 160 180 200 Time (ns) Crosstalk vs. Frequency Closed Loop Output Impedance vs. Frequency -30 10 -35 Output Impedance (Ω) -40 -45 Crosstalk (dB) -50 -55 -60 -65 -70 -75 -80 -85 1 VOUT = 2Vpp -90 0.1 -95 0.1 1 10 100 10k Frequency (MHz) 1M 10M 100M Frequency (Hz) Differential Gain & Phase AC Coupled Output Differential Gain & Phase DC Coupled Output 0.04 0.02 RL = 150Ω AC coupled into 220µF 0.02 0.01 DG 0 -0.01 -0.02 DP -0.03 RL = 150Ω DC coupled 0.01 Diff Gain (%) / Diff Phase (°) 0.03 Diff Gain (%) / Diff Phase (°) 100k DG 0 -0.01 -0.02 -0.03 DP -0.04 -0.05 -0.06 -0.07 -0.7 -0.5 -0.3 -0.1 0.1 Input Voltage (V) ©2004-2008 CADEKA Microcircuits LLC 0.3 0.5 0.7 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 Input Voltage (V) www.cadeka.com 8 Rev 1C -0.04 Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Voltage (V) Small Signal Pulse Response Data Sheet General Information - Current Feedback Technology Advantages of CFB Technology CFB also alleviates the traditional trade-off between closed loop gain and usable bandwidth that is seen with a VFB amplifier. With CFB, the bandwidth is primarily determined by the value of the feedback resistor, Rf. By using optimum feedback resistor values, the bandwidth of a CFB amplifier remains nearly constant with different gain configurations. When designing with CFB amplifiers always abide by these basic rules: • Use the recommended feedback resistor value • Do not use reactive (capacitors, diodes, inductors, etc.) elements in the direct feedback path • Avoid stray or parasitic capacitance across feedback resistors • Follow general high-speed amplifier layout guidelines • Ensure proper precautions have been made for driving capacitive loads VIN Ierr x1 Zo*Ierr VOUT Rf RL Rg VIN = 1+ Rf Rg + 1+ 1 Rf Eq. 1 Zo(jω) Figure 1. Non-Inverting Gain Configuration with First Order Transfer Function ©2004-2008 CADEKA Microcircuits LLC VIN Rg VOUT VIN VOUT Rf = − Rf Rg + 1+ 1 Rf RL Eq. 2 Zo(jω) Figure 2. Inverting Gain Configuration with First Order Transfer Function CFB Technology - Theory of Operation Figure 1 shows a simple representation of a current feedback amplifier that is configured in the traditional noninverting gain configuration. Instead of having two high-impedance inputs similar to a VFB amplifier, the inputs of a CFB amplifier are connected across a unity gain buffer. This buffer has a high impedance input and a low impedance output. It can source or sink current (Ierr) as needed to force the non-inverting input to track the value of Vin. The CFB architecture employs a high gain trans-impedance stage that senses Ierr and drives the output to a value of (Zo(jω) * Ierr) volts. With the application of negative feedback, the amplifier will drive the output to a voltage in a manner which tries to drive Ierr to zero. In practice, primarily due to limitations on the value of Zo(jω), Ierr remains a small but finite value. A closer look at the closed loop transfer function (Eq.1) shows the effect of the trans-impedance, Zo(jω) on the gain of the circuit. At low frequencies where Zo(jω) is very large with respect to Rf, the second term of the equation approaches unity, allowing Rf and Rg to set the gain. At higher frequencies, the value of Zo(jω) will roll off, and the effect of the secondary term will begin to dominate. The -3dB small signal parameter specifies the frequency where the value Zo(jω) equals the value of Rf causing the gain to drop by 0.707 of the value at DC. For more information regarding current feedback amplifiers, visit www.cadeka.com for detailed application notes, such as AN-3: The Ins and Outs of Current Feedback Amplifiers. www.cadeka.com 9 Rev 1C VOUT Ierr Zo*Ierr Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers The CLCx601 Family of amplifiers utilize current feedback (CFB) technology to achieve superior performance. The primary advantage of CFB technology is higher slew rate performance when compared to voltage feedback (VFB) architecture. High slew rate contributes directly to better large signal pulse response, full power bandwidth, and distortion. x1 Data Sheet Application Information Basic Operation +Vs Input Feedback Resistor Selection 6.8μF 0.1μF + Output - RL 0.1μF Rg Rf 6.8μF G = 1 + (Rf/Rg) -Vs Figure 3. Typical Non-Inverting Gain Circuit +Vs R1 Input 0.1μF + Rg 6.8μF RL 0.1μF Rf 6.8μF G = - (Rf/Rg) -Vs For optimum input offset voltage set R1 = Rf || Rg Figure 4. Typical Inverting Gain Circuit Input 6.8μF 0.1μF + Output - 6.8μF RL Rf G=1 Rf is required for CFB amplifiers Figure 5. Typical Unity Gain (G=1) Circuit ©2004-2008 CADEKA Microcircuits LLC Gain (V/V Rf (Ω) Rg (Ω) ±0.1dB BW (MHz) -3dB BW (MHz) 1 1120 - 165 520 2 510 510 120 335 5 200 50 40 230 Table 1: Recommended Rf vs. Gain In general, lowering the value of Rf from the recommended value will extend the bandwidth at the expense of additional high frequency gain peaking. This will cause increased overshoot and ringing in the pulse response characteristics. Reducing Rf too much will eventually cause oscillatory behavior. Increasing the value of Rf will lower the bandwidth. Lowering the bandwidth creates a flatter frequency response and improves 0.1dB bandwidth performance. This is important in applications such as video. Further increase in Rf will cause premature gain rolloff and adversely affect gain flatness. www.cadeka.com 10 Rev 1C 0.1μF -Vs Table 1, provides recommended Rf and associated Rg values for various gain settings. These values produce the optimum frequency response, maximum bandwidth with minimum peaking. Adjust these values to optimize performance for a specific application. The typical performance characteristics section includes plots that illustrate how the bandwidth is directly affected by the value of Rf at various gain settings. Output - +Vs One of the key design considerations when using a CFB amplifier is the selection of the feedback resistor, Rf. Rf is used in conjunction with Rg to set the gain in the traditional non-inverting and inverting circuit configurations. Refer to figures 3 and 4. As discussed in the Current Feedback Technology section, the value of the feedback resistor has a pronounced effect on the frequency response of the circuit. Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Figures 3, 4, and 5 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. CFB amplifiers can be used in unity gain configurations. Do not use the traditional voltage follower circuit, where the output is tied directly to the inverting input. With a CFB amplifier, a feedback resistor of appropriate value must be used to prevent unstable behavior. Refer to figure 5 and Table 1. Although this seems cumbersome, it does allow a degree of freedom to adjust the passband characteristics. Data Sheet Driving Capacitive Loads Input + Rs - Output CL Rf RL Rg Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx601 Family will typically recover in less than 20ns from an overdrive condition. Figure 7 shows the CLC2601 in an overdriven condition. Figure 6. Addition of RS for Driving Capacitive Loads CL (pF) RS (Ω) -3dB BW (MHz) 10 40 350 50 20 200 100 15 140 VIN = 1.5Vpp G=5 0.75 Input Voltage (V) 0.50 4 3 2 Input 0.25 1 Output 0.00 0 -0.25 -1 -0.50 -2 -0.75 -3 -1.00 Output Voltage (V) Table 2 provides the recommended RS for various capacitive loads. The recommended RS values result in <=0.5dB peaking in the frequency response. The Frequency Response vs. CL plot, on page 5, illustrates the response of the CLCx601 Family. 1.00 -4 0 20 40 60 80 100 120 140 160 180 200 Time (ns) Figure 7. Overdrive Recovery Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Parasitic Capacitance on the Inverting Input Physical connections between components create unintentional or parasitic resistive, capacitive, and inductive elements. In general, avoid adding any additional parasitic capacitance at this node. In addition, stray capacitance across the Rf resistor can induce peaking and high frequency ©2004-2008 CADEKA Microcircuits LLC Power dissipation should not be a factor when operating under the stated 1000 ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it’s intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA (ӨJA) is used along with the total die power dissipation. Rev 1C Parasitic capacitance at the inverting input can be especially troublesome with high frequency amplifiers. A parasitic capacitance on this node will be in parallel with the gain setting resistor Rg. At high frequencies, its impedance can begin to raise the system gain by making Rg appear smaller. Power Dissipation Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 6. ringing. Refer to the Layout Considerations section for additional information regarding high speed layout techniques. TJunction = TAmbient + (ӨJA × PD) Where TAmbient is the temperature of the working environment. www.cadeka.com 11 Data Sheet PD = Psupply - Pload Psupply = Vsupply × IRMS supply Vsupply = VS+ - VSPower delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, SOIC-14 2 1.5 SOIC-8 1 0.5 0 -40 -20 0 20 40 60 80 Ambient Temperature (°C) Figure 8. Maximum Power Derating Rloadeff in figure 3 would be calculated as: RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / √2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS Better thermal ratings can be achieved by maximizing PC board metallization at the package pins. However, be careful of stray capacitance on the input pins. In addition, increased airflow across the package can also help to reduce the effective ӨJA of the package. In the event the outputs are momentarily shorted to a low impedance path, internal circuitry and output metallization are set to limit and handle up to 65mA of output current. However, extended duration under these conditions may not guarantee that the maximum junction temperature (+150°C) is not exceeded. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: Assuming the load is referenced in the middle of the power rails or Vsupply/2. • Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling Figure 8 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8 and 14 lead SOIC packages. • Place the 6.8µF capacitor within 0.75 inches of the power pin • Place the 0.01µF capacitor within 0.1 inches of the power pin • Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. ©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 12 Rev 1C • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Supply power is calculated by the standard power equation. 2.5 Maximum Power Dissipation (W) In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. Data Sheet Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Products Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Evaluation Board # CEB006 CEB018 CLC2601 CLC3601, CLC4601 Evalutaion Board Schematics Evaluation board schematics and layouts are shown in Figures 9-14. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. Figure 10. CEB006 Top View 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. Figure 11. CEB006 Bottom View Figure 9. CEB006 Schematic Rev 1C ©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 13 Data Sheet Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers Figure 14. CEB018 Bottom View Figure 12. CEB018 Schematic Figure 13. CEB018 Top View Rev 1C ©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 14 Data Sheet Mechanical Dimensions SOIC-8 Package Comlinear™ CLC2601, CLC3601, CLC4601 Dual, Triple, and Quad 550MHz Amplifiers SOIC-14 Package Rev 1C For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5415 (toll free) CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e