TI TLV713P

TLV713
TLV713P
www.ti.com
SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
Capacitor-Free, 150-mA, Low-Dropout Regulator
with Foldback Current Limit for Portable Devices
Check for Samples: TLV713, TLV713P
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
The TLV713 series of low-dropout (LDO) linear
regulators are low quiescent current LDOs with
excellent line and load transient performance and are
designed for power-sensitive applications. These
devices provide a typical accuracy of 1%.
1
2
•
Stable Operation With or Without Capacitors
Foldback Overcurrent Protection
Package: SOT23-5 and X2SON
Very Low Dropout: 230 mV at 150 mA
Accuracy: 1%
Low IQ: 50 µA
Input Voltage Range: 1.4 V to 5.5 V
Available in Fixed-Output Voltages:
1.0 V to 3.3 V
High PSRR: 65 dB at 1 kHz
APPLICATIONS
•
•
•
PDAs and Battery-Powered Portable Devices
MP3 Players and Other Hand-Held Products
WLAN and Other PC Add-On Cards
DBV PACKAGE
SOT23-5
(Top View)
DQN Package
1-mm x 1-mm X2SON
(Top View)
IN
EN
4
3
The TLV713 also provides inrush current control
during device power-up and enabling. The TLV713
limits the input current to the defined current limit to
avoid large currents from flowing from the input
power source. This functionality is especially
important in battery-operated devices.
The TLV713 series is available in standard DQN and
DBV packages. The TLV713P provides an active pulldown circuit to quickly discharge output loads.
Typical Application Circuit
VIN
IN
1
GND
2
EN
1
OUT
The TLV713 series is designed to be stable without
an output capacitor. The removal of the output
capacitor allows for a very small solution size.
However, the TLV713 series is also stable with any
output capacitor if an output capacitor is used.
3
5
OUT
VOUT
TLV713xx Series
4
On
NC
2
Off
GND
IN
OUT
EN
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TLV713
TLV713P
SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1) (2)
(1)
(2)
PRODUCT
VOUT
TLV713xx(x)Pyyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475 = 4.75 V).
P is optional; devices with P have an LDO regulator with an active output discharge.
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = +25°C, unless otherwise noted. All voltages are with respect to GND.
VALUE
Voltage
Current
MIN
MAX
Input range, VIN
–0.3
6.0
V
Enable range, VEN
–0.3
VIN + 0.3
V
Output range, VOUT
–0.3
6.0
V
Maximum output, IOUT
Internally limited
Output short-circuit duration
Indefinite
Total power dissipation
Continuous, PDISS
Temperature
See Thermal Information table
Junction range, TJ
–55
+85
°C
Storage junction range, Tstg
–55
+150
°C
2000
V
500
V
Human body model (HBM)
Electrostatic discharge (ESD) ratings
(1)
UNIT
Charged device model (CDM)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
TLV713xx
TLV713xxP
DQN (X2SON)
DBV (SOT23)
4 PINS
5 PINS
θJA
Junction-to-ambient thermal resistance
255.8
213.1
θJC(top)
Junction-to-case(top) thermal resistance
159.3
110.9
θJB
Junction-to-board thermal resistance
208.2
97.4
ψJT
Junction-to-top characterization parameter
16.2
22.0
ψJB
Junction-to-board characterization parameter
208.1
78.4
θJC(bottom)
Junction-to-case(bottom) thermal resistance
148.6
n/a
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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TLV713P
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SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and COUT = 0.47 µF, unless otherwise noted.
TLV713
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage range
1.4
5.5
VOUT
Output voltage range
1.0
3.3
V
VOUT ≥ 1.8 V, TA = +25°C
–1
1
%
VOUT < 1.8 V, TA = +25°C
–20
20
mV
VOUT ≥ 1.2 V, –40°C ≤ TA ≤ +85°C
–1.5
1.5
%
VOUT < 1.2 V, –40°C ≤ TA ≤ +85°C
–50
50
mV
1
5
mV
10
30
mV
DC output accuracy
ΔVO/VIN
Line regulation
ΔVO/IOUT
Load regulation
VDO
Dropout voltage
0 mA ≤ IOUT ≤ 150 mA
VOUT = 0.98 × VOUT(NOM)
V
1.8 V ≤ VOUT < 2.1 V, IOUT = 30 mA
70
1.8 V ≤ VOUT < 2.1 V, IOUT = 150 mA
350
2.1 V ≤ VOUT < 2.5 V, IOUT = 30 mA
90
2.1 V ≤ VOUT < 2.5 V, IOUT = 150 mA
290
2.5 V ≤ VOUT < 3.0 V, IOUT = 30 mA
50
2.5 V ≤ VOUT < 3.0 V, IOUT = 150 mA
246
3.3 V ≤ VOUT < 3.6 V, IOUT = 30 mA
46
3.3 V ≤ VOUT < 3.6 V, IOUT = 150 mA
230
420
mV
1.0 V ≤ VOUT < 1.8 V, IOUT = 150 mA
600
900
mV
VOUT = 1.1 V, IOUT = 100 mA
470
600
mV
mV
575
mV
mV
481
mV
mV
445
mV
mV
IGND
Ground pin current
IOUT = 0 mA
50
75
µA
ISHDN
Shutdown current
VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 5.5 V, TA = +25°C
0.1
1
µA
PSRR
Power-supply rejection VIN = 3.3 V, VOUT = 2.8 V,
ratio
IOUT = 30 mA
f = 100 Hz
70
dB
f = 10 kHz
55
dB
f = 1 MHz
55
dB
55
µVRMS
VNOISE
Output noise voltage
BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
tSTR
Startup time (1)
COUT = 1.0 μF, IOUT = 150 mA
VHI
Enable high (enabled)
0.9
VIN
VLO
Enable low (disabled)
0
0.4
IEN
EN pin current
EN = 5.5 V
0.01
µA
RPULLDOWN
Pull-down resistor
(TLV713P only)
VIN = 4 V
120
Ω
TJ
Operating junction
temperature
ILIM
Output current limit
ISC
TSD
(1)
Short-circuit current
Thermal shutdown
100
–40
µs
+125
V
V
°C
VIN = 3.8 V, VOUT = 3.3 V
180
mA
VIN = 2.25 V, VOUT = 1.8 V
180
mA
VIN = 2.0 V, VOUT = 1.2 V
180
VOUT = 0 V
mA
40
mA
Shutdown, temperature increasing
158
°C
Reset, temperature decreasing
140
°C
Startup time is the time from EN assertion to (0.98 × VOUT(nom)).
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TLV713
TLV713P
SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
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PIN CONFIGURATIONS
DQN PACKAGE
1-mm × 1-mm X2SON
(Top View)
IN
EN
4
3
1
2
OUT
GND
DBV PACKAGE
SOT23-5
(Top View)
IN
1
GND
2
EN
3
5
OUT
4
NC
PIN DESCRIPTIONS
PIN
NAME
4
DQN
SOT23-5
DESCRIPTION
EN
3
3
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into
shutdown mode.
GND
2
2
Ground pin
IN
4
1
Input pin. A small capacitor is recommended from this pin to ground. See the Input and Output Capacitor
Requirements section in the Application Information for more details.
NC
—
4
No internal connection
OUT
1
5
Regulated output voltage pin. For best transient response, a small 1-μF ceramic capacitor is
recommended from this pin to ground. See the Input and Output Capacitor Requirements section in the
Application Information for more details.
Thermal
pad
—
—
TI recommends connecting this pin to GND for improved thermal performance.
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TLV713P
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SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
FUNCTIONAL BLOCK DIAGRAMS
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
Bandgap
Logic
TLV713
GND
Figure 1. TLV713 Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
120 W
Bandgap
Logic
TLV713P
GND
Figure 2. TLV713P Block Diagram
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TLV713
TLV713P
SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
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TYPICAL CHARACTERISTICS
At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
1.804
1.805
TJ = −40 °C
TJ = +25 °C
TJ = +85 °C
1.802
1.801
1.8
1.799
1.798
TJ = −40 °C
TJ = +25 °C
TJ = +50 °C
TJ = +85 °C
1.8
Output Voltage (V)
Output Voltage (V)
1.803
1.795
1.79
1.797
TLV71318P
1.796
2
2.5
3
3.5
4
4.5
Input Voltage (V)
5
5.5
1.785
6
0
Figure 3. 1.8-V LINE REGULATION vs
VIN AND TEMPERATURE
40
60
80
100
Output Current (mA)
120
140
160
G002
Figure 4. 1.8-V LOAD REGULATION vs
IOUT AND TEMPERATURE
500
350
TJ = −40 °C
TJ = +25 °C
TJ = +85 °C
400
TJ = −40 °C
TJ = +25 °C
TJ = +85 °C
300
Dropout Voltage (mV)
450
Dropout Voltage (mV)
20
G001
350
300
250
200
150
250
200
150
100
100
50
50
0
TLV71318P
0
0.02
0.04
0.06 0.08
0.1
Output Current (mA)
0.12
0.14
TLV71333P
0
0.16
0
Figure 5. 1.8-V DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE
45
Ground Pin Current ( µA)
Ground Pin Current ( µA)
0.06 0.08
0.1
Output Current (A)
0.12
0.14
0.16
G004
80
40
35
30
25
TJ = −40 °C
TJ = +25 °C
TJ = +85 °C
IOUT = 0 mA
2
3
4
Input Voltage (V)
5
6
60
40
20
0
TJ = −40 °C
TJ = +25 °C
TJ = +85 °C
0
20
G005
Figure 7. GROUND PIN CURRENT vs
VIN AND TEMPERATURE
6
0.04
Figure 6. 3.3-V DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE
50
20
0.02
G024
40
60
80
100
Output Current (mA)
120
140
160
G006
Figure 8. GROUND PIN CURRENT vs
IOUT AND TEMPERATURE
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SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
TYPICAL CHARACTERISTICS (continued)
At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
TJ = −40 °C
TJ = +25 °C
TJ = +85 °C
250
200
150
100
50
0
IOUT = 30 mA
IOUT = 150 mA
80
PSRR (dB)
Shut Down Current ( nA)
300
60
40
COUT = 1.0 µF
VOUT = 1.8 V
VIN = 2.8 V
VIN − VOUT = 1 V
20
2
3
4
Input Voltage (V)
5
10
6
100
1k
G007
Figure 9. SHUTDOWN CURRENT vs
VIN AND TEMPERATURE
10k
100k
Frequency (Hz)
1M
10M
G008
Figure 10. POWER-SUPPLY REJECTION RATIO vs
FREQUENCY
4
VIN
Voltage ( µV / Hz )
VOUT = 1.8 V
IOUT = 10 mA
Channel 1
1V
3
2
VOUT
Channel 3
200 mV
1
0
VIN = 3 V to 4 V
VOUT = 1.8 V
IOUT = 0 mA
CIN = COUT = 0 mF
10
100
1k
Frequency (Hz)
10k
100k
Time (200 ms/s)
G016
G009
Figure 11. OUTPUT SPECTRAL NOISE DENSITY
Figure 12. LINE TRANSIENT
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 1 mF
VIN
Channel 1
1V
Channel 3
0.5 V
Channel 1
1.9 mV
VIN = 3 V to 4 V
VOUT = 1.8 V
IOUT = 150 mA
CIN = COUT = 0 mF
VOUT
VOUT
IOUT
Channel 4
-0.4 mA
Time (200 ms/s)
Time (39 ms)
G017
Figure 13. LINE TRANSIENT
G012
Figure 14. 0-mA to 20-mA LOAD TRANSIENT
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TLV713P
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TYPICAL CHARACTERISTICS (continued)
At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
3.5
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 0 mF
3
Output Voltage (V)
Channel 3
200 mV
VOUT
IOUT
Channel 4
20 mA
2.5
2
1.5
1
0.5
TLV71333P
0
Time (200 ms/s)
0
50
100
150
200
Output Current (mA)
G015
Figure 15. 0-mA to 20-mA LOAD TRANSIENT
G010
2
Output Voltage (V)
1.75
VOUT
IOUT
Channel 4
50 mA
300
Figure 16. 3.3-V OUTPUT VOLTAGE vs OUTPUT CURRENT
(Foldback Current Limit)
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 0 mF
Channel 3
0.5 V
250
1.5
1.25
1
0.75
0.5
0.25
TLV71318P
0
Time (200 ms/s)
0
50
100
G013
Figure 17. 0-mA to 100-mA LOAD TRANSIENT
350
G011
4
IOUT = 150 mA
TPS71318P
VIN
VOUT
3
Voltage (V)
VOUT
2
IOUT
Channel 4
50 mA
1
0
Time (200 ms/s)
0
G014
Figure 19. 10-mA to 150-mA LOAD TRANSIENT
8
300
Figure 18. 1.8-V OUTPUT VOLTAGE vs OUTPUT CURRENT
(Foldback Current Limit)
VIN = 5 V, VOUT = 1.8 V
CIN = COUT = 0 mF
Channel 3
200 mV
150
200
250
Output Current (mA)
0.5
1
Time (s)
1.5
2
G020
Figure 20. VIN POWER-UP AND POWER-DOWN
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SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
TYPICAL CHARACTERISTICS (continued)
At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater),
IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted.
Channel 1
2V
Channel 1
100 mV
VIN
VIN
EN
Channel 3
1V
EN
Channel 2
1V
Channel 3
1V
Channel 2
2V
VOUT
VIN = 3 V
VOUT = 1.8 V
CIN = COUT = 0 mF
IOUT = 150 mA
TLV71318P
IOUT
Channel 4
50 mA
VOUT
Channel 4
50 mA
ILOAD
Time (50 ms/s)
VIN = 2.3 V, VOUT = 1.8 V
CIN = 1 mF, COUT = 10 mF
IOUT = 90 mA
TLV71318P, From Design
Time (100 ms)
G021
G022
Figure 21. STARTUP WITH EN
Channel 1
2V
Channel 2
2V
VIN
VIN = 3 V
VOUT = 1.8 V
CIN = COUT = 1 mF
TPS71318P
No Load
EN
VOUT
Channel 3
1V
Channel 4
100 mA
Figure 22. STARTUP WITH EN
IOUT
Time (50 ms/s)
G019
Figure 23. SHUTDOWN RESPONSE WITH ENABLE
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APPLICATION INFORMATION
The TLV713 belongs to a new family of next-generation value low-dropout (LDO) regulators. These devices
consume low quiescent current and deliver excellent line and load transient performance. These characteristics,
combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for
RF portable applications.
This family of regulators offers current limit and thermal protection. Device operating junction temperature is
–40°C to +85°C.
INPUT AND OUTPUT CAPACITOR CONSIDERATIONS
The TLV713 uses an advanced internal control loop to obtain stable operation both with and without the use of
input or output capacitors. The TLV713xx dynamic performance is improved with the use of an output capacitor.
An output capacitance of 0.1 μF or larger generally provides good dynamic response. X5R- and X7R-type
ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent
series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to
1-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. An input capacitor is recommended if the source impedance is more than
0.5 Ω. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated or if the
device is located several inches from the input power source.
BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE
Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection should be connected directly to the device GND pin. High ESR capacitors
may degrade PSRR performance.
INTERNAL CURRENT LIMIT
The TLV713 has an internal foldback current limit that helps protect the regulator during fault conditions. The
current supplied by the device is gradually throttled down while the output voltage decreases. When the output is
shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in
current limit, and is (VOUT = ILIMIT × RLOAD). The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until
thermal shutdown is triggered and the device turns off. While the device cools down, it is turned on by the
internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and
thermal shutdown. See the Thermal Information section for more details.
The TLV713 PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
SHUTDOWN
The enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. This
relatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO of
recent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device is
turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be
connected to the IN pin.
10
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POWERING THE MSP430 MICROCONTROLLER
Figure 24 shows a diagram of the TLV713 powering an MSP430 microcontroller. Several versions of the TPS713
are ideal for powering the MSP430 microcontroller. Table 1 shows potential applications of some voltage
versions.
VOUT
(1.8 V to 3.6 V)
VIN
IN
0.1 mF
MSP430
OUT
0.1 mF
EN
GND
Figure 24. TLV713 Powering a Microcontroller
Table 1. Typical MSP430 Applications
DEVICE
VOUT (Typ)
APPLICATION
TLV71319
1.9 V
VOUT, minimum > 1.8 V required by many MSP430s, allows lowest power consumption
operation
TLV71323
2.3 V
VOUT, minimum > 2.2 V required by some MSP430s FLASH operation
TLV71330
3.0 V
VOUT, minimum > 2.7 V required by some MSP430s FLASH operation
DROPOUT VOLTAGE
The TLV713 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
UNDERVOLTAGE LOCKOUT (UVLO)
The TLV713 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry
operates properly.
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THERMAL INFORMATION
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, protecting it from damage as a result of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions.
The TLV713 internal protection circuitry is designed to protect against overload conditions. It is not intended to
replace proper heatsinking. Continuously running the TLV713 into thermal shutdown degrades device reliability.
POWER DISSIPATION
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC-low and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition, plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output
current and voltage drop across the output pass element, as shown in Equation 1.
PD = (VIN – VOUT) × IOUT
12
(1)
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV713 TLV713P
TLV713
TLV713P
www.ti.com
SBVS195D – SEPTEMBER 2012 – REVISED JULY 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2013) to Revision D
Page
•
Changed document status from Mixed Status to Production Data ....................................................................................... 1
•
Deleted DPW package from document ................................................................................................................................ 1
•
Deleted DPW pin out drawing from front-page graphic ........................................................................................................ 1
•
Deleted footnote for page 1 graphic ..................................................................................................................................... 1
•
Deleted reference to DPW package from last sentence of Description section ................................................................... 1
•
Deleted footnote 3 of Ordering Information table ................................................................................................................. 2
•
Deleted DPW data from Thermal Information table .............................................................................................................. 2
•
Deleted DPW pin out drawing from Pin Configurations section ........................................................................................... 4
•
Deleted reference to DPW package from Pin Descriptions table ......................................................................................... 4
Changes from Revision B (December 2012) to Revision C
Page
•
Changed last Features bullet ................................................................................................................................................ 1
•
Added Typical Application Circuit ......................................................................................................................................... 1
•
Changed last two rows of the VDO parameter in the Electrical Characteristics table ........................................................... 3
Changes from Revision A (October 2012) to Revision B
Page
•
Changed footnote for page 1 graphic ................................................................................................................................... 1
•
Changed footnote 3 of Ordering Information table ............................................................................................................... 2
•
Added DBV data to Thermal Information table ..................................................................................................................... 2
Changes from Original (September 2012) to Revision A
Page
•
Reordered Features bullets .................................................................................................................................................. 1
•
Changed dropout range in fourth Features bullet ................................................................................................................. 1
•
Changed Package and Fixed-Output Voltage Features bullets ........................................................................................... 1
•
Updated DQN pin out drawing .............................................................................................................................................. 1
•
Added second and third paragraphs to Description section ................................................................................................. 1
•
Changed DQN header row in Thermal Information table ..................................................................................................... 2
•
Changed VOUT maximum specification in Electrical Characteristics table ............................................................................ 3
•
Combined all VDO rows together in Electrical Characteristics table ...................................................................................... 3
•
Changed VDO specifications in Electrical Characteristics table ............................................................................................ 3
•
Changed ISHDN test conditions in Electrical Characteristics table ......................................................................................... 3
•
Changed DQN pin out caption in Pin Configurations section ............................................................................................... 4
•
Changed 1.2 V to 0.9 V in description of EN pin in Pin Descriptions table .......................................................................... 4
•
Updated Figure 1 .................................................................................................................................................................. 5
•
Changed Typical Characteristics conditions ......................................................................................................................... 6
•
Added curves ........................................................................................................................................................................ 6
•
Changed junction temperature range in second paragraph of Application Information section ......................................... 10
•
Changed second paragraph of Input and Output Capacitor Considerations section ......................................................... 10
•
Deleted curve reference from Dropout Voltage section ...................................................................................................... 11
•
Deleted third paragraph from Thermal Information section ................................................................................................ 12
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: TLV713 TLV713P
13
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TLV71310PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUQI
TLV71310PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUQI
TLV71311PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUPI
TLV71311PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUPI
TLV71312PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUEI
TLV71312PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUEI
TLV71312PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AF
TLV71312PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AF
TLV71315PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUGI
TLV71315PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUGI
TLV71315PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AY
TLV71315PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AY
TLV713185PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUII
TLV713185PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUII
TLV713185PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
A1
TLV713185PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
A1
TLV71318PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUDI
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Jul-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TLV71318PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUDI
TLV71318PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AW
TLV71318PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AW
TLV71320DQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
B2
TLV71320DQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
B2
TLV71325PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUJI
TLV71325PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUJI
TLV71325PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AZ
TLV71325PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AZ
TLV713285PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VULI
TLV713285PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VULI
TLV713285PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
A2
TLV713285PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
A2
TLV71328PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUKI
TLV71328PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUKI
TLV71328PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AK
TLV71328PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AK
TLV71330PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUMI
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
18-Jul-2013
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TLV71330PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUMI
TLV71330PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AL
TLV71330PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AL
TLV71333PDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUFI
TLV71333PDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
VUFI
TLV71333PDQNR
ACTIVE
X2SON
DQN
4
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AH
TLV71333PDQNT
ACTIVE
X2SON
DQN
4
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 3
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV71310PDBVR
SOT-23
DBV
5
3000
178.0
9.0
TLV71311PDBVR
SOT-23
DBV
5
3000
178.0
TLV71312PDBVR
SOT-23
DBV
5
3000
178.0
TLV71312PDQNR
X2SON
DQN
4
3000
TLV71312PDQNT
X2SON
DQN
4
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71315PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV71315PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71315PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV713185PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV713185PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV713185PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71318PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV71318PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71318PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71320DQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71320DQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71325PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV71325PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLV71325PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV713285PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV713285PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV713285PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71328PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV71328PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71328PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71330PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV71330PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71330PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71333PDBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
TLV71333PDQNR
X2SON
DQN
4
3000
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
TLV71333PDQNT
X2SON
DQN
4
250
180.0
9.5
1.16
1.16
0.63
4.0
8.0
Q2
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV71310PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71311PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71312PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71312PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2013
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV71312PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71315PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71315PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71315PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV713185PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV713185PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV713185PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71318PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71318PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71318PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71320DQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71320DQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71325PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71325PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71325PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV713285PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV713285PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV713285PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71328PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71328PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71328PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71330PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71330PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71330PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
TLV71333PDBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71333PDQNR
X2SON
DQN
4
3000
180.0
180.0
30.0
TLV71333PDQNT
X2SON
DQN
4
250
180.0
180.0
30.0
Pack Materials-Page 3
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