SN54LVTZ244, SN74LVTZ244 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS302C – SEPTEMBER 1993 – REVISED JULY 1995 D D D D D D 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54LVTZ244 . . . FK PACKAGE (TOP VIEW) 1A2 2Y3 1A3 2Y2 1A4 description 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 These octal buffers / drivers are designed specifically for low-voltage (3.3-V) VCC operation with the capability to provide a TTL interface to a 5-V system environment. 3 2OE D SN54LVTZ244 . . . J PACKAGE SN74LVTZ244 . . . DB, DW, OR PW PACKAGE (TOP VIEW) State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation High-Impedance State During Power Up and Power Down Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (J) DIPs 2Y4 1A1 1OE VCC D These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVTZ244 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVTZ244 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74LVTZ244 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTZ244, SN74LVTZ244 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS302C – SEPTEMBER 1993 – REVISED JULY 1995 logic symbol† 1OE 1A1 1A2 1A3 1A4 1 logic diagram (positive logic) 1OE 2 18 4 16 6 14 8 12 1Y1 1A1 2OE 1Y3 1A2 2A2 2A3 2A4 4 16 6 14 8 12 1Y1 1Y2 1Y3 EN 11 9 13 7 15 5 17 3 1Y4 2Y1 2Y2 2Y3 2OE 19 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2A1 2A2 2A3 2A4 2 18 1Y4 1A4 2A1 2 1Y2 1A3 19 1 EN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 SN54LVTZ244, SN74LVTZ244 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS302C – SEPTEMBER 1993 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . – 0.5 V to 7 V Current into any output in the low state, IO: SN54LVTZ244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTZ244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTZ244 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTZ244 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Operating free-air temperature range, TA: SN54LVTZ244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74LVTZ244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) SN54LVTZ244 SN74LVTZ244 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current – 24 – 32 mA Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate ∆t /∆VCC Power-up ramp rate High-level input voltage 2 Outputs enabled 2 10 200 TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. – 55 V 10 – 40 ns / V µs / V 200 125 V 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVTZ244, SN74LVTZ244 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS302C – SEPTEMBER 1993 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = MIN to MAX‡, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = – 8 mA IOH = – 24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V II Ioff IOZPU§ IOZPD§ SN54LVTZ244 TYP† MAX TEST CONDITIONS –1.2 VCC – 0.2 2.4 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 VCC = 0 to 3.6 V VI = 0 VI or VO = 0 to 4.5 V VO = 0.5 V to 3 V, VO = 0.5 V to 3 V, II(hold) I(h ld) VCC = 3 V VI = 0.8 V VI = 2 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, VO = 3 V VO = 0.5 V ICC VCC = 3.6 V, VI = VCC or GND IO = 0, V 0.55 0.55 Control inputs Data inputs 10 10 ±1 ±1 1 1 –5 OE = X OE = X A inputs 75 75 –75 –75 ± 100 µA ± 50 µA ± 50 µA µA 5 5 µA –5 –5 µA Outputs high 0.12 0.5 0.12 0.225 Outputs low 8.6 15 8.6 15 0.12 0.5 0.12 0.225 Outputs disabled ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 0.3 4 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 µA –5 Co 8 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § This parameter is specified by characterization. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 V 2 0.2 VI = VCC or GND VI = VCC UNIT V 2 0.2 VCC = 0 or MAX‡, VCC = 1.5 V to 0, SN74LVTZ244 TYP† MAX MIN –1.2 VCC – 0.2 2.4 IOH = – 32 mA IOL = 100 µA IOL = 64 mA VI = 5.5 V VCC = 0 V, VCC = 0 V to 1.5 V, MIN 0.2 mA mA 4 pF 8 pF SN54LVTZ244, SN74LVTZ244 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS302C – SEPTEMBER 1993 – REVISED JULY 1995 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTZ244 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y VCC = 3.3 V ± 0.3 V SN74LVTZ244 VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN TYP† MAX VCC = 2.7 V MIN MAX MIN 1 4.7 5.2 1 2.5 4.1 5 1 4.4 5.4 1 2.5 4.1 5.2 1 5.4 6.5 1 2.7 5.2 6.3 1.1 5.4 7.6 1.1 3.1 5.2 6.7 1.9 6.2 6.9 1.9 3.9 5.6 6.3 1.8 5.5 6 1.8 3.2 5.1 5.6 UNIT MAX ns ns ns † All typical values are at VCC = 3.3 V, TA = 25°C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTZ244, SN74LVTZ244 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS302C – SEPTEMBER 1993 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 2.7 V 1.5 V 0V 1.5 V Data Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL VOH Output 1.5 V 1.5 V 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 2.7 V Output Control tPZL VOH Output 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Input th Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated