CS35L01/03 2.9 W Mono Class-D Audio Amplifier with Low Idle Current CS35L01 & CS35L03 Features General Description Filterless Hybrid Class-D Architecture The CS35L01 and the CS35L03 are 2.9W high efficiency Hybrid Class-D audio amplifiers with low idle current consumption. – <1 mA Quiescent Current – 1 x 2.9 W into 4 Ω (10% THD+N) – 1 x 2.3 W into 4 Ω (1% THD+N) – 1 x 1.7 W into 8 Ω (10% THD+N) – 1 x 1.4 W into 8 Ω (1% THD+N) Advanced ΔΣ Closed-loop Modulation – 98 dB Signal-to-Noise Ratio (A-Weighted) – 0.02% THD+N @ 1 W (SD & HD Mode) Integrated Protection and Automatic Recovery for Output Short-circuit and Thermal Overload Pin-compatible 9-ball WLCSP family for easy upgrade path – CS35L01: +6 dB default Gain – CS35L03: +12 dB default Gain Pop and Click Suppression Common Applications Mobile Phones Laptops/Netbooks The CS35L01/03 features an advanced closed-loop architecture to provide 0.02% THD+N at 1 W and -75 dB PSRR at 217 Hz. A flexible Hybrid Class-D output stage offers four modes of operation: Standard Class-D (SD) mode offers full audio bandwidth and high audio performance; Hybrid Class-D (HD) mode offers a substantial reduction in idle power consumption with an integrated ClassH controller; Reduced Frequency Class-D (FSD) mode reduces the output switching frequency, producing lower electromagnetic interference (EMI); and Reduced Frequency Hybrid Class-D (FHD) mode produces both the lower idle power consumption of HD mode and the reduced EMI benefits of FSD mode. Requiring minimal external components and PCB space, the CS35L01 and CS35L03 are available in a 1.2 mm x 1.2 mm, 9-ball WLCSP package in Commercial grade (-10°C to +70°C). Please see “Ordering Information” on page 33 for package options and gain configurations. Portable Navigation Devices Active Speakers Portable Gaming MODE LDO Filter Class-H Controller VBATT 2.5V - 5V Low Drop-Out Voltage Regulator Shutdown Gate Drivers Audio In + Gain Advanced ΔΣ Modulator Speaker Out + Speaker Out Gate Drivers Audio In - Gain Internal Oscillator Short Circuit/Thermal Protection GND Advance Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) APR '10 DS909A2 CS35L01/03 TABLE OF CONTENTS 1. BALL DESCRIPTIONS FOR CS35L01 & CS35L03 .............................................................................. 5 2. DIGITAL BALL CONFIGURATIONS ..................................................................................................... 6 3. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 7 4. CHARACTERISTICS & SPECIFICATIONS ........................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8 ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES ................................................... 9 ELECTRICAL CHARACTERISTICS - SD MODE ................................................................................ 10 ELECTRICAL CHARACTERISTICS - FSD MODE .............................................................................. 11 ELECTRICAL CHARACTERISTICS - HD MODE ................................................................................ 12 ELECTRICAL CHARACTERISTICS - FHD MODE ............................................................................. 13 DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS ............................................... 14 POWER-UP & POWER-DOWN CHARACTERISTICS ........................................................................ 14 5. APPLICATIONS ................................................................................................................................... 15 5.1 MODE Descriptions ....................................................................................................................... 15 5.1.1 Standard Class-D Modes of Operation ................................................................................. 15 5.1.1.1 SD Mode .................................................................................................................... 15 5.1.1.2 FSD Mode .................................................................................................................. 15 5.1.2 Hybrid Class-D Modes of Operation ...................................................................................... 15 5.1.2.1 HD Mode .................................................................................................................... 16 5.1.2.2 FHD Mode ................................................................................................................. 16 5.2 Reducing the Gain with External Series Resistors ........................................................................ 16 5.3 Output Filtering with the CS35L01/03 ............................................................................................ 17 5.3.1 Reduced Filter Order with the CS35L01/03 .......................................................................... 17 5.3.2 Filter Component Selection ................................................................................................... 17 5.3.3 Output Filter Power Dissipation Considerations .................................................................... 18 5.3.3.1 Conduction Losses for All modes of Operation ......................................................... 18 5.3.3.2 Switching Losses in SD/FSD Mode ........................................................................... 18 5.3.3.3 Switching Losses in HD/FHD. .................................................................................... 18 5.4 Power-Up and Power-Down .......................................................................................................... 19 5.4.1 Recommended Power-Up Sequence .................................................................................... 19 5.4.1.1 Zero-Crossing on Power-Up Functionality ................................................................. 19 5.4.2 Recommended Power-Down Sequence ............................................................................... 20 5.5 Over Temperature Protection ........................................................................................................ 20 6. TYPICAL PERFORMANCE PLOTS ..................................................................................................... 21 6.1 SD Mode Typical Performance Plots ............................................................................................. 21 6.2 FSD Mode Typical Performance Plots ........................................................................................... 23 6.3 HD Mode Typical Performance Plots ............................................................................................. 25 6.4 FHD Mode Typical Performance Plots ........................................................................................... 27 7. PARAMETER DEFINITIONS ................................................................................................................ 29 8. PACKAGING AND THERMAL INFORMATION .................................................................................. 30 8.1 Package Drawings and Dimensions .............................................................................................. 30 8.2 Recommend PCB Footprint and Routing Configuration ................................................................ 31 8.3 Package Thermal Performance ..................................................................................................... 31 8.3.1 Determining Maximum Ambient Temperature ....................................................................... 32 9. ORDERING INFORMATION ................................................................................................................ 33 10. REVISION HISTORY .......................................................................................................................... 33 2 DS909A2 CS35L01/03 LIST OF FIGURES Figure 1. Top View of WLCSP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Typical Connection Diagram for SD & FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Typical Connection Diagram for HD & FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Adjusting Gain via External Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. Optional Output Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. Power-Up Timing with Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Power Up Timing without Input Zero-Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. THD+N vs. Output Power - SD Mode RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. THD+N vs. Output Power - SD Mode RL = 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. THD+N vs. Frequency - SD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 11. THD+N vs. Frequency - SD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12. THD+N vs. Frequency - SD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. Frequency Response - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14. Idle Current Draw vs. VBATT - SD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15. Output Power vs. VBATT - SD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 16. Efficiency vs. Output Power - SD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 17. Efficiency vs. Output Power - SD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18. Supply Current vs. Output Power - SD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 19. Supply Current vs. Output Power - SD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 20. THD+N vs. Output Power - FSD Mode RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 21. THD+N vs. Output Power - FSD Mode RL = 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 22. THD+N vs. Frequency - FSD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 23. THD+N vs. Frequency - FSD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 24. THD+N vs. Frequency - FSD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 25. Frequency Response - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 26. Idle Current Draw vs. VBATT - FSD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 27. Output Power vs. VBATT - FSD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 28. Efficiency vs. Output Power - FSD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 29. Efficiency vs. Output Power - FSD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 30. Supply Current vs. Output Power - FSD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 31. Supply Current vs. Output Power - FSD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 32. THD+N vs. Output Power - HD Mode RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 33. THD+N vs. Output Power - HD Mode RL = 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 34. THD+N vs. Frequency - HD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 35. THD+N vs. Frequency - HD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 36. THD+N vs. Frequency - HD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 37. Frequency Response- HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 38. Idle Current Draw vs. VBATT - HD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 39. Output Power vs. VBATT - HD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 40. Efficiency vs. Output Power - HD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 41. Efficiency vs. Output Power - HD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 42. Supply Current vs. Output Power - HD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 43. Supply Current vs. Output Power - HD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 44. THD+N vs. Output Power - FHD Mode RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 45. THD+N vs. Output Power - FHD Mode RL = 4 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 46. THD+N vs. Frequency - FHD Mode VBATT = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 47. THD+N vs. Frequency - FHD Mode VBATT = 4.2 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 48. THD+N vs. Frequency - FHD Mode VBATT = 3.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 49. Frequency Response - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 50. Idle Current Draw vs. VBATT - FHD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 51. Output Power vs. VBATT - FHD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 52. Efficiency vs. Output Power - FHD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DS909A2 3 CS35L01/03 Figure 53. Efficiency vs. Output Power - FHD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 54. Supply Current vs. Output Power - FHD Mode RL = 8 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 55. Supply Current vs. Output Power - FHD Mode RL = 4 Ω + 33 μH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LIST OF TABLES Table 1. LFILT+ and MODE Operation Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 2. θJA Specification for Typical PCB Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 DS909A2 CS35L01/03 1. BALL DESCRIPTIONS FOR CS35L01 & CS35L03 A1 IN+ B1 A2 MODE B2 LFILT + VBATT C1 C2 IN- SD A3 OUT- B3 GND C3 OUT+ Figure 1. Top View of WLCSP Pinout (Looking down through die) Ball Name # Description IN+ A1 Positive Analog Input (Input) - Differential positive audio signal input. MODE A2 Switching Mode (Input) - Controls the output switching modes of the CS35L01/03. OUT- A3 Negative PWM Output (Output) - Differential negative PWM output. LFILT+ B1 Low Drop Out Regulator Filter (Output) - Bypass capacitor connection point for internal LDO. Connecting this net to VBATT places the device into SD mode. VBATT B2 Positive Analog Power Supply (Input) - Positive power supply input. GND B3 Ground (Input) - Power supply ground. IN- C1 Negative Analog Input (Input) - Differential negative audio signal input. SD C2 Shutdown (Input) - Pulling this net low places the CS35L01/03 in shutdown. OUT+ C3 Positive PWM Output (Output) - Differential Positive PWM output. DS909A2 5 CS35L01/03 2. DIGITAL BALL CONFIGURATIONS See (Note 1) and (Note 2) below the table. Power Supply VBATT I/O Name Ball Direction Internal Connections Configuration SD C2 Input No Internal Pull Up Hysteresis on CMOS Input MODE A2 Input No Internal Pull Up Hysteresis on CMOS Input Note: 1. Refer to specification table “Digital Interface Specifications and Characteristics” on page 14 for details on the digital I/O characteristics. 2. I/O voltage levels must not exceed the voltage listed in table “Absolute Maximum Ratings” on page 8. 6 DS909A2 CS35L01/03 3. TYPICAL CONNECTION DIAGRAMS 2.5V - 5V 0.1uF System Controller LFILT+ 10uF VBATT MODE SD Audio In+ AIN+ Audio In- AIN+ OUT+ OUT- GND Figure 2. Typical Connection Diagram for SD & FSD Mode 2.5V - 5V (Note 3) 1uF System Controller 10uF LFILT+ 0.1uF VBATT MODE SD Audio In+ AIN+ Audio In- AIN+ OUT+ OUT- GND Figure 3. Typical Connection Diagram for HD & FHD Mode Note: 3. The value of the capacitance connected to the LFILT+ net should not exceed 4.7 μF. Presence of a capacitance above 4.7 μF will prevent proper HD and FHD operation. DS909A2 7 CS35L01/03 4. CHARACTERISTICS & SPECIFICATIONS Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; Input Signal = 997 Hz Differential Sine; TA = 25°C; VBATT = 5 V; RL = 8 Ω; 10 Hz to 20 kHz Measurement Bandwidth; Measurements taken with AES17 measurement filter and Audio Precision AUX-0025 passive filter. RECOMMENDED OPERATING CONDITIONS GND = 0 V; All voltages with respect to ground. Please see (Note 4). Parameters Symbol Min Typ Max Units VBATT 2.5 5.0 5.5 V Ambient Temperature TA -10 - +70 °C Junction Temperature TJ -10 - +150 °C DC Power Supply Supply Voltage Temperature ABSOLUTE MAXIMUM RATINGS GND = 0 V; All voltages with respect to ground. Parameters Symbol Min Max Units VBATT IVDREG -0.3 6.0 10 μA Iin - ±10 mA TA Tstg -20 -65 +125 +150 °C °C DC Power Supply Supply Voltage LFILT+ Current (Note 5) V Inputs Input Current Temperature Ambient Operating Temperature (power applied) Storage Temperature WARNING: Operation at or beyond these limits may result in permanent damage to the device. Notes: 4. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. 5. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device. 8 DS909A2 CS35L01/03 ELECTRICAL CHARACTERISTICS - ALL OPERATIONAL MODES Parameters Symbol Min Typ ILFILT+ - 10 - μA ZLFILT+ - 0.7 - Ω VBLIM - 3.0 - VDC CS35L03 CS35L01 - 0.014•VBATT 0.027•VBATT - Vrms Vrms Input Level for Entering VBATT Operation CS35L03 V in HD/FHD Modes (Note 9) IN-VBATT CS35L01 - 0.09 0.18 - Vrms Vrms tLDO - 800 - ms VLDO - 1.0 - V - +/-2 - mV Max. Current from LFILT+ (Note 6) LFILT+ Output Impedance VBATT Limit for HD/FHD Mode (Note 7) Input Level for Entering LDO Operation in HD/FHD Modes (Note 8) LDO Entry Time Delay LDO Level for HD/FHD Modes VIN-LDO Test Conditions VOFFSET Inputs AC coupled to GND Output Offset Voltage Amplifier Gain Shutdown Supply Current AV CS35L03 CS35L01 - 12 6 - dB dB IA(SD) SD = Low - 0.05 - μA - 270 - mΩ RDS(ON) Ibias = 0.5 A MOSFET On Resistance Max Units Thermal Error Threshold (Note 10) TTE - 150 - °C Thermal Error Retry Time (Note 10) RTE - 100 - ms UVLO - 1.9 - V GD - 10 - μs VBATT = 5 VDC - 90 - % VBATT = 3.7 VDC - 89 - % VBATT = 5 VDC - 84 - % VBATT = 3.7 VDC - 82 - % Under Voltage Lockout Threshold Total Group Delay Operating Efficiency η 4 Ω + 33μH 8 Ω + 33μH Load Load Output Levels at 10% THD+N Note: 6. No external loads should be connected to the LFILT+ net. Any connection of a load to this point may result in errant operation or performance degradation in the device. 7. When VBATT is below this threshold (VBLIM), operation is automatically restricted to SD mode. 8. When operating in HD or FHD mode and the differential input voltage remains below the input level threshold (VIN-LDO) for a period of time (tLDO), the PWM outputs will be powered by the internally generated LDO supply (VLDO). 9. When operating in HD or FHD mode and the differential input voltage is above this input level threshold (VIN-VBATT), the PWM outputs will powered directly from the VBATT supply. 10. Refer to Section 5.5 for more information on Thermal Error functionality. DS909A2 9 CS35L01/03 ELECTRICAL CHARACTERISTICS - SD MODE Parameters Symbol Output Power (Continuous Average) PO Test Conditions Min Typ Max Units THD+N = 1% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.36/0.95/0.73 2.29/1.59/1.21 - W W THD+N = 10% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.69/1.18/0.91 2.86/1.99/1.52 - W - 0.02 - % W Total Harmonic Distortion + Noise THD+N PO = 1.0 W Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz - 75 75 - dB dB Common-Mode Rejection Ratio CMRR Vripple = 1 VPP, fripple = 217 Hz - 55 - dB - 96 97 - dB dB - 54 49 - μVrms μVrms - 100 100 - μVrms μVrms -0.1 0 0.4 dB - 192 - kHz VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC - 1.06 1.00 0.97 - mA mA mA CS35L03 CS35L01 - 65 100 - kΩ kΩ RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) CS35L03 CS35L01 - 0.84/0.71/0.62 1.69/1.41/1.23 - Vrms Vrms Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) CS35L03 CS35L01 AIN+ connected to AIN- Idle Channel Noise A-Weighted ICNA CS35L03 CS35L01 AIN+ connected to AIN- Idle Channel Noise ICN CS35L03 CS35L01 Frequency Response FR 20 Hz to 20 kHz Output Switching Frequency fsw1 AIN+ connected AIN-, No Output Load Idle Current Draw (Note 11) Input Impedance, Single Ended Input Voltage @ 1 % THD+N 10 IIDLE ZIN VICLIP DS909A2 CS35L01/03 ELECTRICAL CHARACTERISTICS - FSD MODE Parameters Symbol Output Power (Continuous Average) PO Test Conditions Min Typ THD+N = 1% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.31/0.92/0.71 2.21/1.55/1.17 - W W THD+N = 10% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.67/1.17/0.91 2.83/1.97/1.51 - W - 0.15 - % Total Harmonic Distortion + Noise THD+N PO = 1.0 W Max Units W Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz - 75 75 - dB dB Common-Mode Rejection Ratio CMRR Vripple = 1 VPP, fripple = 217 Hz - 55 - dB - 81 81 - dB dB - 300 300 - μVrms μVrms - 660 660 - μVrms μVrms -4.0 0 0.5 dB - 76 - kHz VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC - 0.88 0.86 0.85 - mA mA mA CS35L03 CS35L01 - 160 240 - kΩ kΩ RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) CS35L03 CS35L01 - 0.82/0.69/0.60 1.63/1.36/1.20 - Vrms Vrms Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) CS35L03 CS35L01 AIN+ connected to AIN- Idle Channel Noise A-Weighted ICNA CS35L03 CS35L01 AIN+ connected to AIN- Idle Channel Noise ICN CS35L03 CS35L01 Frequency Response FR 20 Hz to 20 kHz Output Switching Frequency fsw2 AIN+ connected AIN-, No Output Load Idle Current Draw (Note 11) Input Impedance, Single Ended Input Voltage @ 1 % THD+N IIDLE ZIN VICLIP Note: 11. Idle Current Draw (IIDLE) is specified without any output filtering. Refer to Section 5.3 on page 17 for information on output filtering. DS909A2 11 CS35L01/03 ELECTRICAL CHARACTERISTICS - HD MODE Parameters Symbol Output Power (Continuous Average) PO Test Conditions Min Typ THD+N = 1% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.36/0.95/0.73 2.29/1.59/1.21 - W W THD+N = 10% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.69/1.18/0.91 2.86/1.99/1.52 - W - 0.02 - % Total Harmonic Distortion + Noise THD+N PO = 1.0 W Max Units W Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz - 75 75 - dB dB Common-Mode Rejection Ratio CMRR Vripple = 1 VPP, fripple = 217 Hz - 55 - dB - 97 98 - dB dB - 49 43 - μVrms μVrms - 86 85 - μVrms μVrms -0.1 0 0.4 dB - 192 - kHz VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC - 0.94 0.94 0.94 - mA mA mA CS35L03 CS35L01 - 65 100 - kΩ kΩ RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) CS35L03 CS35L01 - 0.85/0.71/0.62 1.69/1.41/1.23 - Vrms Vrms Signal to Noise Ratio A-Weighted SNRA Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) CS35L03 CS35L01 AIN+ connected to AIN- Idle Channel Noise A-Weighted ICNA CS35L03 CS35L01 AIN+ connected to AIN- Idle Channel Noise ICN CS35L03 CS35L01 Frequency Response FR 20 Hz to 20 kHz Output Switching Frequency fsw1 AIN+ connected AIN-, No Output Load Idle Current Draw (Note 13) Input Impedance, Single Ended Input Voltage @ 1% THD+N 12 IIDLE ZIN VICLIP DS909A2 CS35L01/03 ELECTRICAL CHARACTERISTICS - FHD MODE Parameters Symbol Output Power (Continuous Average) PO Test Conditions Min Typ THD+N = 1% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.31/0.92/0.71 2.20/1.55/1.51 - W W THD+N = 10% RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) RL = 4 Ω (VBATT = 5.0/4.2/3.7 VDC) - 1.67/1.17/0.91 2.83/1.97/1.51 - W - 0.15 - % Total Harmonic Distortion + Noise THD+N PO = 1.0 W Max Units W Power Supply Rejection Ratio PSRR Vripple = 200 mVPP, AINx AC coupled to GND @ 217 Hz @ 1 kHz - 75 75 - dB dB Common-Mode Rejection Ratio CMRR Vripple = 1 VPP, fripple = 217 Hz - 55 - dB - 93 94 - dB dB - 71 66 - μVrms μVrms - 125 125 - μVrms μVrms Inputs AC Coupled to Ground, Referenced to 1% THD+N (Note 12) Signal to Noise Ratio A-Weighted SNRA Idle Channel Noise A-Weighted ICNA Idle Channel Noise ICN CS35L03 CS35L01 Frequency Response FR 20 Hz to 20 kHz -4.0 0 0.5 dB Output Switching Frequency fsw1 LDO Operation - 192 - kHz Output Switching Frequency fsw2 VBATT Operation - 76 - kHz VBATT = 5 VDC VBATT = 4.2 VDC VBATT = 3.7 VDC - 0.94 0.94 0.94 - mA mA mA CS35L03 CS35L01 - 160 240 - kΩ kΩ RL = 8 Ω (VBATT = 5.0/4.2/3.7 VDC) CS35L03 CS35L01 - 0.83/0.70/0.61 1.66/1.39/1.22 - Vrms Vrms CS35L03 CS35L01 AIN+ connected to AINCS35L03 CS35L01 AIN+ connected to AIN- AIN+ connected AIN-, No Output Load Idle Current Draw (Note 13) Input Impedance, Single Ended Input Voltage @ 1 % THD+N IIDLE ZIN VICLIP Note: 12. SNRA dB is referenced to the output signal amplitude resulting in the specified output power at THD+N <1%. See “Parameter Definitions” on page 29 for more information. 13. Idle Current Draw (IIDLE) is specified without any output filtering. Refer to Section 5.3 on page 17 for information on output filtering. At idle, the output devices will switch at the same rate in HD and FHD mode. FHD only changes the output switching frequency when the input levels are above the “Input Level for Entering VBATT Operation in HD/FHD Modes (VIN-VBATT) given in “Electrical Characteristics - All Operational Modes” on page 9. DS909A2 13 CS35L01/03 DIGITAL INTERFACE SPECIFICATIONS AND CHARACTERISTICS Parameters Symbol Min Max Units Iin - ±10 μA Input Capacitance - 10 pF SD Pulse Width Requirement 1 - ms Input Leakage Current Logic I/Os (Applicable to GAIN_SEL, MODE, and SD) High-Level Input Voltage VIH 0.7•VBATT - V Low-Level Input Voltage VIL - 0.3•VBATT V POWER-UP & POWER-DOWN CHARACTERISTICS Parameters Start-Up Time Symbol (Note 14) Zero Crossing Power-Up Timeout Power-Down Time tstart ttimeout toff Test Conditions Min Typ Max Units After low-to-high SD pin transition edge - 18 - ms No audio input applied - 25 - ms After high-to-low SD pin transition edge - 1 - ms Note: 14. Start-Up Time (tstart) refers to the internal start-up time from when SD is released to when the device is ready to activate the PWM outputs. The total power-up time from SD release to the PWM outputs becoming active will vary based on the input signal, not exceeding the Start-Up Time + Zero Crossing Power-Up Timeout (tstart + ttimeout). For more information, refer to Section 5.4. 14 DS909A2 CS35L01/03 5. APPLICATIONS 5.1 MODE Descriptions The CS35L01/03 devices can be operated in one of four operating modes, determined by the MODE pin and the LFILT+ pin. The four modes of operation are Standard Class-D operation (SD), Reduced Frequency Standard Class-D operation (FSD), Hybrid Class-D operation (HD), and Reduced Frequency Hybrid ClassD operation (FHD). Each of these modes can be leveraged to optimize different performance criteria in an array of applications. LFILT+ connected to: MODE connected to: GND VBATT VBATT Reduced Frequency Class-D Mode (FSD) Standard Class-D Mode (SD) Filter Cap to Ground Reduced Frequency Hybrid Class-D Mode (FHD) Hybrid Class-D Mode (HD) Table 1. LFILT+ and MODE Operation Configurations 5.1.1 Standard Class-D Modes of Operation 5.1.1.1 SD Mode Standard Class-D (SD) mode supports full audio bandwidth with very good SNR and THD+N performance. This mode of operation is characterized by a traditional closed loop, analog ΔΣ modulated ClassD amplifier. With an output switching frequency of 192 kHz, this mode ensures flat frequency response across the entire audio frequency range. 5.1.1.2 FSD Mode The Reduced Frequency Class-D (FSD) mode provides competitive audio performance and a reduction in radiated emissions by decreasing the switching frequency of the output devices to 76 kHz. This reduction in switching frequency reduces the high-frequency energy being created by the output switching events. Idle channel noise is slightly higher in this mode of operation than SD mode, with the trade-off being better EMI performance and power consumption. 5.1.2 Hybrid Class-D Modes of Operation Hybrid Class-D and Reduced Frequency Hybrid Class-D modes of operation allows the rail voltage for the output devices to switch between a high voltage net and a low voltage net depending on the audio content being amplified. This is explained in more detail in Section 5.1.2.1 and Section 5.1.2.2. Operation in these modes requires that the voltage present on the VBATT pin be above the level listed as “VBATT Limit for HD/FHD Mode (VBLIM)” in “Electrical Characteristics - All Operational Modes” on page 9. If it is not, HD and FHD modes of operation of the device will automatically be disabled and operation will be limited to the SD mode of operation. DS909A2 15 CS35L01/03 In both HD and FHD mode, the value of the capacitance connected to the LFILT+ pin must not exceed 4.7 μF. If this value is greater than 4.7 μF, it will prevent the rail voltage of the output devices from transitioning properly between VBATT and the internal LDO. 5.1.2.1 HD Mode Hybrid Class-D mode (HD) provides competitive analog performance with a substantial reduction in idle power dissipation and radiation emissions. In this mode, the output switches at 192 kHz and a secondary supply is derived from VBATT using an internal 1.0-VDC low drop-out linear regulator (LDO). When the output signal is at a low amplitude, the Class-D output stage begins to switch from the lower rail voltage created by the internal LDO. This not only decreases idle power consumption when output capacitors are used, but also reduces electromagnetic emissions by reducing the amplitude of the square waves being created at the output of the CS35L01/03 when operating at low amplitude or idle power. 5.1.2.2 FHD Mode The Reduced Frequency Hybrid Class-D (FHD) mode provides the best overall EMI performance and the lowest power consumption with slightly decreased frequency response near the top frequency range of the audio band, for high amplitude signals. In this mode of operation, the output switching frequency is reduced to 76 kHz during high amplitude transients on the output. The threshold at which this transition from 192-kHz to 76-kHz switching rate occurs is given as the Input Level Threshold for FHD Operation in “Electrical Characteristics - FHD Mode” on page 13. Combined with the lower amplitude switching offered by the Hybrid design, this reduction in switching energy dramatically reduces the emissions levels of the output stage and its associated components. 5.2 Reducing the Gain with External Series Resistors If necessary, it is possible to decrease the gain of the CS35L01/03 by adding series resistors to the audio input signal as is shown in Figure 4 below. Audio In+ Audio In- RIN RIN x AIN+ x AIN- Figure 4. Adjusting Gain via External Series Resistance If input resistors are added, the new gain of the amplifier can be determined by the following equation: Z IN A V ( adjusted ) = A V – 20 × log -------------------------- Z IN + Z EXT Where: AV(adjusted) = The new, adjusted gain of the system 16 DS909A2 CS35L01/03 ZIN = Input impedance of the device being used (See “Electrical Characteristics - SD Mode” on page 10, “Electrical Characteristics - FSD Mode” on page 11, “Electrical Characteristics - HD Mode” on page 12, or “Electrical Characteristics - FHD Mode” on page 13 for this value.) ZEXT = Value of the resistor added in series with the inputs AV = Original gain of the device being used (See “Electrical Characteristics - All Operational Modes” on page 9 for this value.) 5.3 Output Filtering with the CS35L01/03 The CS35L01/03 is specifically designed to minimize radiated electromagnetic interference (EMI) signals. All of the devices are capable of meeting all stated data sheet performance numbers with no special filtering required. Additionally, the device has shown to be below the compliance limits of both FCC and CISPR testing with no external filtering required. Ultimately, compliance with any radiated emissions requirements depends significantly on the entire system under test. In applications were system-level trade-offs such as compromised component layout or lengthy speaker wires have increased emissions levels, a passive output filter can be added to the outputs of the device in order to decrease EMI levels. 5.3.1 Reduced Filter Order with the CS35L01/03 In applications which require an output filter, the unique design of the CS35L01/03 allows a much smaller, less expensive output filter to be used than what is normally found in Class-D amplifiers. In contrast to a second order filter implemented with a series inductive element (traditional inductor or ferrite beads) and a shunt capacitive element, basic filtering for the CS35L01/03 is accomplished by a single-order capacitive element attached to the OUTx terminals. This is highlighted in Figure 5 below. Of course, if the system requires more aggressive filtering, a ferrite bead can be added in series with the outputs to further attenuate system level noise. OUT+ OUT- OUT+ x LFILT C FILT OUT- x LFILT x C FILT x C FILT Traditional 2nd Order Optional Filter C FILT CS35L01/03’s Minimized Optional Filter Figure 5. Optional Output Filter Components 5.3.2 Filter Component Selection Usually, the need for output filtering is determined after the system under test has failed EMI testing. During this testing, problem frequencies are easily identified by the peaks which appear in the spectral plots gathered in the EMI testing. Selection of the filter components should ensure that shunt elements (i.e. CFILT in Figure 5) present a very low impedance at the frequency corresponding to the tallest peak in the spectral plot. If needed, series components such as ferrite beads (i.e. LFILT in Figure 5) should be chosen to present a very high impedance at the frequency corresponding to the tallest peak in the spectral plot. Careful attention should be paid to the current-carrying capabilities of any included ferrite beads and the impedance of the ferrite beads in the audio band. A proper trade-off in ferrite bead selection is one that DS909A2 17 CS35L01/03 allows the ferrite bead to sufficiently attenuate the problematic high-frequency emissions without compromising audio performance. 5.3.3 Output Filter Power Dissipation Considerations In systems without inductive series elements like inductors or ferrite beads, power losses in the output filter are equal to the switching losses that occur in the system due to the cyclical charging and discharging of capacitors connected to the amplifier outputs. In systems that require an inductive series element, conducted losses also occurs due to the series impedance added to the output path. 5.3.3.1 Conduction Losses for All modes of Operation For all modes of operation (SD, FSD, HD, and FHD) of the CS35L01/03, the conduction losses are governed by the equation: P = I2Z Where: P = Power dissipated in the series impedance. I = RMS AC output current Z = impedance of the series element at the frequency of the AC current This equation neglects any series impedances presented by the PCB traces or speaker wires in the output path. 5.3.3.2 Switching Losses in SD/FSD Mode Switching losses in SD/FSD Mode are governed by the equation 1 P = --- CV 2 f 2 Where: P = Power dissipated in the capacitor (neglecting parasites). C = Value of filtering capacitor V = Peak voltage developed across the capacitor f = Switching frequency of the outputs These calculations are straightforward, as the peak voltage is simply the voltage level attached to VBATT, the capacitor is the value of capacitor that has been added for filtering (neglecting parasitic board capacitances), and the frequency is 192 kHz or 76 kHz for SD and FSD, respectively. 5.3.3.3 Switching Losses in HD/FHD. Many factors affect the switching losses when the device is operated in HD/FHD mode. These factors include the frequency of the content being amplified, the voltage level of VBATT, and the amplitude of the output signal will factor into both the voltage presented across the capacitors and the frequency at which the capacitors are charged or discharged. 18 DS909A2 CS35L01/03 Static signals (i.e. sine waves at a fixed amplitude) are easier to consider than are dynamic signals (i.e. musical content), as they are governed by the same equation as that listed in Section 5.3.3.1 and Section 5.3.3.2 on page 18. Modifications to that equation are limited to the voltage term (V) and the frequency term (f), depending on whether the static input signal amplitude is causing the output devices to switch at 76 kHz or 192 kHz, and to operate off of the VBATT supply or off of the internally generated LDO. It is important to note that the HD and FHD modes offer significant improvement over traditional Class-D in idle power dissipation when an external output filter is necessary. This is because the voltage term (V) is significantly reduced in HD and FHD mode. As can be seen in the equation, this is notable because reduction in the operating voltage reduces power losses not linearly, but instead exponentially- due to the voltage squared term (V2). It is also notable that when operated at high output levels, FHD modes also offers unique improvement in output filter losses, due to reducing the switching frequency (f) at higher output levels. 5.4 Power-Up and Power-Down When pulled to a logic low state, the SD pin tristates the outputs and shuts down the CS35L01/03 device, putting it into a low power mode. 5.4.1 Recommended Power-Up Sequence 1. With the SD pin pulled low, apply power to the CS35L01/03 and wait for the power supply to be stable. 2. Set the SD pin high to begin normal operation. 5.4.1.1 Zero-Crossing on Power-Up Functionality The CS35L01/03 implements an input-signal zero-crossing detection function that is enabled during power-up. This function is designed to prevent audible artifacts and eliminate any need to mute the amplifier’s input audio signal during the power-up process. After a minimum start-up time of tstart, the CS35L01/03 will begin to detect input-signal zero-crossings. The amplifier will then enable its switching outputs at the time of the first detected input-signal zero-crossing transition. If no input-signal zero-crossing is detected before ttimeout, the zero-crossing function will timeout and the outputs will begin switching immediately. Both tstart and ttimeout are specified in “Power-Up & Power-Down Characteristics” on page 14. IN+/- SD IN+/VIH SD VIL tstart VIL ttimeout VBATT or VLDO tstart ttimeout Internal Start-Up Device Ready: Waiting for Zero Crossing Input Signal or t timeout VBATT or VLDO OUT+/- OUT+/Shut-Down / Low Power Mode Internal Start-Up Device Ready: Waiting for Zero Crossing Input Signal or ttimeout PWM OUT+/Active Figure 6. Power-Up Timing with Input Zero-Crossing DS909A2 VIH Shut-Down / Low Power Mode PWM OUT+/Active Figure 7. Power Up Timing without Input Zero-Crossing 19 CS35L01/03 5.4.2 Recommended Power-Down Sequence 1. Mute the audio supplied to the CS35L01/03. 2. Pull the SD pin low in order to reset the device and put it into the low power mode. 3. The power supply to the CS35L01/03 can now be removed. 5.5 Over Temperature Protection The CS35L01/03 is internally protected against thermal overload. Built in die temperature sensing circuitry monitors the die temperature and will place the device into shut-down if thermal overload occurs. A thermal overload is characterized by the die temperature reaching the Thermal Error Threshold (TTE) at which time the outputs will tristate and shut down. If the device has entered into shut-down due to a thermal overload, the die temperature must remain below the Thermal Error Threshold (TTE) for the time specified by the Thermal Error Retry Time (RTE) in order for the device to automatically return to normal operation. Both TTE and RTE are specified in “Electrical Characteristics - All Operational Modes” on page 9. 20 DS909A2 CS35L01/03 6. TYPICAL PERFORMANCE PLOTS Test Conditions (unless otherwise specified): GND = 0 V; All voltages with respect to ground; AV = 6 dB; Input Signal = 997 Hz Differential Sine; TA = 25°C; VBATT = 5.0 V; RL = 8 Ω; 10 Hz to 20 kHz Measurement Bandwidth; Measurements taken with AES17 measurement filter and Audio Precision AUX-0025 passive filter. 6.1 SD Mode Typical Performance Plots 10 10 5 5 5.0 V 4.2 V 3.7 V 2 1 5.0 V 4.2 V 3.7 V 2 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.01 0.007 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.007 1m 2 2m 5m 10m 20m 50m 10 500m 1 2 3 10 5 5 2 2 1 1 0.5 0.5 0.2 0.2 1.0 W 0.1 0.75 W % 0.05 0.1 0.05 0.1 W 0.02 0.1 W 0.02 0.01 0.01 0.005 0.005 0.5 W 0.5 W 0.002 0.001 20 200m Figure 9. THD+N vs. Output Power - SD Mode RL = 4 Ω Figure 8. THD+N vs. Output Power - SD Mode RL = 8 Ω % 100m W W 0.002 50 100 200 500 1k 2k 5k 10k 0.001 20 20k Hz 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 10. THD+N vs. Frequency - SD Mode VBATT = 5.0 V Figure 11. THD+N vs. Frequency - SD Mode VBATT = 4.2 V +4 10 +3.5 5 +3 2 +2.5 +2 1 +1.5 0.5 4Ω +1 0.2 0.625 W % d B r 0.1 A 0.05 0.1 W 8Ω -1.5 0.01 -2 -2.5 0.005 -3 0.5 W 0.002 -3.5 50 100 200 500 1k 2k 5k 10k Hz Figure 12. THD+N vs. Frequency - SD Mode VBATT = 3.7 V DS909A2 +0 -0.5 -1 0.02 0.001 20 +0.5 20k -4 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 13. Frequency Response - SD Mode 21 CS35L01/03 3.5 7.00 3.0 5.00 2.5 Output Power (W) Idle Current Draw (mA) 2200 pF 6.00 4.00 1000 pF 3.00 2.0 RL = 4 Ω 1% THD+N Ratio 1.5 2.00 1.0 1.00 0.5 470 pF RL = 4 Ω 10% THD+N Ratio RL = 8 Ω 10% THD+N Ratio RL = 8 Ω 1% THD+N Ratio No Filter 0.0 0.00 2.5 3 3.5 4 4.5 5 2.5 5.5 3.0 3.5 4.0 Figure 14. Idle Current Draw vs. VBATT - SD Mode RL = 8 Ω + 33 μH (Note 15) 5.0 5.5 Figure 15. Output Power vs. VBATT - SD Mode 100% 100% 90% 90% 80% 80% 3.7 V 5.0 V 4.2 V 70% 70% 60% 60% Efficiency (%) 3.7 V Efficiency (%) 4.5 VBATT Supply Voltage (V) VBATT (V) 50% 5.0 V 4.2 V 50% 40% 40% 30% 30% 20% 20% 10% 10% 0% 0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 0 0.5 1 1.5 Output Power (W) 2 2.5 3 Output Power (W) Figure 16. Efficiency vs. Output Power - SD Mode RL = 8 Ω + 33 μH Figure 17. Efficiency vs. Output Power - SD Mode RL = 4 Ω + 33 μH 0.70 0.40 0.35 0.60 4.2 V 4.2 V 0.30 0.50 Current Consumption (A) 3.7 V Supply Current (A) 0.25 5.0 V 0.20 0.15 3.7 V 5.0 V 0.40 0.30 0.20 0.10 0.10 0.05 0.00 0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W) Figure 18. Supply Current vs. Output Power - SD Mode RL = 8 Ω + 33 μH 0 0.5 1 1.5 2 2.5 3 Output Power (W) Figure 19. Supply Current vs. Output Power - SD Mode RL = 4 Ω + 33 μH Note: 15. “Idle Current Draw vs. VBATT - SD Mode” capacitor values refer to CFILT when configured as the “CS35L01/03’s Minimized Optional Output Filter,” shown in Figure 5 on page 17. 22 DS909A2 CS35L01/03 6.2 FSD Mode Typical Performance Plots 10 10 5 5 5.0 V 4.2 V 3.7 V 2 5.0 V 4.2 V 3.7 V 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.01 1m 2 2m 5m 10m 20m 50m W 100m 200m 500m 1 2 3 W Figure 20. THD+N vs. Output Power - FSD Mode RL = 8 Ω Figure 21. THD+N vs. Output Power - FSD Mode RL = 4 Ω 10 10 5 5 2 2 1.0 W 0.75 W 1 1 0.5 0.5 % % 0.1 W 0.2 0.1 0.1 0.05 0.05 0.5 W 0.5 W 0.02 0.01 20 50 100 200 0.1 W 0.2 500 1k 2k 0.02 5k 10k 0.01 20 20k 50 100 200 500 Hz 1k 2k 5k 10k 20k Hz Figure 23. THD+N vs. Frequency - FSD Mode VBATT = 4.2 V Figure 22. THD+N vs. Frequency - FSD Mode VBATT = 5.0 V 10 +4 +3.5 5 +3 +2.5 0.625 W 2 +2 +1.5 1 4Ω +1 0.5 d B r % A 0.1 W 0.2 +0.5 +0 -0.5 -1 8Ω 0.1 -1.5 -2 0.05 -2.5 0.5 W 0.02 -3 -3.5 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 24. THD+N vs. Frequency - FSD Mode VBATT = 3.7 V DS909A2 -4 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 25. Frequency Response - FSD Mode 23 CS35L01/03 3.5 3.50 3.0 2.50 2.5 2.00 Output Power (W) Idle Current Draw (mA) 2200 pF 3.00 1000 pF 1.50 RL = 4 Ω 10% THD+N Ratio 2.0 RL = 4 Ω 1% THD+N Ratio 1.5 1.0 1.00 RL = 8 Ω 10% THD+N Ratio 470 pF 0.50 0.5 No Filter RL = 8 Ω 1% THD+N Ratio 0.0 0.00 2.5 3 3.5 4 4.5 5 2.5 5.5 3.0 3.5 Figure 26. Idle Current Draw vs. VBATT - FSD Mode RL = 8 Ω + 33 μH (Note 16) 4.5 5.0 5.5 Figure 27. Output Power vs. VBATT - FSD Mode 100% 100% 90% 90% 80% 80% 3.7 V 4.2 V 5.0 V 70% 70% 4.2 V 3.7 V 5.0 V 60% Efficiency (%) 60% Efficiency (%) 4.0 VBATT Supply Voltage (V) VBATT (V) 50% 50% 40% 40% 30% 30% 20% 20% 10% 10% 0% 0% 0 0.25 0.5 0.75 1 1.25 1.5 0 1.75 0.5 1 1.5 2 2.5 3 Output Power (W) Output Power (W) Figure 28. Efficiency vs. Output Power - FSD Mode RL = 8 Ω + 33 μH Figure 29. Efficiency vs. Output Power - FSD Mode RL = 4 Ω + 33 μH 0.70 0.40 0.35 0.60 4.2 V 4.2 V 0.30 0.50 Current Consumption (A) 3.7 V Supply Current (A) 0.25 5.0 V 0.20 0.15 3.7 V 5.0 V 0.40 0.30 0.20 0.10 0.10 0.05 0.00 0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W) Figure 30. Supply Current vs. Output Power - FSD Mode RL = 8 Ω + 33 μH 0 0.5 1 1.5 2 2.5 3 Output Power (W) Figure 31. Supply Current vs. Output Power - FSD Mode RL = 4 Ω + 33 μH Note: 16. “Idle Current Draw vs. VBATT - FSD Mode” capacitor values refer to CFILT when configured as the “CS35L01/03’s Minimized Optional Output Filter”, shown in Figure 5 on page 17. 24 DS909A2 CS35L01/03 6.3 HD Mode Typical Performance Plots 10 10 5 5 5.0 V 4.2 V 3.7 V 2 1 5.0 V 4.2 V 3.7 V 2 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 0.007 1m 0.01 2m 5m 10m 20m 50m 100m 200m 500m 1 0.007 1m 2 2m 5m 10m 20m 50m W 100m 10 10 5 5 2 2 1 1 0.5 0.5 0.2 1 2 3 0.2 1.0 W 0.75 W 0.1 % 0.05 0.1 0.05 0.1 W 0.02 0.1 W 0.02 0.01 0.01 0.005 0.005 0.5 W 0.5 W 0.002 0.001 20 500m Figure 33. THD+N vs. Output Power - HD Mode RL = 4 Ω Figure 32. THD+N vs. Output Power - HD Mode RL = 8 Ω % 200m W 0.002 50 100 200 500 1k 2k 5k 10k 0.001 20 20k 50 100 200 500 Hz 1k 2k 5k 10k 20k Hz Figure 35. THD+N vs. Frequency - HD Mode VBATT = 4.2 V Figure 34. THD+N vs. Frequency - HD Mode VBATT = 5.0 V +4 10 +3.5 5 +3 2 +2.5 +2 1 +1.5 0.5 4Ω +1 0.2 % 0.625 W d B r 0.1 A 0.05 0.1 W +0.5 +0 -0.5 -1 0.02 -1.5 0.01 -2 -2.5 0.005 0.5 W -3 0.002 0.001 20 -3.5 50 100 200 500 1k 2k 5k 10k Hz Figure 36. THD+N vs. Frequency - HD Mode VBATT = 3.7 V DS909A2 8Ω 20k -4 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 37. Frequency Response- HD Mode 25 CS35L01/03 4.00 3.5 3.50 3.0 RL = 4 Ω 10% THD+N Ratio 3.00 2200 pF Output Power (W) Idle Current Draw (mA) 2.5 2.50 1000 pF 2.00 2.0 RL = 4 Ω 1% THD+N Ratio 1.5 1.50 1.0 RL = 8 Ω 10% THD+N Ratio 1.00 470 pF 0.50 0.5 RL = 8 Ω 1% THD+N Ratio No Filter 0.00 0.0 2.5 3 3.5 4 4.5 5 5.5 2.5 3.0 3.5 VBATT (V) 4.0 Figure 38. Idle Current Draw vs. VBATT - HD Mode RL = 8 Ω + 33 μH (Note 17) 5.0 5.5 Figure 39. Output Power vs. VBATT - HD Mode 100% 100% 90% 90% 80% 80% 4.2 V 3.7 V 5.0 V 70% 70% 60% 60% Efficiency (%) 3.7 V Efficiency (%) 4.5 VBATT Supply Voltage (V) 50% 50% 40% 40% 30% 30% 20% 20% 10% 10% 0% 5.0 V 4.2 V 0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 0 0.5 1 Output Power (W) 1.5 2 2.5 3 Output Power (W) Figure 40. Efficiency vs. Output Power - HD Mode RL = 8 Ω + 33 μH Figure 41. Efficiency vs. Output Power - HD Mode RL = 4 Ω + 33 μH 0.40 0.70 0.35 0.60 4.2 V 4.2 V 0.30 0.50 3.7 V Current Consumption (A) 3.7 V Supply Current (A) 0.25 5.0 V 0.20 0.15 5.0 V 0.40 0.30 0.20 0.10 0.10 0.05 0.00 0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W) Figure 42. Supply Current vs. Output Power - HD Mode RL = 8 Ω + 33 μH 0 0.5 1 1.5 2 2.5 3 Output Power (W) Figure 43. Supply Current vs. Output Power - HD Mode RL = 4 Ω + 33 μH Note: 17. “Idle Current Draw vs. VBATT - HD Mode” capacitor values refer to CFILT when configured as the “CS35L01/03’s Minimized Optional Output Filter”, shown in Figure 5 on page 17. When VBATT is below “VBATT Limit for HD/FHD Mode” (VBLIM), operation is restricted to SD Mode. 26 DS909A2 CS35L01/03 6.4 FHD Mode Typical Performance Plots 10 10 5 5 5.0 V 4.2 V 3.7 V 2 5.0 V 4.2 V 3.7 V 2 1 1 0.5 0.5 % % 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 0.01 1m 2 2m 5m 10m 20m 50m W 100m 200m 500m 1 2 3 W Figure 44. THD+N vs. Output Power - FHD Mode RL = 8 Ω Figure 45. THD+N vs. Output Power - FHD Mode RL = 4 Ω 10 10 5 5 1.0 W 2 0.75 W 2 1 1 0.5 0.5 % % 0.1 W 0.2 0.1 W 0.2 0.1 0.1 0.05 0.05 0.5 W 0.5 W 0.02 0.01 20 0.02 50 100 200 500 1k 2k 5k 10k 0.01 20 20k 50 100 200 500 Hz 1k 2k 5k 10k 20k Hz Figure 46. THD+N vs. Frequency - FHD Mode VBATT = 5.0 V Figure 47. THD+N vs. Frequency - FHD Mode VBATT = 4.2 V 10 +4 +3.5 5 +3 +2.5 0.625 W 2 +2 +1.5 1 4Ω +1 0.5 d B r % A 0.1 W 0.2 +0.5 +0 -0.5 -1 8Ω 0.1 -1.5 -2 0.05 -2.5 0.5 W -3 0.02 -3.5 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 48. THD+N vs. Frequency - FHD Mode VBATT = 3.7 V DS909A2 -4 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 49. Frequency Response - FHD Mode 27 CS35L01/03 3.5 4.00 3.50 3.0 RL = 4 Ω 10% THD+N Ratio 3.00 2.50 2200 pF Output Power (W) Idle Current Draw (mA) 2.5 1000 pF 2.00 2.0 RL = 4 Ω 1% THD+N Ratio 1.5 1.50 1.0 RL = 8 Ω 10% THD+N Ratio 1.00 470 pF 0.50 0.5 RL = 8 Ω 1% THD+N Ratio No Filter 0.0 0.00 2.5 3 3.5 4 4.5 5 2.5 5.5 3.0 3.5 4.0 Figure 50. Idle Current Draw vs. VBATT - FHD Mode RL = 8 Ω + 33 μH (Note 18) 5.0 5.5 Figure 51. Output Power vs. VBATT - FHD Mode 100% 100% 90% 90% 80% 80% 3.7 V 4.2 V 5.0 V 70% 70% 60% 60% 4.2 V Efficiency (%) 3.7 V Efficiency (%) 4.5 VBATT Supply Voltage (V) VBATT (V) 50% 50% 40% 40% 30% 30% 20% 20% 10% 10% 0% 5.0 V 0% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 0 0.5 1 Output Power (W) 1.5 2 2.5 3 Output Power (W) Figure 52. Efficiency vs. Output Power - FHD Mode RL = 8 Ω + 33 μH Figure 53. Efficiency vs. Output Power - FHD Mode RL = 4 Ω + 33 μH 0.40 0.70 0.35 0.60 4.2 V 4.2 V 0.30 0.50 3.7 V Current Consumption (A) Supply Current (A) 0.25 5.0 V 0.20 0.15 3.7 V 5.0 V 0.40 0.30 0.20 0.10 0.10 0.05 0.00 0.00 0 0.25 0.5 0.75 1 1.25 1.5 1.75 Output Power (W) Figure 54. Supply Current vs. Output Power - FHD Mode RL = 8 Ω + 33 μH 0 0.5 1 1.5 2 2.5 3 Output Power (W) Figure 55. Supply Current vs. Output Power - FHD Mode RL = 4 Ω + 33 μH Note: 18. “Idle Current Draw vs. VBATT - FHD Mode” capacitor values refer to CFILT when configured as the “CS35L01/03’s Minimized Optional Output Filtering” shown in Figure 5 on page 17. When VBATT is below “VBATT Limit for HD/FHD Mode” (VBLIM), operation is restricted to SD Mode. 28 DS909A2 CS35L01/03 7. PARAMETER DEFINITIONS Signal to Noise Ratio (SNR) The ratio of the RMS value of the output signal, where Pout is equivalent to the specified output power at THD+N<1%, to the RMS value of the noise floor with no input signal applied and measured over the specified bandwidth, typically 20 Hz to 20 kHz. This measurement technique has been accepted by the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Idle Channel Noise (ICN) Measure of the signal present on the outputs of the device when no audio signal is presented to the input pins. For this test, both input pins are shorted together, setting the differential signal to them to zero. DS909A2 29 CS35L01/03 8. PACKAGING AND THERMAL INFORMATION 8.1 Package Drawings and Dimensions (Note 19) 9 BALL WLCSP e Y e b 9 solder spheres X A2 A A1 DIM MIN X Y b e A A1 A2 0.047 0.047 0.009 0.018 0.006 0.012 INCHES NOM 0.048 0.048 0.011 0.015 0.020 0.007 0.013 NOTE MAX MIN MILLIMETERS NOM MAX 0.049 0.049 0.012 0.022 0.008 0.014 1.195 1.195 0.240 0.475 0.175 0.300 1.215 1.215 0.270 0.400 BSC 0.515 0.190 0.325 1.235 1.235 0.300 0.555 0.205 0.350 19 19 19 19 19 19 JEDEC #: MO-220 Controlling Dimension is Millimeters. Note: 19. Dimensioning and tolerance per ASME Y 14.5M-1994. 30 DS909A2 CS35L01/03 8.2 Recommend PCB Footprint and Routing Configuration To ensure high-yield manufacturability, the PCB footprint for the CS35L01/03 should be constructed with strict adherence to the specifications given in IPC-610. Departure from this specification significantly increases the probability of solder bridging and other manufacturing defects. Routing of the traces into and out of the CS35L01/03 device should also be given consideration to avoid manufacturing issues. 8.3 Package Thermal Performance Class-D amplifiers, though highly efficient, will produce some amount of heat through the process of amplifying the audio signal. As is well understood, this amount of heat is very small compared to traditional Class AB amplifiers. Even so, as power levels increase and package sizes decrease, careful consideration must be given to ensure thermal energy is removed from the device as efficiently as possible so that its operating temperature is kept under its Over-Temperature Error Threshold. The thermal impedance, θJA is a measurement of the impedance to the flow of thermal energy out of the device to the environment surrounding the device. This specification is directly related to the ability of the PCB to which the CS35L01/03 is attached to transfer the heat from the device. The thermal impedance from the junction of the device to the ambient surrounding the device and the thermal impedance from the device into the PCB is shown in Table 2. . Parameter (Note 20), (Note 21) Junction to Ambient Thermal Impedance Junction to Printed Circuit Board Thermal Impedance Symbol θA θPCB Min Typical Max Units - 92 - °C/Watt - 67 - °C/Watt Table 2. θJA Specification for Typical PCB Designs Note: 20. Test Printed Circuit Board Assembly (PCBA) constructed in accordance with JEDEC standard JESD51-9. Two signal, two plane (2s2p) PCB utilized. 21. Test conducted with still air in accordance with JEDEC standards JESD51, JESD51-2A, and JESD51-8. DS909A2 31 CS35L01/03 8.3.1 Determining Maximum Ambient Temperature To determine (to a first order approximation) the maximum ambient temperature in which the CS35L01/03 will operate, the following equations can be used: T op = θ JA × ( ( 1 – η ) × P max ) T max = T TE – T op Where: Tmax = The maximum ambient temperature in which the device can operate. Top = The operating temperature of the device, given a dissipated power “Pmax” and a known thermal impedance “θJA”. TTE = The Over-Temperature Error Threshold, given in the “Electrical Characteristics - All Operational Modes” section on page 9. θJA = The thermal impedance of the device and PCB. (This value is highly subjective to a number of application specific scenarios. The numbers given in Table 2 on page 31 can be used for a first order approximation, but proper characterization of the application’s specific PCB and supporting mechanicals is needed to increase the accuracy of the result achieved here.) Pmax = The maximum power at which the amplifier will be operated continuously. (For conservative estimates, the 10% THD+N rated power given in “Electrical Characteristics - SD Mode” section on page 10, “Electrical Characteristics - FSD Mode” section on page 11, “Electrical Characteristics - HD Mode” section on page 12, or “Electrical Characteristics - FHD Mode” section on page 13 can be used. However, this method will predict higher operating temperatures than what may be seen in the application, since power content of audio signals is much smaller than that of the sine wave used to establish the power specifications.) η = The efficiency of the device at the power Pmax. 32 DS909A2 CS35L01/03 9. ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order# CS35L01 2.9 W Mono Audio 9Yes Amplifier with default WLCSP +6 dB gain Commercial -10° to +70°C Tape and Reel CS35L01-CWZR CS35L03 2.9 W Mono Audio 9Yes Amplifier with default WLCSP +12 dB gain Commercial -10° to +70°C Tape and Reel CS35L03-CWZR 10.REVISION HISTORY Release A1 A2 Changes – – – – – – – – – – – – – – – – DS909A2 Initial Release Updated all output switching frequency references to fsw1 from 200 kHz to 192 kHz. Updated all output switching frequency references to fsw2 from 80 kHz to 76 kHz. Updated CS35L0x part number references to CS35L01/03. Updated front page title, features, and common applications. Updated front page block diagram. Updated package dimensions in Section 8. Packaging and thermal Information. Updated Section 3. Typical Connection Diagrams to show 10 μF and 0.1 μF power-supply decoupling capacitors. Reorganized location of individual specifications in electrical characteristics tables based on measured device performance in different operational modes (“Electrical Characteristics - All Operational Modes” on page 9, “Electrical Characteristics - SD Mode” on page 10, “Electrical Characteristics - FSD Mode” on page 11, “Electrical Characteristics - HD Mode” on page 12, and “Electrical Characteristics - FHD Mode” on page 13). The following specification changes have been made in “Electrical Characteristics - SD Mode” on page 10, “Electrical Characteristics - FSD Mode” on page 11, “Electrical Characteristics - HD Mode” on page 12, and “Electrical Characteristics - FHD Mode” on page 13: – Added “Common-Mode Rejection Ratio” test conditions (Vripple = 1 VPP and fripple = 217 Hz) – Updated “Signal to Noise Ratio” to be specified as A-Weighted – Updated “Idle Channel Noise” to be specified as both A-Weighted & Unweighted – Updated “Idle Current Draw” to be specified with no load at 3 voltages (5.0 V, 4.2 V, and 3.7 V) – Changed “Max Input Before Clipping specification to “Input Voltage @ 1 % THD+N” – Updated specification typical values for 1% Output Power, 10% Output Power, THD+N @ 1 W, SNR A-Weighted, Idle Channel Noise A-Weighted, Idle Channel Noise (unweighted), Frequency Response, Output Switching Frequency, Input Impedance, and Input Voltage @ 1% THD+N Updated “Operating Efficiency” to be specified with 8 Ω + 33 μH and 4 Ω + 33 μH in “Electrical Characteristics - All Operational Modes” on page 9. Modified “Power-Up Time” specification into “Start-Up Time” and “Zero Crossing Power-Up” and added a cross-reference in “Power-Up & Power-Down Characteristics” on page 14. Moved power-up and power-down timing specifications from “Electrical Characteristics - All Operational Modes” on page 9 to their own specification table, “Power-Up & Power-Down Characteristics” on page 14. Renamed “Thermal Error Wait Time (WTE)” to “Thermal Error Retry Time (RTE)” in “Electrical Characteristics - All Operational Modes” on page 9 and in Section 5.5 Over Temperature Protection and added (Note 10) Thermal Error cross reference from spec table to description section. Updated “Operating Efficiency” specification (η) in “Electrical Characteristics - All Operational Modes” on page 9. Updated “MOSFET On Resistance” specification (RDS(ON)) in “Electrical Characteristics - All Operational Modes” on page 9. 33 CS35L01/03 A2 – – – – – – – – – – – Updated “Shutdown Supply Current” specification (IA(SD)) in “Electrical Characteristics - All Operational Modes” on page 9. Added “MOSFET On Resistance” test conditions (Ibias = 0.5 A) in “Electrical Characteristics - All Operational Modes” on page 9. Section 5.1.1.1 SD Mode updated to remove references to edge rate control. Section 5.1.2.1 HD Mode updated to include fsw1 switching frequency and clarify the conditions under which radiated emissions gains occur. Added Section 6. Typical Performance Plots. Added Section 5.4 Power-Up and Power-Down. Modified “Input Level Threshold for HD/FHD Modes” to be split up into “Input Level for Entering LDO Operation in HD/FHD Modes” and “Input Level for Entering VBATT Operation in HD/FHD Modes” in “Electrical Characteristics - All Operational Modes” on page 9. Added “LDO Entry Time Delay” specification in “Electrical Characteristics - All Operational Modes” on page 9. Updated (Note 8) and added (Note 9) referring to the “Input Level Thresholds”. Updated Section 5.5 Over Temperature Protection functional description. Updated out of date specification names, symbols, and cross-references in multiple locations throughout the document. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. IMPORTANT NOTICE “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). 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