White Electronic Designs WV3DG72256V-AD2 PRELIMINARY 2GB – 2x128Mx72 SDRAM, REGISTERED FEATURES DESCRIPTION Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock The WV3DG72256V is a 2x128Mx72 synchronous DRAM module which consists of eighteen 256Mx4 stack SDRAM components (stacked from 128Mx4) in TSOP II package, two 18 bit Drive ICs for input control signal and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 168 pin DIMM multilayer FR4 Substrate. Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply Dual Rank * This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option 168 Pin DIMM JEDEC • PCB - AD2: 28.58mm (1.125”) TYP PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE# DQM0 January 2006 Rev. 0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 BACK DQM1 CS0# NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CLK0 VSS NC CS2# DQM2 DQM3 NC VCC NC NC CB2 CB3 VSS DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT DQ18 DQ19 VCC DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC WP SDA SCL VCC PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CAS# DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 BACK DQM5 CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC NC A12 VSS CKE0 CS3# DQM6 DQM7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 1 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PIN NAMES BACK DQ50 DQ51 VCC DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC A0 – A12 BA0-1 DQ0-63 CB0-7 CLK0 CKE0 CS0# - CS3# RAS# CAS# WE# DQM0-7 VCC VSS VREF REGE SDA SCL SA0-2 NC Address Input (Multiplexed) Select Bank Data Input/Output Check Bit (Data-In/Data-Out) Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Power Supply for Reference Register Enable Serial Data I/O Serial Clock Address in EEPROM No Connect * Pins not used in this module. White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* FUNCTIONAL BLOCK DIAGRAM BCS1#, B2CKE0 BCS0#, B0CKE0 PCLK0 B0RAS#, B0CAS#, B0WE#, B0BA0, B0BA1 B0A0~B0A12 BDQM0 DQ0~3 10 PCLK1 DQ0~7 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 BDQM4 DQ32~35 DQ0~11 10 PCLK3 DQ0~15 10 PCLK4 CB0~3 DQ36~39 BDQM2 DQ16~19 10 PCLK6 DQ20~23 10 PCLK7 BDQM3 DQ24~27 10 PCLK8 B1RAS#, B1CAS#, B1WE#, B1BA0, B1BA1 B1A0~B1A12 DQ28~31 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 10 BDQM5 DQ40~43 10 DQ44~47 10 DQ4~7 10 BCS3#, B3CKE0 BCS2, B1CKE0 PCLK5 CLK# CS1, CKE CTL Add DQM DQ0~3 10 10 PCLK2 CLK# CS0, CKE CTL Add DQM DQ0~3 10 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 CLK# CS1, CKE CTL Add DQM DQ0~3 CLK# CS0, CKE CTL Add DQM DQ0~3 BDQM6 DQ48~51 10 DQ52~55 10 DQ56~59 10 DQ60~63 10 VSS B0A3~B0A10, B0BA0 B1A3~B1A10, B1BA0 VCC CLK1,2,3 VCC 10 12pF 74ALVCF162835 CDCF2510 10k PCLK9 REGE LE OE# A11, A12, BA1 CS2#, CS3# CKE0 74ALVCF162835 DQM2, 3, 6, 7 LE RAS#, CAS#, WE# 74ALVCF162835 LE January 2006 Rev. 0 10 CLK FBIN 12pF B0A11, B0A12, B0BA1 B1A11, B1A12, B1BA1 BCS2, BCS3 B0CKE0, B1CKE0 B2CKE0,B3CKE0 DQM2, 3, 6, 7 FBOUT *1 Cb Note 1. The actual values of Cb will depend upon the PLL chosen. OE# A0, A1, A2 CS0#, CS1# DQM0, 1, 4, 5 CLK0,2,3 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 PCLK8 PCLK9 IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 G AGND AVCC A3~A10, BA0 B0A0, B0A1, B0BA2 B1A0, B1A1,B1BA2 B0RAS#, BCAS#, B0WE# B1RAS#, BCAS#, B1WE# BCS0, BCS1 DQM0, 1, 4, 5 Serial PD SCL WP 47K SDA A0 A1 A2 SA0 SA1 SA2 OE# 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 4.6 V TSTG -55 ~ +150 °C Power Dissipation PD 36 W Short Circuit Current IOS 50 mA Storage Temperature Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS Voltage Referenced to: VSS = 0V, 0°C ≤ TA ≤ 70° Parameter Symbol Min Typ Max Unit V Note Supply Voltage VCC 3.0 3.3 3.6 Input High Voltage VIH 2.0 3.0 VCCQ+0.3 V 1 Input Low Voltage VIL -0.3 — 0.8 V 2 Output High Voltage VOH 2.4 — — V IOH= -2mA Output Low Voltage VOL — — 0.4 V IOL= -2mA Input Leakage Current ILI -10 — 10 μA 3 Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE TA = 25 °C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV Parameter Symbol Max Unit Input Capacitance (A0-A12, BA0-BA1) CIN1 15 pF Input Capacitance (RAS#, CAS#, WE#) CIN2 15 pF Input Capacitance (CKE0) CIN3 15 pF Input Capacitance (CLK0) CIN4 20 pF Input Capacitance (CS0# - CS3#) CIN5 15 pF Input Capacitance (DQM0-DQM7) CIN6 15 pF Data input/output capacitance (DQ0-DQ63), (CB0-BC7) COUT 22 pF January 2006 Rev. 0 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* OPERATING CURRENT CHARACTERISTICS VCC = 3.3V, 0°C ≤ TA ≤ 70°C Parameters Operating Current (One bank active) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode Active standby current in power-down mode Symbol Versions Conditions ICC1 Burst Length = 1 tRC ≥ tRC(min) IOL = 0mA 133/100 2,520 Units Note mA 1 ICC2P CKE ≤ VIL(max), tCC = 10ns 530 mA ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 130 mA ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC =10ns Input signals are charged one time during 20 1,170 mA ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC= ∞ Input signals are stable 410 mA ICC3P CKE ≥ VIL(max), tCC = 10ns 670 mA ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 270 mA ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are charged one time during 20ns 1,530 mA ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ input signals are stable 950 mA 2,610 mA 1 4,590 mA 2 420 mA Active standby in current non powerdown mode Operating current (Burst mode) ICC4 Io = mA Page burst 4 Banks activated tCCD = 2CLK Refresh current ICC5 tRC ≥ tRC(min) Self refresh current ICC6 CKE ≤ 0.2V Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. January 2006 Rev. 0 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* AC OPERATING TEST CONDITIONS VCC = 3.3V, 0°C ≤ TA ≤ 70°C Parameter Value Units AC Input level (VIN/VIL) 2.4/0.4 V 1.4 V tr/tf = 1/1 ns 1.4 V Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V VTT=1.4V 1220 50 VOH (DC)=2.4V, IOH=-2mA VOL (DC)=2.4V, IOL=-2mA Output 870 Output Z0 = 50 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit AC OPERATING TEST CONDITIONS Parameter Value Symbol 133/100 Units Notes Row active to row active delay tRRD(MIN) 15 ns 1 RAS# to CAS# delay tRCD(MIN) 20 ns 1 Row Precharge time tRP(MIN) 20 ns 1 1 tRAS(MIN) 45 ns tRAS(MAX) 100 µs Row cycle time tRC(MIN) 65 ns 1 Last data in to row precharge tRDL(MIN) 2 CLK 2 Last data in to Active delay tDAL(MIN) 2 CLK + tRP — Last data in to new col. address delay tCDL(MIN) 1 CLK 1 Last data in to burst stop tBDL(MIN) 1 CLK 2 Col. address to col. address delay tCCD(MIN) 1 CLK 2 CAS Latency = 3 2 CLK 3 Cas Latency = 2 1 ea 4 Row active time Number of valid output data Notes: 1. The minimum number of clock cycles is determined by driving the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. January 2006 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* OPERATING AC PARAMETER 133/100 Parameter CLK cycle time CLK to valid output delay Output data hold time Symbol CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 CAS latency = 3 CAS latency = 2 Min 7.5 tCC – Max 1,000 5.4 tSAC – 3 tOH – Units Notes ns 1 ns 1, 2 ns 2 CLK high pulse width tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 1.5 ns 3 Input hold time tSH 0.8 ns 3 CLK to output in Low-z tSLZ 1 ns 2 CLK to output in Hi-z CAS latency = 3 CAS latency = 2 5.4 tHZ – ns Notes: 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr &tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr = tf)/2-1]ns should be added to the parameter. January 2006 Rev. 0 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* ORDERING INFORMATION FOR AD2 Part Number Clock Speed CAS Latency Height* WV3DG72256V10AD2xx 100MHz CL=2 28.58 (1.25”) TYP WV3DG72256V7AD2xx 133MHz CL=2 28.58 (1.25”) TYP WV3DG72256V75AD2xx 133MHz CL=3 28.58 (1.25”) TYP NOTES: • Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR AD2 133.350 5.250 2.000 0.079 0.157 ± 0.004 (4.000 ± 0.100) 17.780 0.700 3.000 0.118 28.575 TYP 1.125 1.372 0.054 127.350 5.014 3.00 0.118 8.890 0.350 6.350 0.250 11.430 (0.450) 2.540 Min 0.100 Min ? 118DIA ± 0.004 3.000DIA ± 0.100 6.350 0.250 36.830 1.450 54.64 2.150 115.57 4.550 0.165 Min 4.19 Min 8.86 Max (0.270 Max) 1.270±0.10 0.050±0.0039 * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) January 2006 Rev. 0 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* PART NUMBERING GUIDE WV 3 D G 72 256 V xx AD2 I- x G WEDC MEMORY SDRAM GOLD BUS WIDTH DEPTH 3.3 VOLTS CLOCK SPEED (MHz) 10 = 100MHz @ CL = 2 7 = 133MHz @ CL = 2 75 = 133MHz @ CL = 3 PACKAGE 168 PIN DIMM AD2: 28.58mm (1.125”) INDUSTRIAL TEMP COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT January 2006 Rev. 0 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WV3DG72256V-AD2 PRELIMINARY* Document Title 2GB- 2x128Mx72 SDRAM, REGISTERED Revision History Rev # History Release Date Status Rev 0 Created Data sheet January 2006 Advanced January 2006 Rev. 0 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com