ES5120
3 3/4 DIGIT A/D CONVERTER
１． GENERAL DESCRIPTION
The ES5120 is a 3 3/4 digit
measurement system which
combines integrating analog-to-digital converter, frequency counter,and
logic level tester in either 40-pin DIP package or 44-pin QFP
package ． The high level of integration permits ES5120-based
instruments to deliver
higher performance and more features while
actually reducing parts count.
With a maximum range of 3999 counts, the ES5120 provides
10 times greater resolution in the 200mV to 400mV range than
traditional 3 1/2 digit meters. An autozero cycle guarantees a
zero reading with a 0V input. CMOS Processing reduces analog
input bias current to only 1PA. Rollover error, the difference
in readings for equal magnitude but opposite polarity input
signals, is less than ±
1 Count. Differential reference inputs
permit ratiometric measurements for ohms or bridge transducer
applications.
The ES5120's frequency counter option simplifies design
of an instrument which is well suited to both analog and digital
troubleshooting : voltage, current, and resistance measurements
plus precise frequency measurements to 4 MHz (higher frequencies
can be measured with an external prescaler) and a simple logic
probe. The frequency counter will automatically adjust its range
to match the input frequency, over a four decade range.
ES5120
3 3/4 DIGIT A/D CONVERTER
Two logic level measurement inputs permit a ES5120-based
meter to function as a logic probe. When combined with external
level shifters, the ES5120 will display logic levels on the LCD
display and also turn on a piezoelectric buzzer when the measured
logic level is low.
Other ES5120 features simplify instrument design and reduce
parts count. On-chip decimal point drivers are included, as is a
low battery detection annunciator. A piezoelectric buzzer can be
controlled with an external switch or by the logic probe inputs.
Two oscillator options are provided : A crystal can be used if
high accuracy frequency measurements are desired, or a simple RC
option can be used for low-end instruments.
A 'peak reading hold' input allows the ES5120 to retain
the highest A-D or frequency reading. This feature is useful in
measuring motor starting current, maximum temperature, and
similar applications.
The ES5120 operates from a single 9V battery, with typical
power of 16mW. Packages include a 40-pin DIP and 44-pin Flat
Package.
ES5120
3 3/4 DIGIT A/D CONVERTER
２．FEATURES
■ Multiple-Function Measurement System
z Analog to digital Converter
z Frequency Counter
z Logic Probe
■ Frequency Counter
z Measures Input Frequency to 4 MHz
z Autoranging Over Four Decade Range
■ Logic Probe Inputs
z 2 LCD Annunciators
z Buzzer Drive (with Two Types of Buzzer Frequencies, 5 KHz
and 2.5KHz, for choice)
■ Peak Reading Hold with LCD Annunciator
■ 3 3/4 Digit(3999 Maximum) Resolution
■ Low Noise A-D Converter
z Differential Inputs, 1 pA Bias Current
z Differential Reference for Ratiometric Ohms
z On-Chip Voltage Reference, 60 ppM/℃ Drift
■ No External LCD Drivers Required
z Full 3 3/4 Digit Display
z Displays "OL" for Input Overrange
ES5120
3 3/4 DIGIT A/D CONVERTER
z Three Decimal Point and Polarity Drivers
z LCD Annunciator Drive
z Adjustable LCD Drive Voltage
■ Low Battery Detect with LCD Annunciator
■ On Chip Buzzer Driver and Control Input
■ Control Input Changes Full Scale Range by 10:1
■ Data Hold Input
■ Underrange and Overrange Outputs
■ Multiple Package Options
z 40-pin DIP Package
z 44-pin Flat Package
ES5120
3 3/4 DIGIT A/D CONVERTER
３．TYPICAL APPLICATION
0.1μF
ES5120
3 3/4 DIGIT A/D CONVERTER
４．FUNCTIONAL BLOCK DIAGRAM
ES5120
3 3/4 DIGIT A/D CONVERTER
５．PIN ASSIGNMENT
ES5120AQ
ES5120BQ
ES5120AZ
ES5120BZ
ES5120
3 3/4 DIGIT A/D CONVERTER
６．PIN DESCRIPTION AND FUNCTION
Pin No. Pin No.
(40-pin (44-pin Flat
Package) Package) Symbol Descrlption
1
40
L-E4
LCD segment drive for L("logic low"),polarity,and"e"segment of
most significant digit (MSD)
2
41
AGD4
LCD segment drive for"a","g",and"d"segments of MSD
3
42
BC4P3
LCD segment drive for"b"and"c"segments of MSD and decimal
point 3
4
43
HFE3
LCD segment drive for H("logic high"), and"f"and"e"segment of 3rd
LSD
5
44
AGD3
LCD segment drive for"a","g", and"d"segments of 3rd LSD
6
1
BC3P2
LCD segment drive for"b"and"c"segments of 3rd LSD and decimal
point 2.
7
2
OFE2
LCD segment driver for"overrange",and"f"and"e"segments of 2nd
LS
8
3
AGD2
LCD segment drive for"a","g",and"d"segments of 2nd LSD.
9
4
BC2P1
LCD segment drive for"b"and"c"segments of 2nd LSD and decimal
point 1.
10
5
PKFE1
LCD segment drive for "hold peak reading", and"f"and"e"segments
of LSD
11
6
AGD1
LCD segment drive for"a","g",and"d"segments of LSD.
ES5120
3 3/4 DIGIT A/D CONVERTER
Pin No. Pin No.
(40-pin (44-pin Flat Package) Package) Symbol Descrlption
12
7
BC1BT
LCD segment drive for"b"and"c"segments of LSD and "low
battery".
13
8
BP3
LCD backplane #3.
14
9
BP2
LCD backplane #2.
15
10
BP1
LCD backplane #1.
11
VDISP
Sets peak LCD drive signal : VPEAK=(V+)-VDISP may also be set to
compensate for temperature variation of LCD crystal threshold
voltage.(default: The VDISP pin is connected to DGND.)
16
12
DGND
Internal logic digital ground, the logic "O" level. Nominally 4.7V
below V＋
17
13
ANNUNC Square wave output at the backplane frequency, synchronized to
BP1 ANNUNC can be used to control display annunciators.
Connecting an LCD segment to ANNUNC turns it on; connecting it
to its backplane turns it off.
18
14
LOGIC
"Logic Mode" control input. When connected to V＋ the converter
is in logic mode. The LCD displays "OL" and the decimal point
inputs control the "high" and "low" annunciators. When the "low"
annunciator is on, the buzzer will also be on. When unconnected or
connected to DGND, the ES5120 is in the voltage frequency
measurement mode. This pin has a 5μA internal pulldown to
DGND.
ES5120
3 3/4 DIGIT A/D CONVERTER
Pin No. Pin No.
(40-pin (44-pin Flat
Package) Package) Symbol Descrlption
19
15
RANGE/
Dual-purpose input.In voltage mode:When connected to V＋; the
FREQ
FREQ integration time will be 200 counts instead of 2000
counts,and the LCD will display the analog input divided by 10. In
frequency mode, this pin is the frequency input. A digital signal
applied to this pin will be measured with a one second timebase.
There is an internal 5μA pulldown to DGND.
20
16
DP0/LO
Dual-purpose input. Decimal Point select input for voltage
measurements. In logic mode, connecting this pin to V＋ will turn
on "low" LCD segment. There is an internal 5μA pulldown to
DGND in volts mode only. Decimal point logic:
DP1
21
17
DP1/HI
DP0 Decimal Point Selected
0
0
None
0
1
DP1
1
0
DP2
1
1
Dp3
Dual-purpose input. Decimal Point select input for voltage
measurements. In logic mode, connecting this pin to V＋ will turn
on the "high" LCD segment. There is an internal 5μA pulldown to
DGND in volts mode only.
22
18
BUZOUT
Buzzer output. Audio frequency, 2.5K or 5.0K for choice
determined by chip bonding, output which drives a piezo buzzer.
ES5120
3 3/4 DIGIT A/D CONVERTER
Pin No. Pin No.
(40-pin (44-pin Flat
Package) Package) Symbol Descrlption
23
19
BUZIN
Buzzer control input. Connecting BUZIN to V＋ turns the buzzer
on. BUZIN is logically ORed(internally) with the "logic level low"
input. There is an internal 5μA pulldown to DGND.
24
20
FREQ/
Voltage or frequency measurement select input. When connected to
VOLTS
DGND, the a-d converter function is active. When connected to V
＋ the frequency counter function is active. This pin has an internal
5μA pulldown to DGND.
25
21
PKHOLD
Peak Hold input. When connected to V＋, the converter will only
update the display if a new conversion value is greater than the
preceeding value. Thus, the peak reading will be stored and held
indefinitely. When unconnected or connected to DGND, the
converter will operate normally. This pin has an internal 5μA
pulldown to DGND.
(Note : This pin may be with the function of EOC/HOLD which
depends on chip bonding.)
22
UR
Underrange output. This output will be high when the digital
reading is 380 counts or less.
23
OR
Overrange output. This output will be high when the analog signal
input is greater than full scale. The LCD will display "OL" when
the input is overranged.
ES5120
3 3/4 DIGIT A/D CONVERTER
Pin No. Pin No.
(40-pin (44-pin Flat
Package) Package) Symbol Descrlption
26
24
V-
Negative supply connection. Connect to negative terminal of 9V
battery.
27
25
COM
Analog circuit ground reference point. Nominally 3.3V below V＋.
28
26
CREF+
Positive connection for reference capacitor.
29
27
CREF-
Negative connection for reference capacitor.
30
28
VREF+
High differential reference input connection.
31
29
VREF-
Low differential reference input connection.
32
30
VIN-
Low analog input signal connection.
33
31
VIN+
High analog input signal connection.
34
32
VBUFF
Buffer output. Connect to integration resistor.
35
33
CAZ
Autozero capacitor connection.
36
34
VINT
Integrator output. Connect to integration capacitor.
35
EOC/
Bidirectional pin. Pulses low (i.e. from V+ to DGND) at the end of
HOLD
each conversion. If connected to V+, conversions will continue but
the display is not updated.
37
36
OSC1
Crystal oscillator (input) connection.
38
37
OSC2
Crystal oscillator (output) connection.
39
38
OSC3
RC oscillator connection.
40
39
V+
Positive power supply connection. Typically 9V.
ES5120
3 3/4 DIGIT A/D CONVERTER
７．ABSOLUTE MAXIMUM RATING
Characteristic
Supply Voltage (V+ to V-)
Rating
12 V
Analog Input Voltage (either input)
V+ to V-
Reference Input Voltage (either input)
V+ to V-
Digital Inputs
Power Dissipation (plastic package)
Operating Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec)
DGND to V+
800 mW
0℃ to +70℃
-65℃ to +160℃
270℃
※ Note：There are ten pins for Analog section, such as COM, CREF+,CREF-,
VREF+, VREF-, VIN+, VIN-, VBUFF, CAZ, and VINT and the others are related to
Digital section.
ES5120
3 3/4 DIGIT A/D CONVERTER
８．ELECTRICAL CHARACTER ISTICS
At V+=9V，fosc 40KHZ，TA=25℃ unless otherwise noted
Characteristic
Test Conditions
Limit
Zero Input Reading
-000.0
±000.0
+000.0
VIN＝0.0V
Full-Scale=400.0mV
Ratiometric
1999
1999/
2000
VIN=VREF
Reading
2000
VREF=200mV
Linearity
Full-Scale=400mV
-1
1
± 0.2
(Max. deviation from
best straight line
fit)
Roll-over Error
-VIN=+VIN=390.0mV
-1
+1
± 0.2
Common Mode
50
VCM=± 1V, VIN=0V
－
－
Rejection Ratio
Full-Scale=400.0mV
Noise
VIN=0V,
15
－
－
Full-Scale=400.0mV
0.2
1
Zero Reading
VIN=0V
－
Drift
0℃≦TA≦70℃
Scale Factor
1
5
VIN=399.0mV
－
Temperature
0℃≦TA≦70℃(Ext.
Coefficient
Ref.= 0 ppm/℃
Analog COMMON Voltage 25KΩ between
3.15
3.3
3.45
+
(with respect to V )
Common and Positive
Supply
Analog COMMON
30
50
25KΩ between
－
+
Temperature
Common and V
Coefficient
0℃≦TA≦70℃
Back plane Drive
4.5
5.0
5.5
V+ to V-＝9V
Voltage(Peak To Peak)
Supply Current (Does
1.2
1.7
VIN＝0V
－
not include COMMON
current)
Units
Digital
Reading
Digital
Reading
Counts
Counts
μV/V
μVp-p
μV/℃
ppm/℃
V
ppm/℃
V
mA
ES5120
3 3/4 DIGIT A/D CONVERTER
ELECTRICAL CHARACTERISTICS (contd.)
Limit
Characteristic
Test Conditions
Min.
Typ.
Max.
5.0/2.5
Buzzer Freguency
fosc = 40.0 KHz
*1
Counter Timebase
fosc = 40.0 KHz
1
Units
KHz
second
Period
Low Battery
V+ to V-
6.7
7.0
7.3
V
Flag Voltage
Control pin
μA
5
Pulldown Current
Note 1:Two types of Buzzer Frequencies for choice determined by chip bonding.
Limit
Characteristic
Test Conditions
Units
Min.
Typ.
Max.
－
Input Low Voltage
－
DGND
V
+1.5V
Input High Voltage
V+
－
－
V
－
DGND
V
-1.5V
Output, Low Voltage
1L=50uA
－
UR、OR、Outputs
Output High Voltage
UR、OR Outputs
+0.4V
1N=50uA
V+
-1.5V
－
－
V
ES5120
3 3/4 DIGIT A/D CONVERTER
９．TEST CIRCUIT
9.1
General Function Test
ES5120
0.1μF
ES5120
3 3/4 DIGIT A/D CONVERTER
9.2
ICCQ Test
0.1u
ES5120
ES5120
3 3/4 DIGIT A/D CONVERTER
１０．ERAL THEORY OF OPERATION
10.1
Analog Section :
In
addition
to
the
basic
dual slope phases discussed
integrate
and
above, the
deintegrate
ES5120 design
incorporates an "Auto Zero" phase. The additional phase
ensure that the integrator starts
at
zero
volts
(even
after a severe over-range conversion) and that all offset
voltage errors (buffer amplifier, integrator and comparator) are
removed
from
the
conversion. A true digital
zero reading is assured without any external adjustments.
A complete conversion consists of four distinct phases :
(1) Auto Zero Phase
(2) Signal Integrate Phase
(3) Reference Deintegrate Phase
(4) ADC SYSTEM Timing
(1) Auto Zero Phase
During the Auto Zero phase, the differential input signal is
disconnected from the measurement circuit by opening
internal analog switches and the internal nodes are shorted
to Analog Common (0 volt ref.) to establish a zero input
condition. Additional analog switches close a feedback
loop around the integrator and comparator to permit
ES5120
3 3/4 DIGIT A/D CONVERTER
comparator offset voltage error compensation. A voltage
established on CAZ then compensates for internal device
offset voltages during the measurement cycle.
The Auto Zero phase residual is typically 10 to 15μA.
(2) Signal Integration Phase
Upon completion of the Auto Zero phase, the Auto Zero
loop is opened and the internal differential inputs connect
to VIN
+
and VIN-. The differential input signal is then
integrated for a fixed time period, which in the ES5120 is
2000 counts (4000 clock periods). The externally set clock
frequency is divided by two before clocking the internal
counters. The integration time period is :
4000
TINT＝―――― ＝ 2000 Counts
fosc
The differential input voltage must be within the device
common-mode range when the converter and measured
system share the same power supply common (ground). If
the converter and measured system do not share the same
power supply common as in battery powered applications,
VIN- should be tied to Analog Common.
Polarity is determined at the end of signal integration phase.
The sign bit is a "true polarity" indication in that signals
less than 1 LSB are correctly determined. This allows
precision null detection which is limited only by device
noise and Auto Zero residual offsets.
ES5120
3 3/4 DIGIT A/D CONVERTER
(3) Reference Integrate (Deintegrate) Phase
The reference capacitor, which was charged during the
Auto Zero phase, is connected to the input of the
integrating amplifier. The internal sign logic ensures that
the polarity of the reference voltage is always connected in
the phase which is opposite to that of the input voltage.
This causes the integrator to ramp back to zero at a constant
rate which is determined by the reference potential.
The amount of time required (TDEINT) for the integrating
amplifier to reach zero is directly proportional to the
amplitude of the voltage that was put on the integrating
capacitor (VINT) during the integration phase :
TDEINT =
RINT CINT VINT
VREF
The digital reading displayed is :
Digital Count ＝ 2000 VIN + VIN −
VREF
(4) ADC System Timing
The oscillator frequency is divided by 2 prior to clocking
the internal decade counters. Each phase of the
measurement cycle has the following length :
Auto Zero
: 1999 to 5999 counts
Signal Integrate
: 2000 counts
Deintegrate
: 1 to 4001 counts
ES5120
3 3/4 DIGIT A/D CONVERTER
10.2
Frequency counter theory of Operation :
In addition to serving as an analog to digital converter, the
ES5120 internal counter can also function as a frequency
counter, (Figure 5). In the counter mode,
pulses at the RANGE/FREQ input will be counted and
displayed.
The ES5120 frequency counter derives its timebase from the
colck oscillator. The counter time base is :
Tcounter =
4,000,000
Fosc
Thus, the counter will operate with a 1 second timebase when
a 40 kHz oscillator is used. The frequency counter accuracy is
determined by the oscillator
ES5120
3 3/4 DIGIT A/D CONVERTER
accuracy. For accurate frequency measurements, a crystal
oscillator is recommended.
The frequency counter will automatically select the proper
range. Autorange operation extends over four decades, from
3.999 kHz to 3.999 MHz. Decimal points are set automatically
in the frequency mode, (Figure 6).
The logic switching levels of the RANGE/FREQ input are
CMOS levels. For best counter operation, an external buffer is
recommended.
ES5120
3 3/4 DIGIT A/D CONVERTER
10.3
Logic Probe Theory of Operation :
This mode is selected when the LOGIC input is high. Two
dual purpose pins, which normally control the decimal points,
are used as logic inputs. Connecting either input to a logic
high level will turn on the corresponding LCD annunciator,
Also when the "low" annunciator is on the buzzer will be on.
As with the Frequency Counter input, external level
shifters/buffers are recommended for the logic probe inputs.
(Fig.7)
ES5120
3 3/4 DIGIT A/D CONVERTER
When
the
logic
probe
function
is
selected
while
FREQ/VOLTS is low (A/D mode). the analog to digital
converter will remain in the autozero mode. The LCD display
will read "OL" and all decimal points will be off. (Fig. 6 Display)
If the logic probe is active while FREQ/VOLTS is high
(counter mode) the frequency counter will continue to operate.
The display will read "OL" but the decimal points will be
visible. If the logic probe input is also connected to the
RANGE/FREQ input, then bringing the LOGIC input low will
immediately display the frequency at the logic probe input.
ES5120
3 3/4 DIGIT A/D CONVERTER
10.4
Selection of operating Mode
The operating modes are selected with the functional control
inputs. The control input truth table is shown in Table 1.
Table 1.
Control Input Truth Table
Logic Input
Function
FREQ/VOLTS RANGE/FREQ LOGIC
×
×
1
Logic Probe
○
○
○
A/D Converter,Vfullscale=2*VREF
○
1
○
A/D Converter,Vfullscale=20*VREF
○
Frequency Counter
1
Freguency
Counter
Input
Note ＝ Logic "０" ＝ DGND
Logic "１" ＝ V+
ES5120
3 3/4 DIGIT A/D CONVERTER
10.5
LCD Display
The ES5120 drives a triplex (multiplexed 3:1) liquid crystal
display with three backplanes. The LCD display can include
decimal points, polarity sign, and annuciators for overrange,
peak hold, high and low logic levels, and low battery Fig. 8
shows the assignment of the display segments to the
backplanes and the segment drive lines. The back plane drive
frequency is obtained by dividing the oscillator frequency by
240.
40-pin DIP
Pin No
44-pin QFP
Pin No
1
40
2
41
A4
G4
D4
3
42
B4
C4
DP3
4
43
HIGH
F3
E3
5
44
A3
G3
D3
6
1
B3
C3
DP2
7
2
OVER
F2
E2
8
3
A2
G2
D2
9
4
B2
C2
DP1
10
5
PEAK
F1
E1
11
6
A1
G1
D1
12
7
B1
C1
BATT
13
8
14
9
15
10
BP1
BP2
Low 〝―〞
BP3
E4
BP3
BP2
BP1
Fig. 8 LCD Backplane and Segment Assignments
ES5120
3 3/4 DIGIT A/D CONVERTER
Backplane waveform are shown in Fig. 9. These appear on
output BP1, BP2, and BP3. They remain the same regardless
of the segments being driving.
Other display output lines have waveforms that vary
depending on the displays values. Fig. 10 shows a set of
waveforms for the AGD outputs of one digit for several
combinations of "ON" segments.
ES5120
3 3/4 DIGIT A/D CONVERTER
１１．包裝(Package)
44-pin QFP package
ES5120
3 3/4 DIGIT A/D CONVERTER
40-pin DIP package