TC820
3-3/4 Digit A/D Converter with Frequency Counter
and Logic Probe
Features
General Description
• Multiple Analog Measurement System
- Digit A/D Converter
- Frequency Counter
- Logic Probe
• Low Noise A/D Converter:
- Differential Inputs: (1pA Bias Current)
- On-Chip 50ppm/°C Voltage Reference
• Frequency Counter:
- 4MHz Maximum Input Frequency
- Auto-Ranging Over Four Decade Range
• Logic Probe:
- Two LCD Annunciators
- Buzzer Driver
• 3-3/4 Digit Display with Over Range Indicator
• LCD Display Driver with Built-in Contrast Control
• Data Hold Input for Comparison Measurements
• Low Battery Detect with LCD Annunciator
• Under Range and Over Range Outputs
• On-Chip Buzzer Driver with Control Input
• 40-Pin Plastic DIP, 44-Pin Plastic Flat Pack, or
44-Pin PLCC Packages
The TC820 is a 3-3/4 digit, multi-measurement system
especially suited for use in portable instruments. It integrates a dual slope A/D converter, auto-ranging frequency counter and logic probe into a single 44-pin
surface mount, or 40-pin through hole package. The
TC820 operates from a single 9V input voltage (battery) and features a built-in battery low flag. Function
and decimal point selection are accomplished with simple logic inputs designed for direct connection to an
external microcontroller or rotary switch.
Device Selection Table
Part
Number
Resolution
Package
Operating
Temp. Range
TC820CPL
3-3/4 Digits
40-Pin PDIP
0°C to +70°C
TC820CKW
3-3/4 Digits
44-Pin PQFP
0°C to +70°C
TC820CLW
3-3/4 Digits
44-Pin PLCC
0°C to +70°C
2002 Microchip Technology Inc.
DS21476B-page 1
TC820
Package Type
L-E4
VDD
OSC3
OSC2
OSC1
EOC/HOLD
VINT
5
BC4P3
HFE3
6
AGD4
AGD3
44-Pin PLCC
4
3
2
1
44
43
42
41
40
BC3P2
7
39 CAZ
OFE2
8
38 VBUFF
AGD2
9
37 VIN+
BC2P1 10
36 VIN-
PKFE1 11
35 VREF-
TC820CLW
AGD1 12
34 VREF+
BP1BT 13
33 CREF-
BP3 14
32 CREF+
BP2 15
31 COM
BP1 16
30 VSS
VDISP 17
20
21 22
23
24
25
26
27
28
LOGIC
RANGE/FREQ
DP0/LO
DP1/HI
BUZOUT
BUZIN
FREQ/VOLTS
PKHOLD
UR
DGND
18 19
ANNUNC
29 OR
HFE3
BC4P3
AGD4
VDD
OSC3
OSC2
OSC1
EOC/HOLD
VINT
44 43
42
41 40 39
38
37
36
35
34
L–E4
Segments L-E4
1
40 VDD
Segments AGD4
2
39
Segments BC4P3
3
38 OSC2
Segments HFE3
4
37 OSC1
Segments AGD3
5
36 VINT
Segments BC3P2
6
35 CAZ
Segments OFE2
7
34 VBUFF
Segments AGD2
8
33 VIN+
Segments BC2P1
9
Segments PKFE1 10
44-Pin PQFP
AGD3
40-Pin PDIP
33 CAZ
BC3P2 1
Segments BC1BT 12
29 CREF-
BP3 13
28 CREF+
BP2 14
27 COM
BP1 15
26 VSS
AGD2 3
31 VIN+
ANNUNC 17
BC2P1 4
30 VIN-
LOGIC 18
PKFE1 5
29 VREF-
RANGE/FREQ 19
28 VREF+
DP0/LO 20
BC1BT 7
27 CREF-
BP3 8
26 CREF+
BP2 9
25 COM
BP1 10
24 VSS
VDISP 11
31 VREF30 VREF+
32 VBUFF
AGD1 6
32 VIN-
TC820CPL
Segments AGD1 11
OFE2 2
TC820CKW
OSC3
DGND 16
25 PKHOLD
24 FREQ/VOLTS
23 BUZIN
22 BUZOUT
21 DP1/HI
20
21 22
FREQ/VOLTS
PKHOLD
UR
19
BUZIN
RANGE/FREQ
18
BUZOUT
LOGIC
DS21476B-page 2
17
DP1/HI
15 16
DP0/LO
14
ANNUNC
12 13
DGND
23 OR
2002 Microchip Technology Inc.
TC820
Typical Applications
Triplex LCD
Logic High
Over Range
PKHold
Low Batt
Logic Low
Annunciator Drive
EOC
Under Range
Over Range
Analog Input
Low Drift Voltage
Differential
Reference
Clock
Oscillator
Triple LCD
Drivers
3-3/4 Digit A/D
Converter
Decimal
Point
Drivers
Peak Hold
Comparator
Decimal
Point
Select
Analog GND
Full Scale Select
Frequency Input
Logic Probe
Input
Low
Battery
Detect
TC820
Auto-Ranging
Frequency
Counter
Buzzer
Driver
Buzzer
Control
Function
Select
To LCD
and Buzzer
Logic Probe
Volts
Frequency
Logic
Function
Select
Digital Ground
+
9V
Peak
Hold
CREF+
CREF- VBUFF
CAZ
VINT OSC1
OSC2
OSC3
BUZIN
Logic
Low
VIN+
Buzzer
Driver
÷8
÷2
VIN-
Range/
Frequency
Frequency Counter Input
VREF+
A/D Counter Select
VREF-
Frequency/
Volts
Range
Common
Low
Batt
Detect
VDD
SEL
B
To LCD
A/D Counter
(3999 Counts)
A
A/D Control
TC820
Comparator
A>B
DEINT
Under Range
Over Range
EOC
Range
Display
Latch
Logic
Low
Range Frequency
Input
Low Batt
Logic
DP0/LO
Triples
Drivers
VSS
DP1/HI
15
DGND UR OR
2002 Microchip Technology Inc.
EOC/
HOLD
PEAK
HOLD
ANNUNC
VDISP
SEG0 • • • BP3
DS21476B-page 3
TC820
1.0
ELECTRICAL
CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Absolute Maximum Ratings*
Supply Voltage (V DD to GND) ................................ 15V
Analog Input Voltage:
(Either Input) (Note 1) ............................ VDD to VSS
Reference Input Voltage (Either Input) ....... VDD to VSS
Digital Inputs........................................... VDD to DGND
VDISP ....................................... VDD to (DGND – 0.3V)
Package Power Dissipation (TA – 70°C) (Note 2):
40-Pin Plastic DIP ......................................... 1.23W
44-Pin PLCC ..................................................1.23W
44-Pin Plastic Flat Package (PQFP) ..............1.00W
Operating Temperature Range:
"C" Devices ......................................... 0°C to +70°C
"E" Devices.......................................-40°C to +85°C
Storage Temperature Range .............. -65°C to +150°C
TC820 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VS = 9V, TA = 25°C, unless otherwise specified.
Symbol
Parameter
Zero Input Reading
Min
Typ
Max
Units
Test Conditions
-000
±000
+000
Digital
Reading
VIN = 0V
Full Scale = 400mV
RE
Rollover Error
-1
±0.2
+1
Counts
VIN = ±390mV
Full Scale = 400mV
NL
Nonlinearity
(Maximum Deviation From Best
Straight Line Fit)
-1
±0.2
+1
Count
Full Scale = 400mV
1999
1999/2000
2000
—
VIN = VREF, TC820
50
—
µV/V
Ratiometric Reading
CMRR
Common Mode Rejection Ratio
—
VCMR
Common Mode Voltage Range
VSS + 1.5
—
VDD – 1
eN
Noise (P-P Value Not
Exceeded 95% of Time)
—
15
—
IIN
Input Leakage Current
VCOM
Analog Common Voltage
VCTC
Common Voltage Temperature
Coefficient
VCM = ±1V, VIN = 0V
Full Scale = 400mV
(VFS = 200mV)
Input High, Input Low
µV
VIN = 0V
Full Scale = 400mV
—
—
—
—
VIN = 0V
—
1
10
pA
TA = 25°C
—
20
—
pA
0°C ≤ TA ≤ +70°C
—
100
—
pA
-40°C ≤ TA ≤ +85°C
3.15
3.3
3.45
V
25kΩ between Common and
VDD (VSS - VCOM)
—
—
—
—
25kΩ Between Common and
VDD
—
35
50
ppm/°C
—
50
—
—
0°C ≤ TA ≤ +70°C
-40°C ≤ TA ≤ +85°C
Note 1: Input voltages may exceed the supply voltages provided that input current is limited to ±100µA. Current above this value
may result in invalid display readings, but will not destroy the device if limited to ±1mA.
2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
DS21476B-page 4
2002 Microchip Technology Inc.
TC820
TC820 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VS = 9V, TA = 25°C, unless otherwise specified.
Symbol
TCZS
TCFS
IS
Parameter
Zero Reading Drift
Scale Factor Temperature
Coefficient
Supply Current
Peak-to-Peak Backplane
Drive Voltage
Min
Typ
Max
Units
Test Conditions
—
—
—
—
VIN = 0V
—
0.2
—
—
0°C ≤ TA ≤ +70°C
—
1
—
—
-40°C ≤ TA ≤ +85°C
—
—
—
—
—
1
5
ppm/°C
0°C ≤ TA ≤ +70°C
—
5
—
ppm/°C
-40°C ≤ TA ≤ +85°C
Ext Ref = 0ppm/°C
—
1
1.5
mA
4.25
4.7
5.3
V
VIN = 399mV
VIN = 0V
VS = 9V
VDISP = DGND
Buzzer Frequency
—
5
—
kHz
FOSC = 40kHz
Counter TIme-Base Period
—
1
—
Second
FOSC = 40kHz
VDD to VSS
Low Battery Flag Voltage
6.7
7
7.3
V
VIL
Input Low Voltage
—
—
DGND + 1.5
V
VIH
Input High Voltage
VDD – 1.5
—
—
V
VOL
Output Low Voltage,
UR, OR Outputs
VDD – 1.5
—
DGND + 0.4
V
IL = 50µA
—
5
—
µA
VIN = VDD
Control Pin Pull-down Current
Note 1: Input voltages may exceed the supply voltages provided that input current is limited to ±100µA. Current above this value
may result in invalid display readings, but will not destroy the device if limited to ±1mA.
2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.
2002 Microchip Technology Inc.
DS21476B-page 5
TC820
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number Pin Number
(40-PDIP)
(44-PQFP)
Symbol
L-E4
Description
1
40
LCD segment driver for L ("logic LOW"), polarity, and "e" segment of most significant
digit (MSD).
2
41
AGD4
LCD segment drive for "a," "g," and "d" segments of MSD.
3
42
BC4P3
LCD segment drive for "b" and "c" segments of MSD and decimal point 3.
4
43
HFE3
LCD segment drive for H ("logic HIGH"), and "f" and "e" segments of third LSD.
5
44
AGD3
LCD segment drive for "a," "g," and "d" segments of third LSD.
6
1
BC3P2
LCD segment drive for "b" and "c" segments of third LSD and decimal point 2.
7
2
OFE2
LCD segment drive for "over range," and "f" and "e" segments of second LSD.
8
3
AGD2
LCD segment drive for "a," "g," and "d" segments of second LSD.
9
4
BC2P1
LCD segment drive for "b " and "c" segments of second LSD and decimal point 1.
10
5
PKFE1
LCD segment drive for "hold peak reading," and "f" and "e" segments of LSD.
11
6
AGD1
LCD segment drive for "a," "g," and "d" segments of LSD.
12
7
BC1BT
13
8
BP3
LCD segment drive for "b" and "c" segments of LSD and "low battery."
LCD backplane #3.
14
9
BP2
LCD backplane #2.
15
10
BP1
LCD backplane #1.
—
11
VDISP
Sets peak LCD drive signal: VPEAK = (VDD ) – VDISP. VDISP may also be used to
compensate for temperature variation of LCD crystal threshold voltage.
DGND
Internal logic digital ground, the logic "0" level. Nominally 4.7V below VDD .
16
12
17
13
18
14
LOGIC
19
15
RANGE/
FREQ
Dual purpose input. In Range mode, when connected to VDD , the integration time
will be 200 counts instead of 2000 counts
20
16
DP0/LO
Dual purpose input. Decimal point select input for voltage measurements. In logic mode,
connecting this pin to VDD will turn on the "low" LCD segment. There is an internal 5µA
pull-down to DGND in Volts mode only. Decimal point logic:
ANNUNC Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC can be
used to control display annunciators. Connecting an LCD segment to ANNUNC turns it
on; connecting it to its backplane turns it off.
Logic mode control input. When connected to VDD, the converter is in Logic mode. The
LCD displays "OL" and the decimal point inputs control the HIGH and LOW annunciators.
When the "low" annunciator is on, the buzzer will also be on. When unconnected or connected to DGND, the TC820 is in the Voltage/Frequency Measurement mode. This pin
has a 5µA internal pull-down to DGND.
DP1
0
0
1
1
Decimal Point Selected
None
DP1
DP2
DP3
21
17
22
18
23
19
BUZIN
Buzzer control input. Connecting BUZIN to VDD turns the buzzer on. BUZIN is logically
OR’ed (internally) with the "logic level low" input. There is an internal 5µA pull-down to
DGND.
24
20
FREQ/
VOLTS
Voltage or frequency measurement select input. When unconnected, or connected
VOLTS to DGND, the A/D converter function is active. When connected to VDD , the
frequency counter function is active. This pin has an internal 5µA pull-down to DGND.
DS21476B-page 6
DP1/HI
DPQ
0
1
0
1
Dual purpose input. Decimal point select input for voltage measurements. In Logic mode,
connecting this pin to VDD will turn on the "high" LCD segment. There is an internal 5µA
pull-down to DGND in Volts mode only.
BUZOUT Buzzer output. Audio frequency, 5kHz, output which drives a piezoelectric buzzer.
2002 Microchip Technology Inc.
TC820
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Number
(40-PDIP)
(44-PQFP)
Symbol
Description
Peak hold input. When connected to VDD , the converter will only update the display if a
new conversion value is greater than the preceding value. Thus, the peak reading will be
stored and held indefinitely. When unconnected, or connected to DGND, the converter
will operate normally. This pin has an internal 5µA pull-down to DGND.
25
21
PKHOLD
—
22
UR
Under range output. This output will be HIGH when the digital reading is 380
counts or less.
—
23
OR
Over range output. This output will be HIGH when the analog signal input is greater
than full scale. The LCD will display "OL" when the input is over ranged.
Negative supply connection. Connect to negative terminal of 9V battery.
26
24
VSS
27
25
COM
Analog circuit ground reference point. Nominally 3.3V below VDD .
28
26
CREF+
Positive connection for reference capacitor.
29
27
CREF-
Negative connection for reference capacitor.
30
28
VREF+
High differential reference input connection.
31
29
VREF-
Low differential reference input connection.
32
30
VIN-
Low analog input signal connection.
33
31
VIN +
34
32
VBUFF
35
33
CAZ
Auto-zero capacitor connection.
36
34
VINT
Integrator output. Connect to integration capacitor.
—
35
EOC/
HOLD
Bi-directional pin. Pulses low (i.e., from VDD to DGND) at the end of each conversion. If
connected to VDD, conversions will continue, but the display is not updated.
37
36
OSC1
Crystal oscillator (input) connection.
38
37
OSC2
Crystal oscillator (output) connection.
39
38
OSC3
RC oscillator connection.
40
39
VDD
2002 Microchip Technology Inc.
High analog input signal connection.
Buffer output. Connect to integration resistor.
LCD segment drive for "a," "g," and "d" segments of MSD.
DS21476B-page 7
TC820
3.0
DETAILED DESCRIPTION
The TC820 is a 3-3/4 digit measurement system combining an integrating analog-to-digital converter, frequency counter, and logic level tester in a single
package. The TC820 supersedes the TC7106 in new
designs by improving performance and reducing system cost. The TC820 adds features that are difficult,
expensive, or impossible to provide with older A/D converters (see Table 3-1). The high level of integration
permits TC820 based instruments to deliver higher performance and more features, while actually reducing
parts count. Fabricated in low power CMOS, the TC820
directly drives a 3-3/4 digit (3999 maximum) LCD.
With a maximum range of 3999 counts, the TC820 provides 10 times greater resolution in the 200mV to
400mV range than traditional 3-1/2 digit meters. An
auto-zero cycle ensures a zero reading with a 0V input.
CMOS processing reduces analog input bias current to
only 1pA. Rollover error (the difference in readings for
equal magnitude but opposite polarity input signals) is
less than ±1 count. Differential reference inputs permit
ratiometric measurements for ohms or bridge transducer applications.
The TC820's frequency counter option simplifies
design of an instrument well-suited to both analog and
digital troubleshooting: voltage, current, and resistance
measurements, plus precise frequency measurements
to 4MHz (higher frequencies can be measured with an
external prescaler), and a simple logic probe. The frequency counter will automatically adjust its range to
match the input frequency, over a four-decade range.
Two logic level measurement inputs permit a TC820
based meter to function as a logic probe. When combined with external level shifters, the TC820 will display
logic levels on the LCD and also turn on a piezoelectric
buzzer when the measured logic level is low.
Other TC820 features simplify instrument design and
reduce parts count. On-chip decimal point drivers are
included, as is a low battery detection annunciator. A
piezoelectric buzzer can be controlled with an external
switch or by the logic probe inputs. Two oscillator
options are provided: a crystal can be used if high accuracy frequency measurements are desired, or a simple
RC option can be used for low-end instruments.
A "peak reading hold" input allows the TC820 to retain
the highest A/D or frequency reading. This feature is
useful in measuring motor starting current, maximum
temperature, and similar applications.
TABLE 3-1:
COMPETITIVE EVALUATION
Features Comparison
TC820
7106
3-3/4 Digit Resolution
Yes
No
Auto-Ranging Frequency
Counter
Yes
No
Logic Probe
Yes
No
Decimal Point Drive
Yes
No
Peak Reading Hold
(Frequency or Voltage)
Yes
No
Display Hold
Yes
No
Simple 10:1 Range Change
Yes
No
Buzzer Drive
Yes
No
Low Battery Detection
with Annunciator
Yes
No
Over Range Detection
with Annunciator
Yes
No
Low Drift Reference
Yes
No
Under Range/Over Range
Logic Output
Yes
No
Input Overload Display
"OL"
"1"
LCD Annunciator Driver
Yes
No
Triplexed
Direct
LCD Pin Connections
15
24
LCD Elements
36
23
LCD Drive Type
3.1
General Theory of Operation
3.1.1
DUAL SLOPE CONVERSION
PRINCIPLES
The TC820 analog-to-digital converter operates on the
principle of dual slope integration. An understanding of
the dual slope conversion technique will aid the user in
following the detailed TC820 theory of operation following this section. A conventional dual slope converter
measurement cycle has two distinct phases:
1.
2.
Input Signal Integration
Reference Voltage Integration (De-integration)
Referring to Figure 3-1, the unknown input signal to be
converted is integrated from zero for a fixed time period
(tINT), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated until the integrator output voltage returns to
zero. The reference integration (de-integration) time
(tDEINT) is then directly proportional to the unknown
input voltage (VIN).
A family of instruments can be created with the TC820.
No additional design effort is required to create instruments with 3-3/4 digit resolution.
The TC820 operates from a single 9V battery, with typical power of 10mW. Packages include a 40-pin plastic
DIP, 44-pin plastic flat package (PQFP), and 44-pin
PLCC.
DS21476B-page 8
2002 Microchip Technology Inc.
TC820
FIGURE 3-2:
EQUATION 3-1:
tINT
t
V
1
VIN(t)dt = REF DEINT
RINTCINT ∫ 0
RINTCINT
Where: VREF = Reference Voltage
tINT
= Integration Time
tDEINT = De-integration Time
T = Measurement
Period
20
10
0
0.1/T
For a constant VINT:
EQUATION 3-2:
3.2
t
VIN = VREF DEINT
tINT
FIGURE 3-1:
BASIC DUAL SLOPE
CONVERTER
C
Analog
Input Signal
R
Integrator
–
+
Comparator
–
+
NORMAL MODE
REJECTION OF DUAL
SLOPE CONVERTER
30
Normal Mode Rejection (dB)
In a simple dual slope converter, a complete conversion requires the integrator output to "ramp-up" from
zero and "ramp-down" back to zero. A simple mathematical equation relates the input signal, reference voltage, and integration time.
1/T
Input Frequency
10/T
Analog Section
In addition to the basic integrate and de-integrate dual
slope phases discussed above, the TC820 design
incorporates a "zero integrator output" phase and an
"auto-zero" phase. These additional phases ensure
that the integrator starts at 0V (even after a severe over
range conversion), and that all offset voltage errors
(buffer amplifier, integrator and comparator) are
removed from the conversion. A true digital zero reading is assured without any external adjustments.
A complete conversion consists of four distinct phases:
Switch
Driver
REF
Voltage
Phase
Control
Polarity Control
Clock
Control
Logioc
Integrator
Output
Display
Fixed Signal
Integrate Time
Counter
VIN = VREF
VIN = 1.2VREF
Variable Reference
Integrate Time
Accuracy in a dual slope converter is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle. An inherent benefit of the dual slope technique is noise immunity. Noise spikes are integrated or averaged to zero
during the integration periods, making integrating
ADCs immune to the large conversion errors that
plague successive approximation converters in high
noise environments. Interfering signals, with frequency
components at multiples of the averaging (integrating)
period, will be attenuated (Figure 3-2). Integrating
ADCs commonly operate with the signal integration
period set to a multiple of the 50/60Hz power line
period.
2002 Microchip Technology Inc.
1.
2.
3.
4.
Zero Integrator Output
Auto-Zero
Signal Integrate
Reference De-integrate
3.2.1
ZERO INTEGRATOR OUTPUT
PHASE
This phase guarantees that the integrator output is at
0V before the system zero phase is entered, ensuring
that the true system offset voltages will be compensated for even after an over range conversion. The
duration of this phase is 500 counts plus the unused
de-integrate counts.
3.2.2
AUTO-ZERO PHASE
During the auto-zero phase, the differential input signal
is disconnected from the measurement circuit by opening internal analog switches, and the internal nodes are
shorted to Analog Common (0VREF) to establish a zero
input condition. Additional analog switches close a
feedback loop around the integrator and comparator to
permit comparator offset voltage error compensation. A
voltage established on CAZ then compensates for internal device offset voltages during the measurement
cycle. The auto-zero phase residual is typically 10µV to
15µV. The auto-zero duration is 1500 counts.
DS21476B-page 9
TC820
3.2.3
SIGNAL INTEGRATION PHASE
Upon completion of the auto-zero phase, the auto-zero
loop is opened and the internal differential inputs connect to VIN+ and VIN-. The differential input signal is
then integrated for a fixed time period, which is 2000
counts (4000 clock periods). The externally set clock
frequency is divided by two before clocking the internal
counters.
The oscillator frequency is divided by 2 prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 8000 (4000) counts or
16,000 clock pulses. The 8000 count phase is independent of input signal magnitude or polarity.
Each phase of the measurement cycle has the following length:
TABLE 3-2:
The integration time period is:
MEASUREMENT CYCLE
PHASE LENGTH
EQUATION 3-3:
tINT =
Conversion Phase
4000
FOSC
The differential input voltage must be within the
device's Common mode range when the converter and
measured system share the same power supply common (ground). If the converter and measured system
do not share the same power supply common, as in
battery powered applications, VIN- should be tied to
analog common.
Polarity is determined at the end of signal integration
phase. The sign bit is a "true polarity" indication, in that
signals less than 1LSB are correctly determined. This
allows precision null detection that is limited only by
device noise and auto-zero residual offsets.
3.2.4
REFERENCE INTEGRATE
(DE-INTEGRATE) PHASE
The reference capacitor, which was charged during the
auto-zero phase, is connected to the input of the integrating amplifier. The internal sign logic ensures the
polarity of the reference voltage is always connected in
the phase opposite to that of the input voltage. This
causes the integrator to ramp back to zero at a constant
rate, determined by the reference potential.
The amount of time required (tDEINT) for the integrating
amplifier to reach zero is directly proportional to the
amplitude of the voltage that was put on the integrating
capacitor (VINT) during the integration phase.
EQUATION 3-4:
tDEINT =
RINTCINTVINT
VREF
The digital reading displayed by the TC820 is:
Digital Count = 2000
VIN+VINVREF
Counts
1) Auto-Zero
1500
2) Signal Integrate (Notes 1, 2)
2000
3) Reference Integrate
1 to 4001
4) Integrator Output Zero
Note
1:
2:
3.2.5
499 to 4499
This time period is fixed. The integration period for
theTC820 is:
tINT (TC820) = 4000/FOSC = 2000 counts.
Where FOSC is the clock oscillator frequency.
Times shown are the RANGE/FREQ at logic low (normal
operation). When RANGE/FREQ is logic high, signal
integrate times are 200 counts. See Section 3.2.7,
“10:1 Range Change”.
INPUT OVER RANGE
When the analog input is greater than full scale, the
LCD will display "OL" and the "OVER RANGE" LCD
annunciator will be on.
3.2.6
PEAK READING HOLD
The TC820 provides the capability of holding the highest (or peak) reading. Connecting the PK HOLD input
to VDD enables the peak hold feature. At the end of
each conversion, the contents of the TC820 counter
are compared to the contents of the display register. If
the new reading is higher than the reading being displayed, the higher reading is transferred to the display
register. A "higher" reading is defined as the reading
with the higher absolute value.
The peak reading is held in the display register, so the
reading will not "droop" or slowly decay with time. The
held reading will be retained until a higher reading
occurs, the PK HOLD input is disconnected from VDD,
or power is removed.
The peak signal to be measured must be present during the TC820 signal integrate period. The TC820 does
not perform transient peak detection of the analog input
signal. However, in many cases, such as measuring
temperature or electric motor starting current, the
TC820 "acquisition time" will not be a limitation. If true
peak detection is required, a simple circuit will suffice.
See the applications section for details.
The peak reading function is also available when the
TC820 is in the Frequency Counter mode. The counter
auto-ranging feature is disabled when peak reading
hold is selected.
DS21476B-page 10
2002 Microchip Technology Inc.
TC820
3.2.7
10:1 RANGE CHANGE
The analog input full scale range can be changed with
the RANGE/FREQ input. Normally, RANGE/FREQ is
held low by an internal pull-down. Connecting this pin
to VS+ will increase the full scale voltage by a factor
of 10. No external component changes are required.
The RANGE/FREQ input operates by changing the
integrate period. When RANGE/FREQ is connected to
VDD, the signal integration phase of the conversion is
reduced by a factor of 10 (i.e., from 2000 counts to 200
counts).
For the TC820, the 10:1 range change will result in ±4V
full scale. This full scale range will exceed the Common
mode range of the input buffer when operating from a
9V battery. If range changing is required for the TC820,
a higher supply voltage can be provided, or the input
voltage can be divided by 2 externally.
3.3
Frequency Counter
In addition to serving as an analog-to-digital converter,
the TC820 internal counter can also function as a frequency counter (Figure 3-3). In the Counter mode,
pulses at the RANGE/FREQ input will be counted and
displayed.
FIGURE 3-3:
The frequency counter derives its time-base from the
clock oscillator. The counter time-base is:
EQUATION 3-5:
tCOUNT =
FOSC
40,000
Thus, the counter will operate with a 1-second timebase when a 40kHz oscillator is used. The frequency
counter accuracy is determined by the oscillator accuracy. For accurate frequency measurements, a crystal
oscillator is recommended.
The frequency counter will automatically select the
proper range. Auto-range operation extends over four
decades, from 3.999kHz to 3.999MHz. Decimal points
are set automatically in the Frequency mode (Figure 3-4).
The logic switching levels of the RANGE/FREQ input
are CMOS levels. For best counter operation, an external buffer is recommended. See the applications section for details.
3.4
Logic Probe
The TC820 can also function as a simple logic probe
(Figure 3-5). This mode is selected when the LOGIC
input is high. Two dual purpose pins, which normally
control the decimal points, are used as logic inputs.
Connecting either input to a logic high level will turn on
the corresponding LCD annunciator. When the "low"
annunciator is on, the buzzer will be on. As with the frequency counter input, external level shifters/buffers are
recommended for the logic probe inputs.
TC820 COUNTER OPERATION
LCD
TC820
From Integrator
of A/D Converter
Clock
Oscillator
Data Latch, Peak Hold
Register, LCD
Decoder/Drivers
÷2
÷20,000
A/D Converter
Frequency Counter
FREQ/
VOLTS
Comparator
Enable
3-3/4 Digit Counter
Count
Overflow
A/D Converter/Frequency
Counter Select
To Decimal
Point Drivers
RANGE/
FREQ
Over Range
Detect
Frequency Input
2002 Microchip Technology Inc.
Programmable
Divider
( ÷1, 10, 100, 1000)
Under Range
Control
Auto-Range
Control
DS21476B-page 11
TC820
FIGURE 3-4:
AUTO-RANGE DECIMAL POINT SELECTION VS. FREQUENCY COUNTER INPUT
DP3
FIGURE 3-5:
DP2
DP1
fIN
Decimal Point
0Hz - 3999Hz
4kHz - 39.99kHz
40kHz - 399.9kHz
400kHz
DP3
DP2
DP1
NONE
LOGIC PROBE SIMPLIFIED SCHEMATIC
LCD
High
Low
Logic
Probe
Input
External Logic
Level Detection
CMOS
and Pulse Stretching Logic Levels
TC820
DP0/LO
DP1/HI
VDD
LCD
Drivers
LOGIC
Disable A/D Converter
To Buzzer
NC
DS21476B-page 12
2002 Microchip Technology Inc.
TC820
When the logic probe function is selected while FREQ/
VOLTS is low (A/D mode), the ADC will remain in the
Auto-Zero mode. The LCD will read "OL" and all
decimal points will be off (Figure 3-6).
FIGURE 3-6:
High
*
Low
**
To prevent rollover type errors from being induced by
large Common mode voltages, CREF should be large
compared to stray node capacitance. A 0.1µF capacitor
is typical.
The TC820 offers a significantly improved analog common temperature coefficient, providing a very stable
voltage suitable for use as a voltage reference. The
temperature coefficient of analog common is typically
35ppm/°C.
3.5.3
* "High" Annuciator will be on when DP1/HI = Logic High
** "Low" Annunciator and Buzzer will be on when DP0/LO = Logic High
If the logic probe is active while FREQ/VOLTS is high
(Counter mode), the frequency counter will continue to
operate. The display will read "OL" but the decimal
points will be visible. If the logic probe input is also connected to the RANGE/FREQ input, bringing the LOGIC
input low will immediately display the frequency at the
logic probe input.
3.5
3.5.1
Analog Pin Functional Description
DIFFERENTIAL SIGNAL INPUTS
(VIN+), (VIN-)
The TC820 is designed with true differential inputs, and
accepts input signals within the Input Stage Common
mode voltage (VCM) range. The typical range is
VDD – 1V to V SS + 1.5V. Common mode voltages are
removed from the system when the TC820 operates
from a battery or floating power source (isolated from
measured system) and VSS is connected to analog
common (see Figure 3-7).
In systems where Common mode voltages exist, the
86dB Common mode rejection ratio minimizes error.
Common mode voltages do, however, affect the integrator output level. A worst case condition exists if a
large, positive VCM exists in conjunction with a full
scale, negative differential signal. The negative signal
drives the integrator output positive along with VCM
(Figure 3-8). For such applications, the integrator output swing can be reduced below the recommended 2V
full scale swing. The integrator output will swing within
0.3V of V DD, or VDD without increased linearity error.
3.5.2
REFERENCE (VDD, VSS)
The TC820 reference, like the analog signal input, has
true differential inputs. In addition, the reference voltage can be generated anywhere within the power supply voltage of the converter. The differential reference
inputs permit ratiometric measurements and simplify
interfacing with sensors, such as load cells and temperature sensors.
2002 Microchip Technology Inc.
ANALOG COMMON
The analog common pin is set at a voltage potential
approximately 3.3V below VDD. This potential is
between 3.15V and 3.45V below VDD. Analog common
is tied internally to an N-channel FET capable of sinking 3mA. This FET will hold the common line at 3.3V
below VDD should an external load attempt to pull the
common line toward VDD. Analog common source current is limited to 12µA, and is, therefore, easily pulled to
a more negative voltage (i.e., below VDD – 3.3V).
The TC820 connects the internal VIN+ and VIN- inputs
to analog common during the auto-zero cycle. During
the reference integrate phase, VIN- is connected to
analog common. If VIN- is not externally connected to
analog common, a Common mode voltage exists.
This is rejected by the converter's 86dB Common mode
rejection ratio. In battery powered applications, analog
common and VIN- are usually connected, removing
Common mode voltage concerns. In systems where
VIN- is connected to the power supply ground or to a
given voltage, analog common should be connected to
VIN-.
The analog common pin serves to set the analog section reference or common point. The TC820 is specifically designed to operate from a battery, or in any
“measurement" system where input signals are not referenced (float), with respect to the TC820 power
source. The analog common potential of VDD – 3.3V
gives a 7V end of battery life voltage. The analog common potential has a voltage coefficient of 0.001%.
With a sufficiently high total supply voltage
(VDD – VSS > 7V), analog common is a very stable
potential with excellent temperature stability (typically
35ppm/°C). This potential can be used to generate the
TC820 reference voltage. An external voltage reference will be unnecessary in most cases, because of
the 35ppm/°C temperature coefficient. See the applications section for details.
DS21476B-page 13
TC820
FIGURE 3-7:
COMMON MODE VOLTAGE REMOVED IN BATTERY OPERATION WITH
VIN = ANALOG COMMON
Segment
Drive
LCD
BP1
VBUF
VIN+
Measured
System
V+ VPower
Source
FIGURE 3-8:
GND
BP3
BP2
OSC1
TC820
VIN-
V+
V-
CAZ VINT
Analog
Common VREF- VREF+ VDD
OSC2
VSS OSC3
NC
+
GND
9V
COMMON MODE VOLTAGE REDUCES AVAILABLE INTEGRATOR SWING
(VCOM ≠ VIN)
CI
Input Buffer
+
RI
+
–
–
VIN
VI
+
Integrator
–
VI =
VCM
TI
RI CI
[ VCM – VIN [
Where:
4000
TI = Integration Time =
FOSC
CI = Integration Capacitor
RI = Integration Resistor
DS21476B-page 14
2002 Microchip Technology Inc.
TC820
4.0
FUNCTION CONTROL INPUTS
PIN
4.1
Functional Description
The TC820 Operating modes are selected with the
function control inputs. See the control input truth,
Table 4-1. The high logic threshold is ≥ VDD – 1.5V and
the low logic level is ≤ DGND +1.5V.
TABLE 4-1:
TC820 CONTROL INPUT
TRUTH TABLE
Logic Input
RANGE/
FREQ
LOGIC
X
X
1
Logic Probe
0
0
0
A/D Converter,
VFULL SCALE = 2 x VREF
0
1
0
Note
4.1.1
Frequency
Counter
Input
1:
2:
The function of these dual purpose pins is determined
by the LOGIC input. When the TC820 is in the Analogto-Digital Converter mode, these inputs control the
LCD decimal points. See the decimal point truth,
Table 4-2. These inputs have internal 5µA pull-downs
to DGND when the Voltage/Frequency Measurement
mode is active.
0
TC820 DECIMAL POINT
TRUTH TABLE
DP1
DP0
A/D Converter,
VFULL SCALE = 20 x VREF
0
0
3999
0
1
399.9
Frequency Counter
1
0
39.99
1
1
3.999
Logic "0" = DGND
Logic "1" = VDD-
FREQ/VOLTS
LOGIC
The LOGIC input is used to activate the logic probe
function. When connected to VDD, the TC820 will enter
the Logic Probe mode. The LCD will show "OL" and all
decimal points will be off. The decimal point inputs
directly control "high" and "low" display annunciators.
When LOGIC is unconnected, or connected to DGND,
the TC820 will perform analog-to-digital or frequency
measurements, as selected by the FREQ/VOLTS
input. The LOGIC input has an internal 5µA pull-down
to DGND.
4.1.3
DP0/LO, DP1/HI
TABLE 4-2:
This input determines whether the TC820 is in the Analog-to-Digital Conversion mode, or in the Frequency
Counter mode. When FREQ/VOLTS is connected to
VDD, the TC820 will measure frequency at the RANGE/
FREQ input. When unconnected, or connected to
DGND, the TC820 will operate as an analog-to-digital
converter. This input has an internal 5µA pull-down to
DGND.
4.1.2
4.1.4
TC820 Function
FREQ/
VOLTS
1
When the TC820 analog-to-digital converter function is
selected, connecting RANGE/FREQ to VDD will divide
the integration time by 10. Therefore, the RANGE/
FREQ input can be used to perform a 10:1 range
change without changing external components.
LCD
Connecting the LOGIC input to VDD places the TC820
in the Logic Probe mode. In this mode, the DP0/LO and
DP1/HI inputs control the LCD "low" and "high" annunciators directly. When DP1/HI is connected to VDD, the
"high" annunciator will turn on. When DP0/LO is connected to VDD, the "low" annunciator and the buzzer
will turn on. The internal pull-downs on these pins are
disabled when the logic probe function is selected.
These inputs have CMOS logic switching thresholds.
For optimum performance as a logic probe, external
level shifters are recommended. See the applications
section for details.
4.1.5
BUZIN
This input controls the TC820 on-chip buzzer driver.
Connecting BUZIN to VDD will turn the buzzer on.
There is an external pull-down to DGND. BUZIN can be
used with external circuitry to provide additional functions, such as a fast, audible continuity indication.
4.2
Additional Features
The TC820 is available in 40-pin and 44-pin packages.
Several additional features are available in the 44-pin
package.
RANGE/FREQ
The function of this dual purpose pin is determined by
the FREQ/VOLTS input. When FREQ/VOLTS is connected to VDD, RANGE/FREQ is the input for the frequency counter function. Pulses at this input are
counted with a time-base equal to FOSC/40,000. Since
this input has CMOS input levels (VDD – 1.5V and
DGND +1.5V), an external buffer is recommended.
2002 Microchip Technology Inc.
DS21476B-page 15
TC820
4.2.1
4.2.2
EOC/HOLD
EOC/HOLD is a dual purpose, bi-directional pin. As an
output, this pin goes low for 10 clock cycles at the end
of each conversion. This pulse latches the conversion
data into the display driver section of the TC820.
EOC/HOLD can be used to hold (or "FREEZE") the display. Connecting this pin to VDD inhibits the display
update process. Conversions will continue, but the display will not change. EOC/HOLD will hold the display
reading for either analog-to-digital, or frequency
measurements.
The input/output structure of the EOC/HOLD pin is
shown in Figure 4-1. The output drive current is only a
few microAmps, so EOC/HOLD can easily be overdriven by an open collector logic gate, as well as a FET,
bipolar transistor, or mechanical switch. When used as
an output, EOC/HOLD will have a slow rise and fall
time due to the limited output current drive. A CMOS
Schmitt trigger buffer is recommended.
FIGURE 4-1:
EOC/HOLD
The OR output will be high when the analog input signal is greater than full scale (3999 counts). The UR output will be high when the display reading is 380 counts
or less.
The OR and UR outputs can be used to provide an
auto-ranging meter function. By logically ANDing these
outputs with the inverted EOC/HOLD output, a single
pulse will be generated each time an under ranged or
over ranged conversion occurs (Figure 4-2).
FIGURE 4-2:
EOC/HOLD
GENERATING UNDER
RANGE AND OVER
RANGE PULSES
TC820
*
UR
*
OR
*
EOC/HOLD PIN
4
Display
Update
≈ 500kΩ
TC820
*74HC132
4.2.3
EOC
DS21476B-page 16
OVER RANGE (OR),
UNDER RANGE (UR)
VDISP
The VDISP input sets the peak-to-peak LCD drive voltage. In the 40-pin package, VDISP is connected internally to DGND, providing a typical LCD drive voltage of
5VP-P. The 44-pin package includes a separate V DISP
input for applications requiring a variable or temperature compensated LCD drive voltage. See the applications information for suggested circuits.
2002 Microchip Technology Inc.
TC820
5.0
TYPICAL APPLICATIONS
5.2
5.1
Power Supplies
Digital ground is generated from an internal zener
diode (Figure 5-3). The voltage between V DD and
DGND is the internal supply voltage for the digital section of the TC820. DGND will sink a minimum of 3mA.
The TC820 is designed to operate from a single power
supply such as a 9V battery (Figure 5-1). The converter
will operate over a range of 7V to 15V. For battery operation, analog common (COM) provides a Common
mode bias voltage (see analog common discussion in
the theory of operation section). However, measurements cannot be referenced to battery ground. To do so
will exceed the Negative Common mode voltage limit.
FIGURE 5-1:
POWERING THE TC820
FROM A SINGLE 9V
BATTERY
Digital Ground (DGND)
DGND establishes the low logic level reference for the
TC820 mode select inputs, and for the frequency and
logic probe inputs. The DGND pin can be used as the
negative supply for external logic gates, such as the
logic probe buffers. To ensure correct counter operation at high frequency, connect a 1µF capacitor from
DGND to VDD.
DGND also provides the drive voltage for the LCD. The
TC820 40-pin package internally connects the LCD
VDISP pin to DGND, and provides an LCD drive voltage
of about 5VP-P. In the 44-pin package, connecting the
VDISP pin to DGND will provide a 5V LCD drive voltage.
TC820
VDD
FIGURE 5-3:
DGND AND COM
OUTPUTS
VREF+
+
VDD
VREF-
9V
COM
–
3.2V
12µA
+
VIN+
COM
VIN
VIN-
5V
–
N
–
+
Logic
Section
VSS
A battery with voltage between 3.5V and 7V can be
used to power the TC820, when used with a voltage
doubler, as shown in Figure 5-2. The voltage doubler
uses the TC7660 and two external capacitors. With this
configuration, measurements can be referenced either
to analog common or to battery ground.
FIGURE 5-2:
POWERING THE TC820
FROM A LOW VOLTAGE
BATTERY
VDD
VREF+
+
VREF-
3.5V to 6V
COM
VIN+
+
VIN
VINVSS
8
2
5
+
10µF
4
TC7660
3
10µF
+
2002 Microchip Technology Inc.
TC820
N
VSS
5.3
–
Digital Input Logic Levels
Logic levels for the TC820 digital inputs are referenced
to VDD and DGND. The high level threshold is
VDD – 1.5V, and the low logic level is DGND + 1.5V. In
most cases, digital inputs will be connected directly to
VDD with a mechanical switch. CMOS gates can also
be used to control the logic inputs, as shown in the logic
probe inputs section.
5.4
TC820
DGND
P
Clock Oscillator
The TC820 oscillator can be controlled with either a
crystal, or with an inexpensive resistor capacitor combination. The crystal circuit, shown in Figure 5-4, is recommended when high accuracy is required in the
Frequency Counter mode. The 40kHz crystal is a standard frequency for ultrasonic alarms, and will provide a
1-second time-base for the counter or 2.5 analog-todigital conversions per second. Consult the crystal
manufacturer for detailed applications information.
DS21476B-page 17
TC820
FIGURE 5-4:
SUGGESTED CRYSTAL
OSCILLATOR CIRCUIT
FIGURE 5-6:
SYSTEM CLOCK
GENERATION
TC820
TC820
RC
Oscillator
Components
10pF
5pF
38
37
XTAL
Oscillator
Components
39
470kΩ
40kHz
OSC1
OSC2
OSC3
22MΩ
Where low cost is important, the RC circuit of Figure 5-5
can be used. The frequency of this circuit will be
approximately:
A/D
Counter
÷2
Buzzer
÷8
EQUATION 5-1:
0.3
RC
TOSC =
FIGURE 5-5:
RC OSCILLATOR CIRCUIT
TC820
5pF
5.6.1
37
38
110kΩ
39
75pF
Typical values are R = 10kΩ and C = 68pF. The resistor value should be ≥ 100kΩ. For accurate frequency
measurement, an RC oscillator frequency of 40kHz is
required.
System Timing
All system timing is derived from the clock oscillator.
The clock oscillator is divided by 2 prior to clocking the
A/D counters. The clock is also divided by 8 to drive the
buzzer, by 240 to generate the LCD backplane frequency, and by 40,000 for the frequency counter timebase. A simplified diagram of the system clock is
shown in Figure 5-6.
DS21476B-page 18
÷ 240
Counter
Time-Base
÷ 40,000
10pF
5.6
5.5
LCD
Backplane
Driver
Component Value Selection
AUTO-ZERO CAPACITOR - CAZ
The value of the auto-zero capacitor (CAZ) has some
influence on system noise. A 0.47µF capacitor is recommended; a low dielectric absorption capacitor
(Mylar) is required.
5.6.2
REFERENCE VOLTAGE
CAPACITOR - CREF
The reference voltage capacitor used to ramp the integrator output voltage back to zero during the reference
integrate cycle is stored on C REF. A 0.1µF capacitor is
typical. A good quality, low leakage capacitor (such as
Mylar) should be used.
2002 Microchip Technology Inc.
TC820
5.6.3
INTEGRATING CAPACITOR - CINT
CINT should be selected to maximize integrator output
voltage swing without causing output saturation. Analog
common will normally supply the differential voltage reference. For this case, a ±2V integrator output swing is
optimum when the analog input is near full scale. For 2.5
readings/second (FOSC = 40kHz) and VFS = 400mV, a
0.22µF value is suggested. If a different oscillator frequency is used, CINT must be changed in inverse proportion to maintain the nominal ±2V integrator swing.
An exact expression for CINT is:
EQUATION 5-2:
CINT =
Where: FOSC =
VFS =
RINT =
VINT =
4000 VFS
VINT RINT FOSC
Clock Frequency
Full Scale Input Voltage
Integrating Resistor
Desired Full Scale Integrator
Output Swing
In some applications, a scale factor other than unity
may exist between a transducer output voltage and the
required digital reading. Assume, for example, that a
pressure transducer output is 800mV for 4000 lb/in2.
Rather than dividing the input voltage by two, the reference voltage should be set to 400mV. This permits the
transducer input to be used directly.
The internal voltage reference potential available at analog common will normally be used to supply the converter's reference voltage. This potential is stable
whenever the supply potential is greater than approximately 7V. The low battery detection circuit and analog
common operate from the same internal reference. This
ensures that the low battery annunciator will turn on at
the time the internal reference begins to lose regulation.
The TC820 can also operate with an external reference. Figure 5-7 shows internal and external reference
applications.
FIGURE 5-7:
9V
CINT must have low dielectric absorption to minimize
rollover error. A polypropylene capacitor is
recommended.
5.6.4
5.7
VSS
A full scale reading (4000 counts for TC820) requires
the input signal be twice the reference voltage. See
Reference Voltage Selection, Table 5-1 below.
TABLE 5-1:
REFERENCE VOLTAGE
SELECTION
Full Scale Input Voltage
(VFS) (Note 1)
VREF
Resolution
200mV
(Note 2)
—
400mV
200mV
10µV
1V
500mV
250µV
2V (Notes 3, 4)
1V
500µV
Note 1: TC820 in A/D Converter mode, RANGE/FREQ =
logic low.
2: Not recommended.
3: VFS > 2V may exceed the Input Common mode
range. See Section 3.2.7, "10:1 Range Change".
4: Full scale voltage values are not limited to the values shown. For example, TC820 VFS can be any
value from 400mV to 2V.
2002 Microchip Technology Inc.
MCP1525
VDD
VDD
VREF+ 2kΩ
TC820
VIN
VOUT
TC820
VREF
VSS
VREF+
VREF-
VREF-
Analog
Common
Analog
Common
1µF
SET VREF = 1/2 VFULL SCALE
(a) Internal Reference
5.8
Reference Voltage Selection
V+
+
22kΩ
INTEGRATING RESISTOR - R INT
The input buffer amplifier and integrator are designed
with class A output stages. The integrator and buffer
can supply 40µA drive currents with negligible linearity
errors. RINT is chosen to remain in the output stage linear drive region, but not so large that printed circuit
board leakage currents induce errors. For a 400mV full
scale, R INT should be about 100kΩ.
REFERENCE VOLTAGE
CONNECTIONS
(b) External Reference
Ratiometric Resistance
Measurements
The TC820 true differential input and differential reference make ratiometric readings possible. In ratiometric
operation, an unknown resistance is measured with
respect to a known standard resistance. No accurately
defined reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current is passed through the pair
(Figure 5-8). The voltage developed across the unknown
is applied to the input and voltages across the known
resistor applied to the reference input. If the unknown
equals the standard, the input voltage will equal the reference voltage and the display will read 2000. The displayed
reading can be determined from the following expression:
EQUATION 5-3:
Displayed Reading =
RUNKNOWN
R STANDARD
The display will over range for values of RUNKNOWN ≥
2 x RSTANDARD.
DS21476B-page 19
TC820
FIGURE 5-8:
LOW PARTS COUNT
RATIOMETRIC
RESISTANCE
MEASUREMENT
FIGURE 5-10:
SIMPLE EXTERNAL
LOGIC PROBE BUFFER
TC820
+9V
VDD
VREF+
RSTANDARD
VDD
VREF-
LCD
VIN+
RUNKNOWN
LOGIC
Logic
Probe
Input
TC820
VINAnalog
Common
*
DP1/HI
*
DP0/LO
DGND
*74HC14
5.9
Buffering the FREQ Input
When the FREQ/VOLTS input is high and the LOGIC
input is low, the TC820 will count pulses at the RANGE/
FREQ input. The time-base will be FOSC/40,000, or
1 second with a 40kHz clock. The signal to be measured should swing from V DD to DGND. The RANGE/
FREQ input has CMOS input levels without hysteresis.
For best results, especially with low frequency sinewave inputs, an external buffer with hysteresis should
be added. A typical circuit is shown in Figure 5-9.
FIGURE 5-9:
FREQUENCY COUNTER
EXTERNAL BUFFER
+9V
TC820
+
1µF
If carefully controlled logic thresholds are required, a
window comparator can be used. Figure 5-11 shows a
typical circuit. This circuit will turn on the high or low
annunciators when the logic thresholds are exceeded,
but the resistors connected from DP0/LO and DP1/HI
to DGND will turn both annunciators off when the logic
probe is unconnected.
The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or impossible to see. To display short pulses properly, the input
pulse should be "stretched." The circuit of Figure 5-11
shows capacitors added across the input pull-down
resistors to stretch the input pulse and permit viewing
short duration input pulses.
FIGURE 5-11:
WINDOW COMPARATOR
LOGIC PROBE
VDD
+9V
FREQ/VOLTS
DGND
VDD
Frequency
Input
RANGE/FREQ
R1
VH –
74HC14
1MΩ
GND
5.10
DGND
Logic Probe Inputs
TC820
LOGIC
1N4148
DP1/HI
+
R2
Logic
Probe Input
–
1N4148
VL +
DP0/LO
1MΩ
The DP0/LO and DP1/HI inputs provide the logic probe
inputs when the LOGIC input is high. Driving either
DP0/LO or DP1/HI to a logic high will turn on the appropriate LCD annunciator. When DP0/LO is high, the
buzzer will be on.
R3
DGND
Note: Select R1, R2, R3 for desired logic thresholds.
To provide a "single input" logic probe function, external
buffers should be used. A simple circuit is shown in
Figure 5-10. This circuit will turn the appropriate annunciator on for high and low level inputs.
DS21476B-page 20
2002 Microchip Technology Inc.
TC820
5.11
External Peak Detection
The TC820 will hold the highest A/D conversion or frequency reading indefinitely when the PKHOLD input is
connected to VDD. However, the analog peak input
must be present during the A/D converter's signal integrate period. For slowly changing signals, such as temperature, the peak reading will be properly converted
and held.
If rapidly changing analog signals must be held, an
external peak detector should be added. An inexpensive
circuit can be made from an op amp and a few discrete
components, as shown in Figure 5-12. The droop rate of
the external peak detector should be adjusted so that the
held voltage will not decay below the desired accuracy
level during the converter's 400msec conversion time.
FIGURE 5-12:
EXTERNAL PEAK
DETECTOR
Other display output lines have waveforms that vary
depending on the displays values. Figure 5-13 shows a
set of waveforms for the a, g, d outputs of one digit for
several combinations of "on" segments.
FIGURE 5-14:
TYPICAL DISPLAY
OUTPUT WAVEFORMS
VDD
VH
Segment
Line
All OFF
VL
VDISP
VDD
VH
a Segment
ON
d, g OFF
VL
VDISP
VDD
VH
a, g ON
d OFF
VL
VDISP
+9V
VDD
10kΩ
VDD
VH
PKHOLD
1N4148
–
TL061
+
VIN
All ON
VIN+
0.01µF
Offset Null
TABLE 5-2:
VSS
0V
5.12
VL
VDISP
TC820
Liquid Crystal Display (LCD)
The TC820 drives a triplex (multiplexed 3:1) LCD with
three backplanes. The LCD can include decimal points,
polarity sign, and annunciators for over range, peak
hold, high and low logic levels, and low battery.
Table 5-2 shows the assignment of the display segments to the backplanes and segment drive lines. The
backplane drive frequency is obtained by dividing the
oscillator frequency by 240.
Backplane waveforms are shown in Figure 5-13. These
appear on outputs BP1, BP2, and BP3. They remain the
same, regardless of the segments being driven.
FIGURE 5-13:
BACKPLANE
WAVEFORMS
BP1
LCD BACKPLANE AND
SEGMENT ASSIGNMENTS
40-Pin 44-Pin LCD Display
(PDIP) (PQFP) Pin Number
BP1
BP2
BP3
1
40
3
2
41
4
LOW
A4
"—"
3
42
5
B4
G4
4
43
6
HIGH
C4
D4
5
44
7
A3
F3
DP3
6
1
8
B3
G3
E3
7
2
9
OVER
C3
D3
8
3
10
A2
F2
DP2
9
4
11
B2
G2
E2
10
5
12
PEAK
C2
D2
11
6
13
A1
F1
DP1
12
7
14
B1
G1
E1
13
8
2,16*
—
C1
D1
E4
14
9
1
BP1
—
BATT
15
10
15
LOW
BP2
BP3
*Connect both pins 2 and 16 of LCD to TC820 BP3 of output.
BP2
BP3
2002 Microchip Technology Inc.
DS21476B-page 21
TC820
5.13
LCD Source
5.15
Although most users will design their own custom LCD,
a standard display for the TC820 (Figure 5-15), Part No.
ST-1355-M1, is available from the following sources:
LCD Drive Voltage (VDISP)
The peak-to-peak LCD drive voltage is equal to (VDD –
VDISP). In the 40-pin dual in-line package (DIP), V DISP
is internally connected to DGND, providing a typical
LCD drive voltage of 5VP-P.
Crystaloid (USA)
Crystaloid Electronics
P.O. Box 628
5282 Hudson Drive
Hudson, OH 44238
Phone: 216-655-2429
For applications with a wide temperature range, some
LCDs require that the drive levels vary with temperature
to maintain good viewing angle and display contrast. In
this case, the TC820 44-pin package provides a pin connection for VDISP. Figure 5-16 shows TC820 circuits that
can be adjusted to give a temperature compensation of
about 10mV/°C between VDD and VDISP. The diode
between GND and VDISP should have a low turn on voltage because VDISP cannot exceed 0.3V below GND.
Crystaloid (Europe)
Rep. France
102, rue des Nouvelles
F92150 Suresnes France
Phone: 33-1-42-04-29-25
Fax: 33-1-45-06-46-99
5.16
Crystal Source
Two sources of the 40kHz crystal are:
FIGURE 5-15:
HIGH
TYPICAL TC820 LCD
OVER
PEAK
Statek Corp.
512 N. Main St.
Orange, CA 92668
Phone: 714-639-7810
Fax: 714-997-1256
Part #: CX-1V-40.0
BATT
LOW
SPK Electronics
2F-1, No. 312, Sec, 4, Jen Ai Rd.
Taipei, Taiwan R.O.C.
Phone: (02) 754-2677
Fax: 886-2-708-4124
Part #: QRT-38-40.0kHz
PIN 1
5.14
Annunciator Output
The annunciator output is a square wave running
at the backplane frequency (for example, 167Hz when
FOSC = 40kHz). The peak-to-peak amplitude is equal to
(VDD – VDISP). Connecting an annunciator of the LCD
to the annunciator output turns it on; connecting it to its
backplane turns it off.
FIGURE 5-16:
TEMPERATURE COMPENSATING CIRCUITS
V+
1N4148
39kΩ
V+
39kΩ
39
200kΩ
2N2222
20kΩ
–
5kΩ
+
TL071 1N5817
75kΩ
39
TC820
TC820
11 V
DISP
12
11 V
DISP
1N5817
DGND
12
DGND
18kΩ
24
V-
24
V-
Note: Pin numbers shown are for 44-pin flat package.
DS21476B-page 22
2002 Microchip Technology Inc.
TC820
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Package marking data not available at this time.
6.2
Taping Forms
Component Taping Orientation for 44-Pin PLCC Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
44-Pin PLCC
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
32 mm
24 mm
500
13 in
Note: Drawing does not represent total number of pins.
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
44-Pin PQFP
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24 mm
16 mm
500
13 in
Note: Drawing does not represent total number of pins.
2002 Microchip Technology Inc.
DS21476B-page 23
TC820
6.3
Package Dimensions
40-Pin PDIP (Wide)
PIN 1
.555 (14.10)
.530 (13.46)
2.065 (52.45)
2.027 (51.49)
.610 (15.49)
.590 (14.99)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.150 (3.81)
.115 (2.92)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.015 (0.38)
.008 (0.20)
3° MIN.
.700 (17.78)
.610 (15.50)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
44-Pin PLCC
PIN 1
.021 (0.53)
.013 (0.33)
.050 (1.27) TYP.
.695 (17.65)
.685 (17.40)
.630 (16.00)
.591 (15.00)
.656 (16.66)
.650 (16.51)
.032 (0.81)
.026 (0.66)
.020 (0.51) MIN.
.656 (16.66)
.650 (16.51)
.120 (3.05)
.090 (2.29)
.695 (17.65)
.685 (17.40)
.180 (4.57)
.165 (4.19)
Dimensions: inches (mm)
DS21476B-page 24
2002 Microchip Technology Inc.
TC820
6.3
Package Dimensions (Continued)
44-Pin PQFP
7° MAX.
.009 (0.23)
.005 (0.13)
PIN 1
.018 (0.45)
.012 (0.30)
.041 (1.03)
.026 (0.65)
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
.031 (0.80) TYP.
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
.010 (0.25) TYP.
.083 (2.10)
.075 (1.90)
.096 (2.45) MAX.
Dimensions: inches (mm)
2002 Microchip Technology Inc.
DS21476B-page 25
TC820
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21476B-page 26
2002 Microchip Technology Inc.
TC820
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro ® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
2002 Microchip Technology Inc.
DS21476B-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Japan
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd
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Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
China - Beijing
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Tel: 480-792-7966 Fax: 480-792-7456
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
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500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
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Tel: 978-692-3848 Fax: 978-692-3821
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Tel: 630-285-0071 Fax: 630-285-0075
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03/01/02
*DS21476B*
DS21476B-page 28
2002 Microchip Technology Inc.