DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter General Description recovery circuits to minimize bit delay through the converter (no FIFO is used to buffer data between the FX and TX interfaces). Furthermore, due to the excellent rise/fall time control by a built-in waveshaping filter, the DM9301FP needs no external filter to transport signals to the media on the 100Base-TX interface. The DM9301FP is a physical-layer, single-chip, lowpower media converter for 100BASE-TX/FX full duplex repeater applications. On the TX media side, it provides a direct interface to Unshielded Twisted Pair Cable 5 (UTP5) for 100BASE-TX Fast Ethernet. On the FX media side, it provides a direct interface to a Pseudo Emitter Coupled Logic level interface (PECL). The DM9301FP uses a low power and high performance CMOS process. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE802.3u, including the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD) and a PECL compliant interface for a fiber optic module, compliant with ANSI X3.166. The DM9301FP provides two independent clock Patent-Pending Circuits • Smart adaptive receiver equalizer • Digital algorithm for high frequency clock/data recovery circuit • High speed wave-shaping circuit Block Diagram PECLSD Link Status Monitor & LED Driver FXSD RCVR Rise/Fall Time CTL 25M FXRXCLK 125M FXRXCLK PECLRXI +/- PECL RCVR RX CRM NRZI to NRZ Serial to Parallel TX Codegroup Alignment Monitor 25M OSC/XTAL Scrambler Parallel to Serial NRZ to NRZI NRZI to MLT-3 MLT-3 Driver TPTXO+/- FX Codegroup Alignment Monitor CGM 25M TPRXCLK 125M TPRXCLK PECLTXO +/- PECL TXMT Final Version: DM9301FP-DS-F03 June 06, 2007 NRZ to NRZI Parallel to Serial Descrambler Serial to Parallel NRZI to NRZ MLT-3 to NRZI Adaptive EQ TPRXI+/- RX CRM 1 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Table of Contents Block Diagram .......................................................... 1 FX Parallel to Serial Converter........................... 13 FX NRZ to NRZI Encoder................................... 13 Link Monitor and LED Driver .............................. 13 Table of contents...................................................... 2 Absolute Maximum Ratings ................................... 14 Features ................................................................... 3 DC Electrical Characteristics.................................. 15 Pin Configuration: DM9301FP QFP ......................... 4 AC Electrical Characteristics.................................. 16 Pin Description ......................................................... 5 Timing Waveforms ................................................. 17 100BASE-TX to FX Transmit Timing Diagram... 17 100BASE-FX to TX Transmit Timing Diagram... 17 5-Bit Symbol 100Base-TX/FX Transmit Timing Diagram............................................................... 17 5-Bit Symbol 100Base-TX/FX Receive Timing Diagram............................................................... 18 General Description.................................................. 1 Functional Description............................................ 10 100Base-FX to TX Operation ................................. 10 FX PECL Receiver.............................................. 10 FX Receiver Clock Recovery Module................. 10 FX NRZI to NRZ Converter ................................ 10 FX Serial to Parallel Converter ........................... 11 FX Code Group Alignment Monitor .................... 11 TX Scrambler...................................................... 11 TX Parallel to Serial Converter ........................... 11 TX NRZ to NRZI Converter ................................ 11 TX NRZI to MLT-3 Converter ............................. 11 TX MLT-3 Driver ................................................. 11 100Base-TX to FX Operation ................................. 12 TX Signal Detect................................................. 12 TX Digital Adaptive Equalization ........................ 12 TX MLT-3 to NRZI Decoder................................ 13 TX Clock Recovery Module ................................ 13 TX NRZI to NRZ Decoder................................... 13 TX Serial to Parallel Converter ........................... 13 TX Code Group Monitor...................................... 13 TX Descrambler.................................................. 13 2 Application Circuit (For Reference Only) ............... 19 Package Information .............................................. 21 Ordering Information .............................................. 22 Disclaimer............................................................... 22 Company Overview................................................ 22 Products ................................................................. 22 Contact Windows ................................................... 22 Warning .................................................................. 22 Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Features • 100BASE-TX/FX single-chip media converter • Total bit delay from FX to TX interface is 20 bit times (10 bit times each direction). • Optional propagate HALT on no Link condition • Compliant with IEEE802.3u 100BASE-TX standard • Compliant with ANSI X3T12 TP-PMD 1995 standard • Compliant with ANSI X3.166 FDDI-PMD • Supports Half and Full Duplex operation 100Mbps, the DM9301FP operates in Full Duplex mode at all times • High performance 100Mbps clock generator and data recovery circuit • Controlled output edge rates in the 100Base-TX transmitter without the need for an external filter Final Version: DM9301FP-DS-F03 June 06, 2007 • LED supports for FX Link, TX link, FX receive data; TX receives data, and FX code group error and TX code group error. • Built in LED test, all LED will light during a reset condition on the DM9301FP • Digital clock recovery and regeneration circuit using an advanced digital algorithm to minimize jitter • Supports diagnostic TX to TX analog Loopback and FX to FX analog Loopback (Loopback at the NRZI interface) • Supports diagnostic TX to TX digital Loopback and FX to FX digital Loopback (Loopback at the 5B symbol interface) • Low-power, high-performance CMOS process • Available in a 100 QFP package 3 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter 4 RESET# TRIDRV TESTMODE DGND DVCC 83 82 81 86 84 DVCC 87 85 TPI0 TPMUX 88 DGND 91 TPI1 TPI2 92 89 TPI3 93 90 DVCC CONFIGA 94 FXDLPBK CONFIGB 95 TXDLPBK 97 96 AGND DGND 98 AGND 99 100 Pin Configuration: DM9301FP QFP TPRXI+ 1 80 FXERRLED# TPRXI- 2 79 RXD0 AVCC 3 78 DGND AVCC 4 77 RXD1 AGND 5 76 RXD2 AGND 6 75 DVCC AVCC 7 74 RXD3 BGREF 8 73 RXD4 BGRET 9 72 DGND TXCLK AVCC 10 71 AGND 11 70 RXCLK AGND 12 69 FXRCVLED# TPTXO- 13 68 DGND TPTXO+ 14 67 FXLNKLED# AVCC 15 66 DVCC AGND 16 65 TPO6 DM9301FP AGND 17 64 TXLNKLED# PECLTXO- 18 63 DGND PECLTXO+ 19 62 TXRCVLED# AGND 20 61 TPO0 AVCC 21 60 TPO1 PECLSD- 22 59 DGND PECLSD+ 23 58 TPO2 PECLRXI- 24 57 TPO3 PECLRXI+ 25 56 DVCC TPO4 43 44 45 46 47 TXD4 TXD3 TXD2 DVCC TXD1 50 42 DGND DGND 41 BPSCRAM 49 40 MUXCTL0 48 39 MUXCTL1 TXD0 38 TPEN FRCFXSD 37 DVCC DVCC 36 TXERRLED# 51 FXALPBK 52 30 35 29 34 AGND OSC/XTL# TXALPBK DGND HLTNOLNK 53 33 28 DGND TPO5 X2 32 54 31 55 27 AVCC 26 AGND AVCC OSC/X1 Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Pin Description Pin No. Media Interface 1, 2 Pin Name I/O Description TPRXI+, TPRXI- I 13, 14 TPTXO-, TPTXO+ O 24, 25 PECLRXI-, PECLRXI+ I 18, 19 PECLTXO-, PECLTXO+ O 22, 23 PECLSD-, PECLSD+ I 100Mbps-TX Differential Input Pair: These pins are differential receive input for 100BASETX. They are capable of receiving 100BASE-TX MLT-3 data. 100BASE-TX Differential Output Pair: These outputs drive MLT-3 encoded data over 100Mbps twisted pair cable and provide controlled rise and fall times designed to filter the transmitter output, reducing any associated EMI. 100BASE-FX PECL Receive Data Differential Pair: These pins are differential receive input for 100BASEFX PECL. They are capable of receiving PECL 100BASE-FX NRZI data. 100BASE-FX Transmit Differential Output Pair: These outputs drive NRZI encoded data for PECL FX interface. 100BASE-FX PECL Signal detect: These pins are differential signals that indicate to the DM9301FP that the Optical Module interface is detecting valid optical energy. Clock and Misc. Interface 27 OSCI/X1 I 28 X2 O 30 OSC/XTL# I 8 BGREF I 9 BGRET I Final Version: DM9301FP-DS-F03 June 06, 2007 Crystal or Oscillator Input: This pin should connect to one side of a 25MHz, 50ppm crystal if OSC/XTL#=0. This pin is the 25MHz, 50ppm external TTL oscillator input, if OSC/XTLB=1. Crystal Oscillator Output: The other side of a 25MHz, 50ppm crystal should connect to this pin if OSC/XTL#=0. Leave this pin open if OSC/XTL#=1. Crystal or Oscillator Selector Pin: OSC/XTL#=0: An external 25MHz, 50ppm crystal should connect to X1 and X2 pins. OSC/XTL#=1: An external 25MHz, 50ppm oscillator should connect to X1 and left X2 pin open. Bandgap Voltage Reference Resistor: It connects to a 6.49KΩ, 1% error tolerance resistor between this pin and BGRET pin 9 to provide an accurate current reference for the chip. Bandgap Return Return pin for 6.49KΩ resistor connection, DO NOT CONNECT TO GROUND. 5 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Clock and Misc. Interface (Continued) 84 TRIDRV 6 I 85 RESET# I 34 HLTNOLNK I 93 95 LED Interface 67 CONFIGA CONFIGB I I FXLNKLED# OD 64 TXLNKLED# OD 69 FXRCVLED# OD 62 TXRCVLED# OD 80 FXERRLED# OD Tristate Digital Output Pins: When set high, all digital output pins are set to high impedance. Reset: Active Low input that initializes the DM9301FP, must be asserted low for 30msecs after VCC is stable. Send Halt on no Link Condition: Causes the DM9301FP to Send out a Halt symbol to the TX interface if no FX link active or send out a Halt symbol to the FX interface if no TX link active. Propagates a no-link condition to the Link Partner if 1, Idle symbol if 0. Active high Config A: Must be connected to GND Config B: Must be connected to GND FX Link LED: Indicates Good Link status for 100Mbps FX operation. Active low (Open Drain Output) TX Link LED: Indicates Good Link status for 100Mbps TX operation. Active low (Open Drain Output) FX Receive LED: Indicates the presence of receive activity for 100Mbps FX operation. Active low (Open Drain Output) The DM9301FP incorporates a "monostable" function on the FXRCVLED output. This ensures that even minimum size packets generate adequate LED ON to insure visibility. TX Receive LED: Indicates the presence of receive activity for 100Mbps TX operation. Active low (Open Drain Output) The DM9301FP incorporates a "monostable" function on the TXRCVLED output. This ensures that even minimum size packets generate adequate LED ON to insure visibility. FX Error LED: Indicates an error was detected by the FX Code Group Alignment Monitor function on the FX receiver. Active low (Open Drain Output) The DM9301FP incorporates a "monostable" function on the FXERRLED output. This ensures that even minimum size errors generate adequate LED ON to insure visibility. Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter LED Interface(Continued) 52 TXERRLED# Diagnostic Port Interface 36 FXALPBK OD TX Error LED: Indicates an error was detected by the TX Code Group Alignment Monitor function on the TX receiver. Active low (Open Drain Output) The DM9301FP incorporates a "monostable" function on the TXERRLED output. This ensures that even minimum size errors generate adequate LED ON to insure visibility. I FX Interface Analog Loop Back: Loops the FX NRZI analog transmit data path to the FX NRZI analog receive path. Initiated at an H/W reset. Active high. TX Interface Analog Loop Back: Loops the TX NRZI analog transmit data path to the TX NRZI analog receive path. Initiated at an H/W reset. Active high. FX Interface Digital Loop Back: Loops the FX 5-bit symbol digital transmit data path to the FX 5-bit symbol digital receive path. Initiated at an H/W reset. Active high. TX Interface Digital Loop Back: Loops the TX 5-bit symbol digital transmit data path to the TX 5-bit symbol digital receive path. Initiated at an H/W reset. Active high. Receive Data 4 through 0: The receive data 5-bit symbol interface. Data is clocked out on the falling edge of RXCLK. Receive Clock: 25 MHz recovered clock, clock source is selected by the MUXCTL1 and MUXCTL0. Transmit Data 4 through 0: The transmit data 5-bit symbol interface. Data is clocked in on the rising edge of TXCLK. Transmit Clock: 25 MHz recovered clock, clock source is selected by the MUXCTL1 and MUXCTL0. 35 TXALPBK I 96 FXDLPBK I 97 TXDLPBK I 79, 77, 76, 74, 73 70 RXD0, RXD1, RXD2, RXD3, RXD4 RXCLK 0 48, 47, 45, 44, 43 71 TXD0, TXD1, TXD2, TXD3, TXD4 TXCLK Final Version: DM9301FP-DS-F03 June 06, 2007 O I O 7 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Diagnostic Port Interface (Continued) 39, 40 MUXCTL1, MUXCTL0 I Mux. Control 1 and 0: Used for testing the DM9301FP Data Paths. Set to zero for normal operation. Initiated at an H/W reset. Active high. DATA PATH MUXCTL1 MUXCTL0 0 0 Normal, FX to TX and TX to FX 65, 54, 55, 57, 58, 60, 61 92, 91, 89, 88 8 TPO6, TPO5, TPO4, TPO3, TPO2, TPO1, TPO0 TPI3, TPI2, TPI1, TPI0, O I 1 0 TX Transmit from TXD[4:0] TXCLK from TX PLL TX Receive to RXD[4:0] RXCLK from TX receive clock 0 1 FX Transmit from TXD[4:0] TXCLK from FX PLL FX Receive to RXD[4:0] RXCLK from FX receive clock 1 1 TX Transmit from TXD[4:0] TXCLK from TX PLL FX Receive to RXD[4:0] RXCLK from FX receive clock Test Port Output: Reflects the DM9301FP internal status. Selection of status indicators is made by using TPEN and TPMUX. Initiated at an H/W reset. Active high. Test Port Input: Controls the DM9301FP internal test features. Selection of input control is made by using TPEN and TPMUX. TPEN must be true (one) for this signal to take effect. Initiated at an H/W reset. Active high. Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Diagnostic Port Interface (Continued) 49 FRCFXSD I 38 TPEN I 87 TPMUX I 41 BPSCRAM I Force FX Signal Detect Forces the DM9301FP FX interface Signal Detect true Initiated at an H/W reset. Active high. Test Port Enable: Enables the DM9301FP Test Port features. Initiated at an H/W reset. Active high. Test Port Mux: Controls the DM9301FP Test Port Input and Output bits. A value of zero indicates the TX interface and a value of one indicates the FX interface. TPEN must be true (one) for this signal to take effect. Initiated at an H/W reset. Active high. Bypass Scrambler: Controls the DM9301FP TX interface Scrambler/Descrambler function. A value of zero indicates to scramble and de-scramble the TX interface 5-bit symbol data to and from the FX interface. A value of one bypasses the scrambler/de-scrambler function. Initiated at an H/W reset. Active high. Power and Ground Pins : The power (VCC) and ground (GND) pins of the DM9301FP are grouped in pairs of two categories - Digital Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair. Group A - Digital Supply Pairs 33, 42, 50, 53, 63, 68, 72, 78, 82, 90, 98 DGND P Digital Logic Ground. 37, 46, 51, 56, 66, 75, 81, 86, 94 DVCC P Digital Logic power supply Group B - Analog Circuit Supply Pairs 5, 6, 11, 12, 16, 17, 20, 29, 32, 99, 100, AGND P Analog circuit ground 3, 4, 7, 10, 15, 21, 26, 31 AVCC P Analog circuit power supply Final Version: DM9301FP-DS-F03 June 06, 2007 9 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Functional Description FX PECL Receiver The DM9301FP Fast Ethernet single-chip TX/FX media converter, provides the functionality as specified in IEEE802.3, integrates the complete 100BASE-TX and a PECL optic module interface for 100Base-FX. The DM9301FP implements the PCS, PMA, and TP-PMD sublayer functions, as defined by specification. The term “X” will be used to describe the sections used in the fiber PHY layer interface. The term “X” will be used to describe the sections used in the twisted-pair PMD layer interface. The PECL receiver receives NRZI encoded, differential Pseudo Emitter Coupled Logic level signal. The receiver converts the receive signal into a single-ended NRZI signal and presents this signal to the FX Clock Recovery Module. FX Receiver Clock Recovery Module The FX Clock Recovery Module accepts NRZI data from the PECL receiver. The FX Clock Recovery Module locks onto the data stream, using a Phase Lock Loop (PLL) and extracts the 125 MHz reference clock. The extracted and synchronized clock and data are presented to the FX NRZI to NRZ Decoder. 100BASE-FX to TX Operation The block diagram in figure 1 provides an overview of the functional blocks contained in the FX to TX media converter interface. The FX to TX interface includes the following functional blocks: • • • • • • • • • • FX NRZI to NRZ Converter The receive data stream is required to be NRZI encoded for compatibility with the standards for 100Base- FX. This conversion process must be reversed on the transmit end. The FX NRZI to NRZ decoder receives the NRZI data stream from the FX Clock Recovery Module and converts it to a NRZ data stream to be presented to the FX Serial to Parallel conversion block. FX PECL Receiver FX Receiver Clock Recovery Module FX NRZI to NRZ Converter FX Serial to Parallel Converter FX Code Group Alignment Monitor TX Scrambler TX Parallel to Serial Converter TX NRZ to NRZI Converter TX NRZI to MLT-3 Converter TX MLT-3 Driver PECLSD FX Link Status Monitor FXSD RCVR Rise/Fall Time CTL 25M FXRXCLK 125M FXRXCLK PECLRXI +/- FX PECL RCVR FX RX CRM FX NRZI to NRZ FX Serial to Parallel TX Scrambler TX Parallel to Serial TX NRZ to NRZI TX NRZI to MLT-3 MLT-3 Driver TPTXO+/- FX Codegroup Alignment Monitor 25M OSC/XTAL CGM FX to TX Block Diagram Figure 1 10 Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter FX Serial to Parallel Converter TX Parallel to Serial Converter The Serial to Parallel converter receives a serial data stream from the NRZI to NRZ converter, and converts the data stream to parallel data to be presented to the scrambler. The parallel data format presented to the TX scrambler is 5B coded. The TX Parallel to Serial converter receives parallel 5B scrambled data from the scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the NRZ to NRZI converter block FX Code Group Alignment Monitor TX NRZ to NRZI Converter The FX Code Group Alignment block receives nonaligned 5B data from the FX Serial to Parallel converter and monitors it for 5B code group violations. FX Code Group Alignment occurs after the J/K is detected, and subsequent data is monitored on a fixed boundary. If a violation is detected, the FX Code Group Alignment Monitor block signals the error to the Link Status Monitor blocks. In turn, the Link Status Monitor block flashes the FX error LED (FXERRLED#). After the transmit data stream has been scrambled and serialized, the data must be NRZI encoded for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. TX Scrambler The scrambler also receives data from the FX Serial to Parallel converter. Data from the serial to parallel conversion block is 5B symbol encoded. The scrambler is required to control the radiated emissions (EMI) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100BaseTX transmit operation. TX MLT-3 Converter The MLT-3 conversion is accomplished by converting the data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. TX MLT-3 Driver The two binary data streams created at the MLT-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current MLT-3 signal. By scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels on the cable could peak beyond FCC limitations at frequencies related to repeated 5B sequences like continuous transmission of IDLE symbols. The scrambler output is combined with the NRZ 5B data from the FX Serial to Parallel converter via an XOR logic function. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. Final Version: DM9301FP-DS-F03 June 06, 2007 11 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter 100Base-TX to FX Operation TX Digital Adaptive Equalization The block diagram in figure 2 provides an overview of the functional blocks contained in the TX to FX media converter interface. When transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. In high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. This variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. In order to ensure quality transmission when employing MLT-3 encoding, the compensation must be Able to adapt to various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a given implementation requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. Conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. The TX to FX interface contains the following functional blocks: • • • • • • • • • • TX Digital Adaptive Equalization TX MLT-3 to NRZI TX Clock Recovery Module TX NRZI to NRZ Decoder TX Serial to Parallel Conversion TX Descrambler TX Code Group Alignment Monitor FX Parallel to Serial Conversion FX NRZ to NRZI FX PECL Transmitter TX Signal Detect The signal detects function meets the specifications mandated by the ANSI XT12 TP-PMD100Base-TX standards for both voltage thresholds and timing parameters. TX Link Status Monitor TX Codegroup Alignment Monitor 25M OSC/XTAL CGM 25M TPRXCLK 125M TPRXCLK PECLTXO +/- TX PECL TXMT TX NRZ to NRZI FX Parallel to Serial TX Descrambler TX Serial to Parallel TX NRZI to NRZ TX MLT-3 to NRZI TX Adaptive EQ TPRXI+/- TX CRM TX to FX Block Diagram Figure 2 12 Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. Status Monitor block. In turn, the Link Status Monitor block flashes the TX error LED (TXERRLED#). TX MLT-3 to NRZI Decoder TX Descrambler The DM9301FP decodes the MLT-3 information from the TX Digital Adaptive Equalizer into NRZI data. Because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. The TX Descrambler receives scrambled parallel data streams from the Serial to Parallel converter, descrambles the data streams, and presents the data streams to the Code Group alignment block. TX Clock Recovery Module The TX Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The TX Clock Recovery Module locks onto the data stream and extracts the 125 MHz reference clock. The extracted and synchronized clock and data are presented to the NRZI to NRZ Decoder. TX NRZI to NRZ Decoder The TX transmit data stream is required to be NRZI encoded in for compatibility with the TP-PMD standard for 100Base-TX transmission over Category-5 unshielded twisted pair cable. This conversion process must be reversed on the receive end. The NRZI to NRZ decoder receives the NRZI data stream from the TX Clock Recovery Module and converts it to a NRZ data stream to be presented to the TX Serial to Parallel conversion block. TX Serial to Parallel Converter The TX Serial to Parallel converter receives a serial data stream from the TX NRZI to NRZ decoder, and converts the data stream to parallel data to be presented to the TX descrambler. The parallel data format presented to the TX descrambler is 5B coded. TX Code Group Monitor The TX Code Group Alignment block receives nonaligned 5B data from the TX descrambler and monitors it for 5B code group violations. TX Code Group Alignment occurs after the J/K is detected, and subsequent data is monitored on a fixed boundary. If a violation is detected, the TX Code Group Monitor block signals the error to the Link Final Version: DM9301FP-DS-F03 June 06, 2007 FX Parallel to Serial Converter The FX Parallel to Serial Converter receives parallel 5B data from the TX de-scrambler and serializes it (converts it from a parallel to a serial data stream). The serialized data stream is then presented to the FX NRZ to NRZI Encoder block FX NRZ to NRZI Encoder After the transmit data stream has been serialized, the data must be NRZI encoded for compatibility with the standard for 100Base-FX. Link Monitor and LED Driver The Link Monitor block monitors both the TX and FX interfaces for link active, receive data and erring 5-bit stream. The Link Monitor has the ability to detect each interfaces link status. The TX will transmit either an idle symbol or a Halt symbol if the FX link is not established. Conversely the FX will transmit either an idle symbol or a Halt symbol if the TX link is not established. When an o Link” condition exists, the interface pin called LTNOLNK” will cause Halt symbols to be transmitted instead of idle symbols. The link active LED is a static indication of the TX and FX links. It will be true to indicate the presence of a link. The receive data and error LED are generated through a ne-Shot” so that even the smallest receive or error condition will be indicated. 13 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Absolute Maximum Ratings* Absolute Maximum Ratings (25°C) Symbol Parameter VCC Max. Supply Voltage VIN DC Input Voltage (VIN) VOUT DC Output Voltage(VOUT) Tstg Storage Temperature Rang (Tstg) PD Power Dissipation (PD) LT Lead Temp. (TL, Soldering, 10 sec.) ESD ESD rating (Rzap=1.5K,Czap=100pF) Min. --0.5 -0.5 -65 ------- Max. 7.0 5.5 5.5 +150 1 240 4000 Unit V V V °C W °C V Conditions Non-operating Operating Conditions Symbol Parameter DVCC,AVCC Supply Voltage Tc Case Temperature 100BASE-TX PD Min. 4.75 0 --- Max. --85 200 Unit 5.25 °C mA Conditions 5V (Power Dissipation) *Comments Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or any other 14 conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Final Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter DC Electrical Characteristics (VCC = 5V) Symbol Parameter Min. TTL Inputs (DPLXSEL, RESET# ) VIL Input Low Voltage VIH Input High Voltage 2.0 IIL Input Low Current -200 IIH Input High Current LED Driver Outputs (FXLINKLED#, TXLINKLED#, FXRXD#,RXRXD#) VOL Output Low Voltage VOH Output High Voltage 2.4 TPTX Receiver VICM RXI+/RXI- Input Common-Mode 1.5 Voltage TPTX Transmitter ITD100 100TXO+/- 100BASE-TX Mode │19│ Differential Output Current PECL FX Transmitter IFD100 PECLTX+/- 100BASE-FX Mode │19│ Differential Output Current Typ. Max. Unit 0.8 V V uA uA IIL = -400uA IIH = 100uA VIN = 0.4V VIN = 2.7V 0.4 V V IOL = 8mA IOH = -0.1mA 2.0 2.5 V 100 Ω Termination Across │20│ │21│ mA │20│ │21│ mA 100 VOH PECL Output Voltage – High VCC1.05 VCC0.88 V VOL PECL Output Voltage – Low VCC1.81 VCC1.62 V Final Version: DM9301FP-DS-F03 June 06, 2007 Conditions 15 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter AC Electrical Characteristics (Over full range of operating condition unless specified otherwise) Symbol Parameter Transmitter tTR/F 100TXO+/- Differential Rise/Fall Time tTM 100TXO+/- Differential Rise/Fall Time Mismatch tTDC 100TXO+/- Differential Output Duty Cycle Distortion tT/T 100TXO+/- Differential Output Peak-toPeak Jitter XOST 100TXO+/- Differential Voltage Overshoot PECL Transmitter (FX Transmit Interface) ptTR/F 100FXTD+/- Differential Rise/Fall Time ptTM 100FXTD+/- Differential Rise/Fall Time Mismatch ptTDC 100FXTD+/- Differential Output Duty Cycle Distortion ptPPJ 100FXTD+/- Differential Output Peak-toPeak Jitter ptDDJ 100FXTD+/- Differential Output Data Dependent Jitter Clock Specifications XNTOL TX Input Clock Frequency Tolerance (Oscillator or Crystal input frequency) XBTOL TX Output Clock Frequency Tolerance tPWH OSC Pulse Width High tPWL OSC Pulse Width Low tRPWH RX_CLK Pulse Width High tRPWL RX_CLK Pulse Width Low 16 Min. Typ. Max. Unit 3.0 -0.5 5.0 0.5 ns ns -0.5 0.5 ns 300 Conditions ps 5 % 1.0 -0.5 2.0 0.5 ns ns -0.5 0.5 ns 300 ps 2.0 ns -50 +50 ppm 25MHz Frequency -100 14 14 14 14 +100 ppm ns ns ns ns 25MHz Frequency Preliminary Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Timing Waveforms 100BASE-TX to FX Transmit Timing Diagram TPRXI+/tFXpd PECLTX+/- 100BASE-TX to FX Transmit Timing Parameters Symbol Parameter Min. tFXpd TPRXI+/- to PECLTX+/- Out (FX Latency) - Typ1. - Max. Unit 10 BT Typ1. - Max. Unit 10 BT Conditions 100BASE-FX to TX Transmit Timing Diagram PECLTX+/tTXpd TPRXI+/- 100BASE-FX to TX Transmit Timing Parameters Symbol tTXpd Parameter Min. PECLRX+/- to TPTXo+/- Out (TX Latency) - Conditions 5-Bit Symbol 100Base-TX/FX Transmit Timing Diagram TXCLK tTXS tTXh TXD [4:0] 100TX+/- tTXD pdtpo tTXDpdfxo tTXrft 100FX+/- Final Version: DM9301FP-DS-F03 June 06, 2007 17 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter 5-Bit Symbol 100Base-TX/FX Transmit Timing Parameters Symbol Parameter Min. tTXs tTXh TXD[4:0] Setup To TX_CLK High TXD[4:0] Hold From TX_CLK High TXD[4:0] Sampled To TPTXO (TXD to TP Latency) TXD[4:0] Sampled To PECLTXO (TXD to FX Latency) 100TX Driver Rise/Fall Time tTXDpdtpo tTXDpdfxo tTXr/f Max. Unit 11 0 Typ.1 - - ns ns - - 6 BT - - 4 BT 3 4 5 ns Conditions 90% To 10%, Into 100ohm Differential 1. Typical values are at 25and are for design aid only; not guaranteed and not subject to production testing. 5-Bit Symbol 100Base-TX/FX Receive Timing Diagram RXCLK tRXS tRXh RXD [4:0] tRXDpdtxi tRXD pdfxi TX RXI+/FX RXI+/- 5-Bit Symbol 100Base-TX/FX Receive Timing Parameter Symbol tRXs tRXh tRXDpdtxi tRXDpdfxi 18 Parameter RXD[4:0) Setup To RX_CLK High RXD[4:0]Hold From RX_CLK High TXRXI In To RXD[0:3] Out (Rx Latency) PECLRDI In To RXD[4:0] Out (Rx Latency) Min. Max. Unit 10 Typ1. - - ns 10 - - ns - - 6 BT - - 4 BT Conditions Preliminary Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter MII Application Circuit: DM9301FP QFP (For Reference Only) Final Version: DM9301FP-DS-F03 June 06, 2007 19 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter MII Application Circuit: DM9301FP QFP (For Reference Only) 470 ohm R1 VCC place caps close to U1 pins Isolation Barrier. No Power under this area. All these components and their traces should not intersect other areas. 470 ohm R2 VCC D1 470 ohm R3 C1 C2 C3 C4 10uf SMD-B .1uf .01uf .1uf 470 ohm R4 VCC 470 ohm R6 RJ45 J1 D2 75 1% DVCC TPO5 GND TXERRLED# VCC 7 6 5 4 75 1% C8 VCC 10K 81 GND 82 GND 83 GND 84 RESET# 85 VCC 86 C9 10uf S1 SW PUSHBUTTON 87 88 SMD-B 89 90 91 GND 92 93 VCC 94 95 TX CKT POWER/GROUND AREA 96 97 C22 98 .1uf 99 100 GND TXD2 TPMUX TXD3 TPI0 TXD4 DGND TPI1 DM9301F (TCO) MUXCTL0 TPI3 MUXCTL1 TPEN CONFIGA DVCC DVCC CONFIGB FXALPBK FXDLPBK TXALPBK TXDLPBK HLTNOLNK DGND DGND AGND AGND AGND AVCC .1uf GND 49.9 1% 49 GND GND 48 GND 47 GND 46 VCC 45 GND 44 GND 43 GND TPRXI- 2 TPRXI+ 1 8 9 7 10 6 11 5 12 4 13 3 14 2 15 1 16 9 GND 10 11 12 13 R10 75 1% 14 15 TPTXO- 16 TPTXO+ PE68515 GND VCC 42 GND 41 BPSCRAM 40 GND 39 GND 38 3 .1uf 1 2 3 4 VCC 36 GND 35 GND Disable Scrambler CON4 GND 37 J? GND Pop Table For : 3.3V 34 1 2 3 4 HLTNOLNK 33 GND 32 GND 31 VCC R19 R20 R21 R22 R23 R24 optic U3 C10 C11 R25 R26 R12 R13 R27 R28 R29 R30 Halt If No Link CON4 GND R20 OSC/XTL# R13 30 AGND OSC/X1 AVCC X2 29 28 PECLRXI+ PECLRXI- PECLSD+ 62/ 69.8 R19 0 Ohm R12 VCC 3.3V 0 Ohm GND GND X2 Y1 C13 18pF 49.9 1% Load ONLY R12 OR R13 R12=+5V for HFBR Large Optic R13=3.3V for Siemans V23812 Optic. 25M L3 1uH C14 18pF L4 1uH C15 GND Place these components as close to Optics as possible. 182 69.8 182 69.8 13.2K 127 FX1 In In In 127 127 out 0 83 83 19.8K 83 300 62 300 62 130 82 FX2 out out out 82 82 0 out 130 130 374 130 C16 GND .1uf 300/ 182 VCC 5.0V VCC J? VCC PECLSD+ PECLRXI+ PECLRXI- PECLSD- OSC/X1 27 26 25 24 23 PECLSD- AGND PECLTXO+ PECLTXO- AVCC 22 21 20 18 19 GND PECLTXO- R17 R16 49.9 1% VCC AGND AVCC AGND 17 GND 16 15 GND VCC TPTXO- AGND AGND TPTXO+ 14 13 GND 12 AVCC 10 VCC GND 11 BGRET 9 AVCC AGND BGREF 8 6 7 VCC AGND R18 VCC PECLTXO+ 49.9 1% C12 TPTXO+ GND TPTXO- .1uf R15 .01uf BFRET .01uf 6.49K 1% .1uf GND R14 .01uf 5 TPRXI+ C29 BFREF C28 GND C27 TPRXI+ 1 C26 50 C5 GND place caps close to U1 pins C25 BPSCRAM TPI2 AVCC Digital Ckt Power & Ground Area Locate near U1's VCC & Ground Pins Physically place caps on SOLDER SIDE. DVCC 4 .01uf DVCC VCC C21 TXD1 RESET# AVCC .1uf TXD0 TRIDRV TPRXI- C20 .01uf TESTMODE 3 C19 .1uf FRCFXSD 2 C18 DGND TPRXI- C17 .01uF DGND VCC VCC BYPASS CAPACITOR FOR U1 DVCC DGND U2 8 R9 VCC 75 1% .1uf /1KV GND R11 R7 U1 51 52 53 54 TPO5 DGND TPO4 R8 TXERRLED# TPO2 TPO3 VCC TPO4 55 56 58 57 TPO3 TPO2 DVCC TPO0 TPO1 GND TXRCVLED# GND 59 TPO1 DGND 60 62 63 61 TPO0 DGND TXRCVLED# VCC TXLNKLED# 64 TPO6 LED D4 TXLNKLED# GND FXLNKLED# FXRCVLED# TPO6 65 66 DVCC 67 69 68 DGND FXRCVLED# RXCLK D6 FXLNKLED# RXD4 TXCLK RXCLK 70 71 TXCLK RXD3 VCC GND 72 DGND 74 75 GND RXD1 RXD0 RXD2 76 77 78 79 73 RXD4 RXD3 10uf GND DVCC .1uf D3 RXD2 Ferrite Hi current SMD-B C7 RXD1 C6 L2 Power Jack 80 VCC RXD0 Ferrite Hi current FXERRLED# L1 DGND Plus 5 volt D.C. input J2 470 ohm R5 FXERRLED# D5 1 2 3 4 5 6 7 8 Both LEDs in one package. D2 is upper LED (TxLnk) GND C23 .1uf .1uf R21 GND 300/ 182 This node will be 3.3V or 5V depending on strapping. 3.3V SOT-223 800ma R22 62/ 69.8 GND HFBR5103T FX2 VCC_R VCC 2 C11 1 U3 PECLTXO+ 3.3V C10 .1uf 10uf SMD-B GND 130/13.2K 82/ 127 R23 R25 82/ 127 PECLRXI- GND R26 82/127 C24 PECLRXI+ R24 .1uf Load ONLY for 3.3V Siemans V23812 Optics. GND 9 8 7 6 5 4 3 2 1 PECLTXO- R27 130/83 R28 130/ 83 GND R29 374/19.8K GND PECLSD+ Vout PECLSD- Vin GND VCC_T 3 PECLTXO+ PECLTXOPECLSD+ PECLRXIPECLRXI+ GND VCC_T VCC_R GND 9 8 7 6 5 4 3 2 1 VCC_T VCC_R PECLSD+ PECLRXI- V23818-C8-V10 FX1 PECLRXI+ GND R30 130 /83 DAVICOM SEMICONDUCTOR, INC. GND Title 9301 Media Converter Size Document Number Custom Date: 20 Monday , April 24, 2000 Rev 1.1 DM9301.DSN Sheet 1 of 1 Preliminary Version: DM9301FP-DS-F03 June 06, 2007 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Package Information 100 Pins QFP Package Outline Information: Symbol A A1 A2 B C D D1 E E1 e L L1 y θ Dimension in mm Min Nom Max － － 3.40 0.25 － － 2.73 2.85 2.97 0.25 0.30 0.38 0.13 0.15 0.23 23.00 23.20 23.40 19.90 20.00 20.10 17.00 17.20 17.40 13.90 14.00 14.10 0.65 BSC 0.73 0.88 1.03 1.60 BSC － － 0.10 o o 0 － 7 Dimension in inch Min Nom Max － － 0.134 0.010 － － 0.107 0.112 0.117 0.010 0.012 0.015 0.005 0.006 0.009 0.906 0.913 0.921 0.783 0.787 0.791 0.669 0.677 0.685 0.547 0.551 0.555 0.026 BSC 0.029 0.035 0.041 0.063 BSC － － 0.004 o o 0 － 7 1. Dimension D1 and E1 do not include resin fin. 2. All dimensions are base on metric system. 3. General appearance spec should base on its final visual inspection spec. Final Version: DM9301FP-DS-F03 June 06, 2007 21 DM9301FP 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter Ordering Information Part Number DM9301FP Pin Count 100 Package QFP (Pb-Free) Disclaimer DAVICOM‘s terms and conditions printed on the order acknowledgment govern all sales by DAVICOM. DAVICOM will not be bound by any terms inconsistent with these unless DAVICOM agrees otherwise in writing. Acceptance of the buyer’s orders shall be based on these terms. Company Overview The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHER, DAVICOM MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. DAVICOM reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by DAVICOM for such applications. Please note that application circuits illustrated in this document are for reference purposes only. DAVICOM Semiconductor, Inc. develops and manufactures integrated circuits for integration into data communication products. Our mission is to design and produce IC products that are the industry’s best value for Data, Audio, Video, and Internet/Intranet applications. To achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. Products We offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. Our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and Ethernet networking standards. Contact Windows For additional information about DAVICOM products, contact the sales department at: Headquarters Hsin-chu Office: No.6 Li-Hsin Rd. VI, Science-based Industrial Park, Hsin-chu City, Taiwan, R.O.C. TEL: 886-3-5798797 FAX: 886-3-5646929 Davicom America Corp 4633 Old Ironsides Dr., STE 318 Santa Clara, CA 95054, USA Tel: 408.980.9108 Fax:408.980.9236 WARNING Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. 22 Preliminary Version: DM9301FP-DS-F03 June 06, 2007