ELPIDA EDS2532AABH-1AR2

DATA SHEET
256M bits SDRAM
EDS2532AABH-1AR2 (8M words × 32 bits)
Pin Configurations
The EDS2532AABH is a 256M bits SDRAM organized
as 2,097,152 words × 32 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
It is packaged in 90-ball FBGA.
/xxx indicate active low signal.
EO
Description
Features
90-ball FBGA
1
2
3
4
5
6
7
8
9
A
DQ26 DQ24 VSS
VDD DQ23 DQ21
DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
B
•
•
•
•
•
L
3.3V power supply
Clock frequency: 100MHz (max.)
Single pulsed /RAS
×32 organization
4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full
page
• 2 variations of burst sequence
⎯ Sequential (BL = 1, 2, 4, 8, full page)
⎯ Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Address
⎯ 4K Row address /512 column address
• Refresh cycles
⎯ 4096 refresh cycles/32ms
• Auto refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
C
D
E
VDDQ DQ31
NC
NC
DQ16 VSSQ
VSS DQM3
A3
A2
DQM2 VDD
F
G
A4
A5
A6
A10
A0
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
/CS
/RAS
NC
NC
/CAS
/WE DQM0
VSS
VDD
DQ7 VSSQ
VSSQ DQ10 DQ9
DQ6
DQ5 VDDQ
VSSQ DQ12 DQ14
DQ1
DQ3 VDDQ
H
J
K
Pr
DQM1
L
VDDQ DQ8
M
N
P
od
DQ11 VDDQ VSSQ
VDDQ VSSQ DQ4
R
DQ13 DQ15 VSS
VDD
DQ0
DQ2
(Top view)
Address inputs
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
DQ mask enable
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
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A0 to A11
BA0, BA1
DQ0 to DQ31
/CS
/RAS
/CAS
/WE
DQM0 to DQM3
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Document No. E0517E20 (Ver. 2.0)
Date Published October 2004 (K) Japan
URL: http://www.elpida.com
This product became EOL in April, 2007.
©Elpida Memory, Inc. 2004
EDS2532AABH-1AR2
Ordering Information
Part number
Supply
voltage
EDS2532AABH-1AR2-E 3.3V
Organization
(words × bits) Internal Banks
Clock frequency
MHz (max.)
/CAS latency
Package
8M × 32
100
2, 3
90-ball FBGA
4
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Data Sheet E0517E20 (Ver. 2.0)
2
EDS2532AABH-1AR2
CONTENTS
Description .................................................................................................................................................... 1
Features ........................................................................................................................................................ 1
Pin Configurations......................................................................................................................................... 1
Ordering Information ..................................................................................................................................... 2
Electrical Specifications ................................................................................................................................ 4
Block Diagram............................................................................................................................................... 9
Pin Function ................................................................................................................................................ 10
Command Operation................................................................................................................................... 11
Simplified State Diagram ............................................................................................................................ 19
EO
Mode Register Configuration ...................................................................................................................... 20
Power-up sequence .................................................................................................................................... 22
Operation of the SDRAM ............................................................................................................................ 23
Timing Waveforms ...................................................................................................................................... 39
Package Drawing........................................................................................................................................ 45
Recommended Soldering Conditions ......................................................................................................... 46
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Data Sheet E0517E20 (Ver. 2.0)
3
EDS2532AABH-1AR2
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, execute power up sequence and initialization sequence before proper device operation is achieved
(refer to the Power up sequence).
Absolute Maximum Ratings
Symbol
Rating
Unit
Voltage on any pin relative to VSS
VT
–0.5 to VDD + 0.5 (≤ 4.6 (max.))
V
Supply voltage relative to VSS
VDD
–0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating ambient temperature
TA
0 to +70
°C
Tstg
–55 to +125
°C
EO
Parameter
Storage temperature
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Parameter
Symbol
min.
max.
Unit
Notes
VDD, VDDQ
3.1
3.5
V
1
VSS, VSSQ
0
0
V
2
L
Supply voltage
Input high voltage
VIH
2.0
VDD + 0.3
V
3
Input low voltage
VIL
–0.3
0.8
V
4
The supply voltage with all VDD and VDDQ pins must be on the same level.
The supply voltage with all VSS and VSSQ pins must be on the same level.
VIH (max.) = VDD + 1.5V (pulse width ≤ 5ns).
VIL (min.) = VSS – 1.5V (pulse width ≤ 5ns).
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Notes: 1.
2.
3.
4.
Data Sheet E0517E20 (Ver. 2.0)
4
EDS2532AABH-1AR2
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.1V to 3.5V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol
Operating current
Grade
Unit
IDD1
125
mA
Standby current in power down
IDD2P
3
mA
Standby current in power down
(input signal stable)
IDD2PS
2
mA
Standby current in non power down
IDD2N
20
mA
Standby current in non power down
(input signal stable)
IDD2NS
9
mA
Active standby current in power down
IDD3P
4
mA
Active standby current in power down
(input signal stable)
IDD3PS
3
mA
Active standby current in non power down
IDD3N
50
mA
Active standby current in non power down
(input signal stable)
IDD3NS
40
mA
Burst operating current
IDD4
150
mA
Refresh current
IDD5
270
mA
L
EO
max.
Test condition
Burst length = 1
tRC = tRC (min.)
CKE = VIL,
tCK = tCK (min.)
CKE = VIL, tCK = ∞
Notes
1, 2, 3
6
7
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
CKE = VIL,
tCK = tCK (min.)
8
CKE = VIL, tCK = ∞
2, 7
4
1, 2, 6
CKE, /CS = VIH,
tCK = tCK (min.)
CKE = VIH, tCK = ∞,
/CS = VIH
tCK = tCK (min.),
BL = 4
2, 8
tRC = tRC (min.)
3
1, 2, 4
1, 2, 5
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Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0517E20 (Ver. 2.0)
5
EDS2532AABH-1AR2
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.1V to 3.5V, VSS, VSSQ = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Note
Input leakage current
ILI
–2
2
µA
0 ≤ VIN ≤ VDD
Output leakage current
ILO
–5
5
µA
0 ≤ VOUT ≤ VDD, DQ = disable
Output high voltage
VOH
2.4
—
V
IOH = –2 mA
Output low voltage
VOL
—
0.4
V
IOL = 2 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.1V to 3.5V)
Symbol
Pins
min.
typ.
max.
Unit
Notes
Input capacitance
CI1
CLK
1.5
—
3.0
pF
1, 2, 4
CI2
Address, CKE, /CS,
/RAS, /CAS, /WE,
DQM
1.5
—
3.0
pF
1, 2, 4
CI/O
DQ
3.0
—
5.5
pF
1, 2, 3, 4
EO
Parameter
Data input/output
capacitance
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
DQM = VIH to disable DOUT.
This parameter is sampled and not 100% tested.
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Data Sheet E0517E20 (Ver. 2.0)
6
EDS2532AABH-1AR2
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.1V to 3.5V, VSS, VSSQ = 0V)
-1AR2
Parameter
Symbol
min.
max.
Unit
Notes
System clock cycle time
(CL = 2)
tCK
10
—
ns
1
(CL = 3)
tCK
10
—
ns
1
tCH
3
—
ns
1
CLK low pulse width
tCL
3
—
ns
1
Access time from CLK
tAC
—
6
ns
1, 2
Data-out hold time
tOH
2.0
—
ns
1, 2
CLK to Data-out low impedance
tLZ
0
—
ns
1, 2, 3
CLK to Data-out high impedance
tHZ
—
6
ns
1, 4
Input setup time
tSI
2.0
—
ns
1
Input hold time
tHI
1.0
—
ns
1
Ref/Active to Ref/Active command period
tRC
70
—
ns
1
Active to Precharge command period
tRAS
50
120000
ns
1
Active command to column command (same bank)
tRCD
20
—
ns
1
Precharge to active command period
tRP
20
—
ns
1
Write recovery or data-in to precharge lead time
—
ns
1
1
EO
CLK high pulse width
20
tDAL
2CLK + 20ns —
Active (a) to Active (b) command period
tRRD
20
—
ns
Transition time (rise and fall)
tT
0.5
5.0
ns
Refresh period (4096 refresh cycles)
tREF
—
32
ms
L
tDPL
Last data into active latency
AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
Access time is measured at 1.4V. Load condition is CL = 30pF.
tLZ (min.) defines the time at which the outputs achieves the low impedance state.
tHZ (max.) defines the time at which the outputs achieves the high impedance state.
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Notes: 1.
2.
3.
4.
Data Sheet E0517E20 (Ver. 2.0)
7
EDS2532AABH-1AR2
Test Conditions
• Input and output timing reference levels: 1.4V
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
I/O
2.0 V
0.8 V
CL
tT
tT
Output load
Relationship Between Frequency and Minimum Latency
-1AR2
Frequency (MHz)
100
EO
Parameter
Symbol
10
Unit
Note
Active command to column command (same bank)
lRCD
2
tCK
1
Active command to active command (same bank)
lRC
7
tCK
1
Active command to precharge command (same bank)
lRAS
5
tCK
1
Precharge command to active command (same bank)
lRP
2
tCK
1
Write recovery or data-in to precharge command (same bank)
lDPL
2
tCK
1
Active command to active command (different bank)
lRRD
2
tCK
1
Last data in to active command (Auto precharge, same bank)
lDAL
4
tCK
= [lDPL + lRP]
Precharge command to high impedance
(CL = 2)
lHZP
2
tCK
(CL = 3)
lHZP
3
tCK
L
tCK (ns)
Pr
Last data out to active command (Auto precharge, same bank)
lAPR
1
tCK
Last data out to precharge (early precharge)
(CL = 2)
lEP
–1
tCK
(CL = 3)
lEP
–2
tCK
Column command to column command
lCCD
1
tCK
Write command to data in latency
lWCD
0
tCK
DQM to data out
CKE to CLK disable
Register set to active command
/CS to command disable
Power down exit to command input
lDID
0
tCK
lDOD
2
tCK
lCLE
1
tCK
lMRD
2
tCK
lCDD
0
tCK
lPEC
1
tCK
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Note: 1. lRCD to lRRD are recommended value.
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DQM to data in
Data Sheet E0517E20 (Ver. 2.0)
8
EDS2532AABH-1AR2
Block Diagram
CLK
CKE
Clock
Generator
Bank 3
Bank 2
Bank 1
Mode
Register
Data Control Circuit
Input & Output
Buffer
/WE
DQM
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
Latch Circuit
/CAS
Bank 0
Sense Amplifier
Control Logic
/RAS
Command Decoder
EO
/CS
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
Address
DQ
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Data Sheet E0517E20 (Ver. 2.0)
9
EDS2532AABH-1AR2
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
EO
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
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A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A8 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
[Bank Select Signal Table]
Bank 0
Bank 1
Bank 2
Remark: H: VIH. L: VIL.
BA0
BA1
L
L
H
L
L
H
H
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Bank 3
Pr
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal. (See Bank Select Signal Table)
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
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DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,
DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM
high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In
write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0517E20 (Ver. 2.0)
10
EDS2532AABH-1AR2
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Symbol
n–1
n
/CS
/RAS
/CAS
/WE
BA1,BA0 A10
A0 to A11
Device deselect
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
Burst stop
BST
H
×
L
H
H
L
×
×
×
Read
READ
H
×
L
H
L
H
V
L
V
Read with auto precharge
READA
H
×
L
H
L
H
V
H
V
Write
WRIT
H
×
L
H
L
L
V
L
V
Write with auto precharge
WRITA
H
×
L
H
L
L
V
H
V
Bank activate
ACT
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
EO
Function
Precharge all banks
PALL
H
×
L
L
H
L
×
H
×
Mode register set
MRS
H
×
L
L
L
L
L
L
V
Remark: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input.
L
Device deselect command [DESL]
When this command is set (/CS is High), the SDRAM ignore command input at the clock. However, the internal
status is held.
Pr
No operation [NOP]
This command is not an execution command. However, the internal operations continue.
Burst stop command [BST]
This command can stop the current burst operation.
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Column address strobe and read command [READ]
This command starts a read operation. In addition, the start address of burst read is determined by the column
address (see Address Pins Table in Pin Function) and the bank select address (BA0, BA1). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8.
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Column address strobe and write command [WRIT]
This command starts a write operation. When the burst write mode is selected, the column address (see Address
Pins Table in Pin Function) and the bank select address (BA0, BA1) become the burst write start address. When the
single write mode is selected, data is only written to the location specified by the column address (see Address Pins
Table in Pin Function) and the bank select address (BA0, BA1).
Write with auto-precharge [WRITA]
This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a
single write operation.
Data Sheet E0517E20 (Ver. 2.0)
11
EDS2532AABH-1AR2
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (A0 to A11). (See
Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
EO
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF]
This command starts the refresh operation. For details, refer to the CKE truth table section.
L
Mode register set [MRS]
The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins
(A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the mode register configuration. After
power on, the contents of the mode register are undefined, execute the mode register set command to set up the
mode register.
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Data Sheet E0517E20 (Ver. 2.0)
12
EDS2532AABH-1AR2
DQM Truth Table
CKE
DQM
0
1
2
3
Function
Symbol
n–1
n
Data write / output enable
ENB
H
×
L
L
L
L
Data mask / output disable
MASK
H
×
H
H
H
H
DQ0 to DQ7 write enable/output enable
ENB0
H
×
L
×
×
×
DQ8 to DQ15 write enable/output enable
ENB1
H
×
×
L
×
×
DQ16 to DQ23 write enable/output enable
ENB2
H
×
×
×
L
×
DQ24 to DQ31 write enable/output enable
ENB3
H
×
×
×
×
L
MASK0
H
×
H
×
×
×
DQ8 to DQ15 write inhibit/output disable
MASK 1
H
×
×
H
×
×
DQ16 to DQ23 write inhibit/output disable
MASK 2
H
×
×
×
H
×
DQ24 to DQ31 write inhibit/output disable
MASK 3
H
×
×
×
×
H
EO
DQ0 to DQ7 write inhibit/output disable
Remark: H: VIH. L: VIL. ×: VIH or VIL
Write: lDID is needed.
Read: lDOD is needed.
CKE Truth Table
Activating
Any
Clock suspend
Function
L
Current state
CKE
Symbol
Clock suspend mode entry
n–1
n
/CS
/RAS
/CAS
/WE
Address
H
L
×
×
×
×
×
Clock suspend mode
L
L
×
×
×
×
×
Clock suspend mode exit
L
H
×
×
×
×
×
H
H
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
Power down
Power down exit
L
H
H
×
×
×
×
L
H
L
H
H
H
×
Idle
CBR (auto) refresh command
REF
Pr
Remark: H: VIH. L: VIL. ×: VIH or VIL
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Data Sheet E0517E20 (Ver. 2.0)
13
EDS2532AABH-1AR2
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the
SDRAM.
The following table assumes that CKE is high.
Current state
/CS
Precharge
H
×
L
H
L
H
L
/WE
Address
Command
Operation
×
×
×
DESL
Enter IDLE after tRP
H
H
×
NOP
Enter IDLE after tRP
H
L
×
BST
ILLEGAL
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*3
L
L
H
H
BA, RA
ACT
ILLEGAL*3
L
L
H
L
BA, A10
PRE, PALL
NOP*5
L
L
L
H
×
REF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
EO
Idle
/RAS
/CAS
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*4
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*4
L
H
H
BA, RA
ACT
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF
Refresh
L
L
L
L
MODE
MRS
Mode register set*8
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
Begin read*6
L
H
L
L
BA, CA, A10
WRIT/WRITA
Begin write*6
L
L
H
H
BA, RA
ACT
Other bank active
ILLEGAL on same bank*2
L
L
H
L
BA, A10
PRE, PALL
Precharge*7
L
L
L
H
×
REF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
od
Read
L
Pr
Row active
L
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Continue burst read to /CAS
latency and New read
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst read/start write
Other bank active
ILLEGAL on same bank*2
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H
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE, PALL
Term burst read and Precharge
L
L
L
H
×
REF
ILLEGAL
L
L
L
L
MODE
MRS
Data Sheet E0517E20 (Ver. 2.0)
14
ILLEGAL
EDS2532AABH-1AR2
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Read with autoprecharge
H
×
×
×
×
DESL
L
H
H
H
×
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*3
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*3
L
L
H
H
BA, RA
ACT
Other bank active
ILLEGAL on same bank*2
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*3
L
L
L
H
×
REF
ILLEGAL
EO
Write
L
L
L
L
MODE
MRS
ILLEGAL
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop
L
H
L
H
BA, CA, A10
READ/READA
Term burst and New read
L
H
L
L
BA, CA, A10
WRIT/WRITA
Term burst and New write
L
H
H
BA, RA
ACT
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and Precharge*1
L
L
L
H
×
REF
ILLEGAL
L
L
L
L
MODE
MRS
L
H
×
L
H
L
H
L
H
L
H
L
L
L
×
×
×
DESL
ILLEGAL
Continue burst to end and
precharge
Continue burst to end and
precharge
H
H
×
NOP
H
L
×
BST
ILLEGAL
L
H
BA, CA, A10
READ/READA
ILLEGAL*3
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*3
H
H
BA, RA
ACT
Other bank active
ILLEGAL on same bank*3
L
H
L
BA, A10
PRE, PALL
ILLEGAL*3
L
L
L
H
×
REF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Enter IDLE after tRC
L
H
H
H
×
NOP
Enter IDLE after tRC
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*4
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*4
L
L
H
H
BA, RA
ACT
ILLEGAL*4
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF
ILLEGAL
L
L
L
L
MODE
MRS
Data Sheet E0517E20 (Ver. 2.0)
15
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Pr
Refresh (auto-refresh)
Continue burst to end and
precharge
Continue burst to end and
precharge
H
L
Write with autoprecharge
Operation
ILLEGAL
EDS2532AABH-1AR2
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*4
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*4
L
L
H
H
BA, RA
ACT
Bank and row active*9
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF
Refresh*9
L
L
L
L
MODE
MRS
Mode register set*8
H: VIH. L: VIL. ×: VIH or VIL
An interval of tDPL is required between the final valid data input and the precharge command.
If tRRD is not satisfied, this operation is illegal.
Illegal for same bank, except for another bank.
Illegal for all banks.
NOP for same bank, except for another bank.
Illegal if tRCD is not satisfied.
Illegal if tRAS is not satisfied.
MRS command must be issued after DOUT finished, in case of DOUT remaining.
Illegal if lMRD is not satisfied.
L
EO
Remark:
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
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Pr
Data Sheet E0517E20 (Ver. 2.0)
16
EDS2532AABH-1AR2
Command Truth Table for CKE
CKE
Current State
n–1 n
Power down
H
All banks idle
/CS
/RAS /CAS /WE Address
Operation
×
×
×
×
×
INVALID, CLK (n – 1) would exit power down
L
H
H
×
×
×
L
H
L
H
H
H
×
EXIT power down
L
L
×
×
×
×
×
Continue power down mode
×
Notes
EXIT power down
H
H
H
×
×
×
Refer to operations in Function Truth Table
H
H
L
H
×
×
Refer to operations in Function Truth Table
H
H
L
L
H
×
Refer to operations in Function Truth Table
H
L
L
L
H
×
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
×
×
×
Begin power down next cycle
H
L
L
H
×
×
Refer to operations in Function Truth Table
H
L
L
L
H
×
Refer to operations in Function Truth Table
EO
H
H
CBR (auto) Refresh
L
L
L
L
L
OPCODE Refer to operations in Function Truth Table
L
H
×
×
×
×
×
Exit power down next cycle
L
L
×
×
×
×
×
Power down
H
×
×
×
×
×
×
Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Clock suspend
Any state other than
H
H
×
×
×
×
listed above
H
L
×
×
×
×
×
Begin clock suspend next cycle
L
H
×
×
×
×
×
Exit clock suspend next cycle
L
L
×
×
×
×
×
Maintain clock suspend
Row active
L
H
1
1
Refer to operations in Function Truth Table
2
Pr
Remark: H: VIH. L: VIL. ×: VIH or VIL
Notes: 1. Power down can be entered only from all banks idle. Clock suspend can be entered only from following
states, row active, read, read with auto-precharge, write and write with auto precharge.
2. Must be legal command as defined in Function Truth Table.
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Data Sheet E0517E20 (Ver. 2.0)
17
EDS2532AABH-1AR2
Clock suspend mode entry
The SDRAM enters clock suspend mode from active mode by setting CKE to Low. If command is input in the clock
suspend mode entry cycle, the command is valid. The clock suspend mode changes depending on the current
status (1 clock before) as shown below.
ACTIVE clock suspend
This suspend mode ignores inputs after the next clock by internally maintaining the bank active status.
READ suspend and READ with Auto-precharge suspend
The data being output is held (and continues to be output).
WRITE suspend and WRIT with Auto-precharge suspend
In this mode, external signals are not accepted. However, the internal state is held.
EO
Clock suspend
During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit
The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state.
L
IDLE
In this state, all banks are not selected, and completed precharge operation.
Pr
Auto-refresh command [REF]
When this command is input from the IDLE state, the SDRAM starts auto-refresh operation. (The auto-refresh is the
same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank
select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is
updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh
command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically
performed after auto-refresh, no precharge command is required after auto-refresh.
Power down mode entry
When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down
mode, power consumption is suppressed by cutting off the initial input circuit.
od
Power down exit
When this command is executed at the power down mode, the SDRAM can exit from power down mode. After
exiting from power down mode, the SDRAM enters the IDLE state.
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Data Sheet E0517E20 (Ver. 2.0)
18
EDS2532AABH-1AR2
Simplified State Diagram
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
ROW
ACTIVE
BST
BST
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
READ
WRITE
WITH
AP
READ
READ
WITH AP
WRITE
WITH AP
CKE_
READ
CKE
WRITEA
READ
WITH AP
CKE_
READA
CKE
CKE
PRECHARGE
READ
SUSPEND
READA
SUSPEND
PRECHARGE
Pr
POWER
APPLIED
WRITE
WITH AP
Read
PRECHARGE
CKE_
WRITEA
SUSPEND
READ
WITH
AP
WRITE
CKE
L
EO
CKE_
CKE
POWER
ON
PRECHARGE
PRECHARGE
od
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
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Data Sheet E0517E20 (Ver. 2.0)
19
EDS2532AABH-1AR2
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode,
and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
EO
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
A11
A10
A9
A8
L
BA1 BA0
OPCODE
A6
A6
0
A5
A4
LMODE
A3
0
0
R
0
Sequential
0
0
1
R
1
Interleave
0
1
0
0
1
1
1
X
X
R
0
X
X
0
0
R
1
0
X
X
0
0
R
1
1
X
X
X
X
X
X
0
0
0
1
R
R
X
X
X
X
1
0
X
X
X
X
1
1
BT=1
0
0
0
2
0
0
1
2
2
3
0
1
0
4
4
0
1
1
8
8
1
0
0
R
R
Burst read and burst write
Burst read and single write
R
Burst length
BT=0
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
Mode Register Set Timing
Data Sheet E0517E20 (Ver. 2.0)
20
1
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0
1
A2 A1 A0
1
Write mode
0
A0
BL
od
A8
A1
A3 Burst type
A5 A4 CAS latency
0
A9
A2
BT
Pr
BA1 BA0 A11 A10
0
0
0
0
A7
EDS2532AABH-1AR2
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Starting Ad. Addressing(decimal)
Sequential Interleave
A1
A0
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Sequential
Interleave
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
A0 Sequential
Interleave
0
0
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
EO
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
Burst Sequence
L
Full page burst is available only for sequential addressing. The addressing sequence is started from the column
address that is asserted by read/write command. And the address is increased one by one.
It is back to the address 0 when the address reaches at the end of address 511. “Full page burst” stops the burst
read/write with burst stop command.
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Data Sheet E0517E20 (Ver. 2.0)
21
EDS2532AABH-1AR2
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these
pins go high before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
EO
When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
VDD, VDDQ
Initialization sequence
Power up sequence
100 μs
200 μs
0V
L
CKE, DQM
Low
CLK
Low
/CS, DQ
Low
Pr
Power stabilize
Power-up sequence and Initialization sequence
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Data Sheet E0517E20 (Ver. 2.0)
22
EDS2532AABH-1AR2
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
EO
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
CLK
Command
DQ
READ
ACT
L
Address
tRCD
Row
Column
out 0
CL = 2
CL = 3
out 1
out 2
out 3
out 0
out 1
out 2
out 3
Pr
CL = /CAS latency
Burst Length = 4
/CAS Latency
CLK
tRCD
ACT
READ
Address
Row
Column
BL = 1
out 0
out 0 out 1
DQ
BL = 2
od
Command
out 0 out 1 out 2 out 3
BL = 4
out 0 out 1 out 2
out 3 out 4 out 5 out 6 out 7
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BL = 8
BL : Burst Length
/CAS Latency = 2
Burst Length
Data Sheet E0517E20 (Ver. 2.0)
23
EDS2532AABH-1AR2
Write operation
Burst write or single write mode is selected by the OPCODE of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the
same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4
and 8, like burst read operations. The write start address is specified by the column address and the bank select
address at the write command set cycle.
CLK
tRCD
Command
ACT
WRIT
Address
Row
Column
in 0
EO
BL = 1
DQ
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
BL = 2
BL = 4
in 4
in 5
in 6
in 7
BL = 8
CL = 2, 3
Burst write
L
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CLK
Command
DQ
WRIT
Pr
Address
ACT
tRCD
Row
Column
in 0
Single write
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Data Sheet E0517E20 (Ver. 2.0)
24
EDS2532AABH-1AR2
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
EO
CL=2 Command
ACT
READA
ACT
lRAS
DQ
CL=3 Command
out0
out1
out2
out3
lAPR
ACT
READA
ACT
lRAS
DQ
out0
out1
L
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge "
out2
out3
lAPR
".
Burst Read (BL = 4)
CLK
ACT
ACT
WRITA
od
Command
Pr
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
lRAS
DQ
in0
in1
in2
in3
lDAL
Burst Write (BL = 4)
Data Sheet E0517E20 (Ver. 2.0)
25
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Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
EDS2532AABH-1AR2
CLK
Command
ACT
ACT
WRITA
lRAS
DQ
in
lDAL
EO
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Single Write
L
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Pr
Data Sheet E0517E20 (Ver. 2.0)
26
EDS2532AABH-1AR2
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
READ
Command
BST
DQ
(CL = 2)
out
EO
DQ
(CL = 3)
out
out
out
out
High-Z
out
High-Z
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
CLK
Command
L
DQ
WRITE
in
BST
High-Z
in
in
in
Burst Stop at Write
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Pr
Data Sheet E0517E20 (Ver. 2.0)
27
EDS2532AABH-1AR2
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
ACT
Address
Row
READ
READ
Column A Column B
BS
EO
DQ
Bank0
Active
out A0 out B0 out B1 out B2 out B3
CL = 3
BL = 4
Bank 0
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
READ to READ Command Interval (same ROW address in same bank)
L
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
Address
ACT
ACT
READ READ
Row 0
Row 1
Column A Column B
DQ
Pr
BS
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
CL = 3
BL = 4
Bank0 Bank3
Dout
Dout
READ to READ Command Interval (different bank)
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Data Sheet E0517E20 (Ver. 2.0)
28
EDS2532AABH-1AR2
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW address of the
same bank as the preceding write command, the second write can be performed after an interval of no less than
1 clock. In the case of burst writes, the second write command has priority.
CLK
Command
ACT
Address
Row
WRIT
WRIT
Column A Column B
BS
DQ
in A0
EO
Bank0
Active
in B0
in B1
in B2
in B3
Burst Write Mode
BL = 4
Bank 0
Column =A Column =B
Write
Write
WRITE to WRITE Command Interval (same ROW address in same bank)
L
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two write commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. In the case of burst write, the second write
command has priority.
CLK
Command
ACT
WRIT
Row 0
Row 1
Column A Column B
BS
DQ
in A0
Bank0
Active
WRIT
Pr
Address
ACT
in B0
in B1
in B2
in B3
Burst Write Mode
BL = 4
Bank3 Bank0 Bank3
Active Write Write
t
uc
od
WRITE to WRITE Command Interval (different bank)
Data Sheet E0517E20 (Ver. 2.0)
29
EDS2532AABH-1AR2
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same
bank as the preceding read command, the write command can be performed after an interval of no less than 1
clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK
Command
READ WRIT
CL=2
DQM
CL=3
in B0
DQ (input)
in B1
in B2
in B3
EO
BL = 4
Burst write
High-Z
DQ (output)
READ to WRITE Command Interval (1)
CLK
Command
READ
WRIT
DQM
L
CL=2
2 clock
out
out
out
in
in
in
in
out
out
in
in
in
in
DQ
CL=3
Pr
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1
cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the
output buffer becomes High-Z before data input.
t
uc
od
Data Sheet E0517E20 (Ver. 2.0)
30
EDS2532AABH-1AR2
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
WRIT
READ
DQM
DQ (input)
in A0
EO
DQ (output)
out B0
Column = A
Write
Column = B
Read
out B1
out B2
out B3
Burst Write Mode
CL = 2
BL = 4
Bank 0
/CAS Latency
Column = B
Dout
WRITE to READ Command Interval (1)
CLK
DQM
DQ (input)
WRIT
L
Command
in A1
out B0
Pr
DQ (output)
in A0
READ
Column = A
Write
out B1
out B2
/CAS Latency
Column = B
Read
Column = B
Dout
out B3
Burst Write Mode
CL = 2
BL = 4
Bank 0
WRITE to READ Command Interval (2)
t
uc
od
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
continue to be written until one clock before the read command is executed (as in the case of the same bank and
the same address).
Data Sheet E0517E20 (Ver. 2.0)
31
EDS2532AABH-1AR2
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second
command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK
Command
READA
READ
bank0
Read A
bank3
Read
BS
DQ
out A0
out A1
out B1
CL= 3
BL = 4
".
EO
Note: Internal auto-precharge starts at the timing indicated by "
out B0
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank
starts 2 clocks later from the second command.
L
WRIT
DQ
in B0
CLK
Command
WRITA
BS
in A0
in A1
in B2
in B3
bank3
Write
Pr
bank0
Write A
in B1
Note: Internal auto-precharge starts at the timing indicated by "
BL= 4
".
Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
t
uc
od
Data Sheet E0517E20 (Ver. 2.0)
32
EDS2532AABH-1AR2
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.
CLK
Command
READA
WRIT
BS
CL = 2
DQM
CL = 3
DQ (input)
EO
in B0
DQ (output)
in B1
in B2
in B3
High-Z
bank0
ReadA
BL = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
Read with Auto Precharge to Write Command Interval (Different bank)
L
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
Pr
CLK
Command
WRITA
BS
DQM
in A0
DQ (output)
od
DQ (input)
READ
out B0
bank0
WriteA
bank3
Read
out B1
out B2
out B3
Note: Internal auto-precharge starts at the timing indicated by "
CL = 3
BL = 4
".
t
uc
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Data Sheet E0517E20 (Ver. 2.0)
33
EDS2532AABH-1AR2
Read command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the
clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge
command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as
an interval from the final data output to precharge command execution.
CLK
PRE/PALL
READ
Command
DQ
out A0
out A1
CL=2
out A2
out A3
EO
lEP = -1 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
CLK
Command
PRE/PALL
READ
DQ
out A0
out A1
L
CL=3
out A2
out A3
lEP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
CLK
READ
Pr
Command
PRE/PALL
High-Z
DQ
out A0
lHZP = 2
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
Command
READ
PRE/PALL
od
CLK
High-Z
DQ
out A0
t
uc
lHZP =3
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Data Sheet E0517E20 (Ver. 2.0)
34
EDS2532AABH-1AR2
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
PRE/PALL
WRIT
Command
DQM
DQ
in A0
in A1
in A2
EO
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
Command
PRE/PALL
WRIT
DQM
L
DQ
in A0
in A1
in A2
in A3
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
t
uc
od
Pr
Data Sheet E0517E20 (Ver. 2.0)
35
EDS2532AABH-1AR2
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
ACT
ACT
Address
ROW
ROW
BS
EO
tRC
Bank 0
Active
Bank 0
Active
Bank Active to Bank Active for Same Bank
CLK
Command
ACT
ROW:0
ROW:1
L
Address
ACT
BS
tRRD
Bank 3
Active
Pr
Bank 0
Active
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
Address
MRS
OPCODE
od
Command
ACT
BS & ROW
lMRD
Mode
Register Set
Bank
Active
t
uc
Mode register set to Bank active command interval
Data Sheet E0517E20 (Ver. 2.0)
36
EDS2532AABH-1AR2
DQM Control
The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively.
The timing of UDQM/LDQM is different during reading and writing.
Reading
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes
Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding
data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks.
Writing
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to
High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0
clock.
EO
CLK
DQM
High-Z
DQ
out 0
out 1
out 3
lDOD = 2 Latency
L
Reading
CLK
DQ
Pr
DQM
in 0
in 3
in 1
od
lDID = 0 Latency
Writing
t
uc
Data Sheet E0517E20 (Ver. 2.0)
37
EDS2532AABH-1AR2
Refresh
Auto-refresh
All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command
updates the internal counter every time it is executed and determines the banks and the ROW addresses to be
refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW
addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a
precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by
the precharge command is not required.
Others
EO
Power-down mode
The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power
consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held
Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is
enabled from the next clock. In this mode, internal refresh is not performed.
Clock suspend mode
By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During
clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven
High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details,
refer to the "CKE Truth Table".
L
t
uc
od
Pr
Data Sheet E0517E20 (Ver. 2.0)
38
EDS2532AABH-1AR2
Timing Waveforms
Read Cycle
tCK
tCH t CL
CLK
t RC
VIH
CKE
t RP
tRAS
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
/RAS
EO
tSI tHI
tSI tHI
/CAS
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/WE
tSI tHI
BS
tSI tHI
tSI tHI
A10
tSI tHI
L
Address
tSI tHI
tSI tHI
tSI
DQM
tHI
DQ (input)
Pr
tAC
DQ (output)
tAC
tAC
tHZ
t AC
tOH
tOH
Bank 0
Active
Bank 0
Read
tLZ
tOH
tOH
/CAS latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
= VOH or VOL
Bank 0
Precharge
t
uc
od
Data Sheet E0517E20 (Ver. 2.0)
39
EDS2532AABH-1AR2
Write Cycle
tCK
tCH tCL
CLK
tRC
VIH
CKE
tRP
tRAS
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/CS
tSI tHI
tSI tHI
/RAS
tSI tHI
tSI tHI
/CAS
EO
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
/WE
tSI tHI
tSI tHI
BS
tSI tHI
tSI tHI
A10
tSI tHI
tSI tHI
tSI tHI
Address
tSI
L
DQM
tSI
DQ (input)
tHI
t HI
tSI
tHI tSI
tHI
tSI
tHI
tDPL
Bank 0
Write
Bank 0
Active
Mode Register Set Cycle
0
1
CKE
2
3
4
5
VIH
/CS
/RAS
/CAS
/WE
7
8
9
10
11
12
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
13
14
15
16
17
18
19
code
valid
C: b’
C: b
R: b
DQM
DQ (output)
b
High-Z
DQ (input)
lMRD
lRP
Precharge
If needed
Mode
register
Set
Bank 3
Active
lRCD
Output mask
Bank 3
Read
Data Sheet E0517E20 (Ver. 2.0)
40
t
uc
BS
Address
6
Bank 0
Precharge
od
CLK
Pr
DQ (output)
b+3
b’
b’+1
b’+2
b’+3
lRCD = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
EDS2532AABH-1AR2
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
VIH
CKE
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQM
DQ (output)
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
DQ (input)
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
VIH
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
EO
CKE
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQM
High-Z
DQ (output)
DQ (input)
a
a+1 a+2 a+3
Bank 0
Write
b
Bank 3
Active
L
Bank 0
Active
b+1 b+2 b+3 b'
Bank 3
Write
Bank 0
Precharge
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Write
Bank 3
Precharge
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
VIH
/RAS
/CAS
/WE
BS
R:a
Address
DQM
Pr
/CS
C:a
R:b
C:a' C:a
a
Bank 0
Active
CKE
od
a
DQ (input)
DQ (output)
Bank 3
Active
C:a
R:b
a
Bank 0 Bank 0
Write
Read
VIH
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
DQM
a
DQ (input)
DQ (output)
a
Bank 0
Active
Bank 0
Read
a+1
a+3
Bank 0
Write
Bank 3
Active
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
t
uc
Bank 0
Read
a+1 a+2 a+3
C:b C:c
b
c
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0517E20 (Ver. 2.0)
41
EDS2532AABH-1AR2
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
R:a
Address
C:a
R:b
C:a'
DQM
a
DQ (input)
DQ (output)
EO
a
Bank 0
Active
CKE
Clock
suspend
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a+1 a+2 a+3
Bank 0
Precharge
Bank 0
Write
Bank 3
Precharge
VIH
/CS
/RAS
/CAS
/WE
BS
DQM
DQ (input)
DQ (output)
R:a
L
Address
Bank 0
Active
Bank 0
Read
0
1
2
CLK
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 3
Active
3
4
5
6
7
VIH
/CS
/RAS
/CAS
/WE
BS
8
9
10
11
12
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
13
14
15
R:a
A10=1
DQM
DQ (input)
16
17
t RP
t RC
Auto Refresh
t RC
Auto Refresh
Data Sheet E0517E20 (Ver. 2.0)
42
18
19
20
C:a
a
High-Z
DQ (output)
Precharge
If needed
Bank 0
Precharge
t
uc
Address
a+1
od
CKE
a
a
Pr
Auto Refresh Cycle
C:a
Active
Bank 0
Read
Bank 0
a+1
Refresh cycle and
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
EDS2532AABH-1AR2
Clock Suspend Mode
tSI
0
1
2
3
4
tSI
tHI
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
R:a
C:a
R:b
C:b
DQM
DQ (output)
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
DQ (input)
EO
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3
Active
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
Earliest Bank3
Precharge
CKE
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
/CS
/RAS
/CAS
/WE
BS
Address
C:a R:b
R:a
C:b
DQM
High-Z
DQ (output)
L
DQ (input)
Bank0
Active
Active clock
suspend start
a
a+1 a+2
Active clock Bank0 Bank3
supend end Write Active
a+3 b
Write suspend
start
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
Power Down Mode
CLK
/CS
/RAS
/CAS
CKE Low
BS
Address
od
/WE
Pr
CKE
R: a
A10=1
DQM
DQ (input)
High-Z
DQ (output)
t
uc
tRP
Precharge command
If needed
Power down cycle
Power down entry
Power down
/RAS-/CAS delay = 3
mode exit
Active Bank 0 /CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0517E20 (Ver. 2.0)
43
EDS2532AABH-1AR2
Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
CLK
CKE
VIH
/CS
/RAS
/CAS
/WE
DQM
code
valid
Address
Valid
VIH
High-Z
EO
DQ
All banks
Precharge
t RC
tRP
lMRD
tRC
Auto Refresh
Auto Refresh
Mode register
Set
Bank active
If needed
L
t
uc
od
Pr
Data Sheet E0517E20 (Ver. 2.0)
44
EDS2532AABH-1AR2
Package Drawing
90-ball FBGA
Solder ball: Lead free (Sn-Ag-Cu)
Unit: mm
0.2 S A
8.0 ± 0.1
INDEX AREA
L
EO
13.0 ± 0.1
0.2 S B
0.2 S
1.14 max.
S
Pr
0.35 ± 0.05
0.1 S
0.8
B
90-φ0.45 ± 0.05
φ0.08 M S A B
od
A
INDEX MARK
0.8
1.6
0.9
t
uc
0.8
ECA-TS2-0096-01
Data Sheet E0517E20 (Ver. 2.0)
45
EDS2532AABH-1AR2
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS2532AABH.
Type of Surface Mount Device
EDS2532AABH: 90-ball FBGA < Lead free (Sn-Ag-Cu) >
L
EO
t
uc
od
Pr
Data Sheet E0517E20 (Ver. 2.0)
46
EDS2532AABH-1AR2
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
EO
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
3
L
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Pr
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
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EDS2532AABH-1AR2
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
EO
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
L
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
Pr
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
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