ESMT M12S64164A-6BG

ESMT
M12S64164A
SDRAM
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
y
y
y
y
y
y
y
y
ORDERING INFORMATION
PRODUCT NO.
JEDEC standard 2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6 μ s refresh interval
MAX FREQ. PACKAGE Comments
M12S64164A-6TG
166MHz
54 TSOP II
Pb-free
M12S64164A-6BG
166MHz
54 BGA
Pb-free
M12S64164A-7TG
143MHz
54 TSOP II
Pb-free
M12S64164A-7BG
143MHz
54 BGA
Pb-free
M12S64164A-10TG
100MHz
54 TSOP II
Pb-free
M12S64164A-10BG
100MHz
54 BGA
Pb-free
GENERAL DESCRIPTION
The M12S64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
V DD
DQ0
V DDQ
DQ1
DQ2
V SSQ
DQ3
DQ4
V DDQ
DQ5
DQ6
V SSQ
DQ7
V DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A 10 /AP
A0
A1
A2
A3
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V SS
DQ1 5
V S SQ
DQ1 4
DQ1 3
VDDQ
DQ1 2
DQ1 1
V S SQ
DQ1 0
DQ9
VDDQ
DQ8
VSS
NC
UDQ M
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
A
VSS
DQ15
B
DQ14
C
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
NC
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Elite Semiconductor Memory Technology Inc.
4
5
6
Publication Date: Apr. 2009
Revision: 1.2
1/45
ESMT
M12S64164A
FUNCTIONAL BLOCK DIAGRAM
CKE
Clock
Generator
Bank D
Bank C
Bank B
Address
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Row Decoder
CLK
Bank A
WE
Data Control Circuit
Input & Output
Buffer
CAS
L(U)DQM
Column Decoder
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Sense Amplifier
Column
Address
Buffer
&
Refresh
Counter
DQ
PIN FUNCTION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
BA1, BA0
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Latches row addresses on the positive going edge of the CLK with
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
VDD / VSS
Power Supply / Ground
VDDQ / VSSQ
Data Output Power / Ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC
No Connection
This pin is recommended to be left No Connection on the device.
RAS low.
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Elite Semiconductor Memory Technology Inc.
Latches data in starting from CAS , WE active.
Publication Date: Apr. 2009
Revision: 1.2
2/45
ESMT
M12S64164A
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNIT
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 3.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 3.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 °C )
PARAMETER
Supply voltage
SYMBOL
MIN
TYP
MAX
UNIT
NOTE
VDD, VDDQ
2.3
2.5
2.7
V
Input logic high voltage
VIH
0.8*VDDQ
-
VDDQ+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.3
V
2
Output logic high voltage
VOH
VDDQ -0.2
-
-
V
IOH = -0.1mA
Output logic low voltage
VOL
-
-
0.2
V
IOL = 0.1mA
Input leakage current
IIL
-5
-
5
μA
3
Output leakage current
IOL
-5
-
5
μA
4
Note:
1. VIH(max) = 3.0V AC for pulse width ≤ 3ns acceptable.
2. VIL(min) = -1.0V AC for pulse width ≤ 3ns acceptable.
3. Any input 0V ≤ VIN ≤ VDDQ, all other pins are not under test = 0V.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 2.5V, TA = 25 °C , f = 1MHZ)
PARAMETER
SYMBOL
MIN
MAX
UNIT
CIN1
2
4
pF
(CLK, CKE, CS , RAS , CAS , WE &
L(U)DQM)
CIN2
2
4
pF
Data input/output capacitance (DQ0 ~ DQ15)
COUT
2
6
pF
Input capacitance (A0 ~ A11, BA0~ BA1)
Input capacitance
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
3/45
ESMT
M12S64164A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70 °C
PARAMETER
Operating Current
(One Bank Active)
SYMBOL
ICC1
Active Standby Current
in power-down mode
tcc = tcc(min)
-6
-7
-10
85
85
60
2
CKE & CLK ≤ VIL(max), tcc = ∞
1
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = tcc(min)
Input signals are changed one time during 2CLK
20
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
10
ICC3P
CKE ≤ VIL(max), tcc = tcc(min)
10
ICC3PS
CKE & CLK ≤ VIL(max), tcc = ∞
10
ICC2N
ICC3N
Active Standby Current
in non power-down mode
(One Bank Active)
Burst Length = 1, tRC ≥ tRC(min), IOL = 0 mA,
VERSION
CKE ≤ VIL(max), tcc = tcc(min)
ICC2P
Precharge Standby Current
in power-down mode
ICC2PS
Precharge Standby Current
in non power-down mode
TEST CONDITION
UNIT
NOTE
mA
1,2
mA
mA
mA
CS CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
Input signals are changed one time during 2 CLKs
All other pins ≥ VDD - 0.2V or ≤ 0.2V
30
mA
25
mA
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
Operating Current
(Burst Mode)
ICC4
IOL = 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
150
140
120
mA
Refresh Current
ICC5
tRFC ≥ tRFC(min), tCC = tcc(min)
150
140
120
mA
Self Refresh Current
ICC6
CKE ≤ 0.2V
Note:
1
mA
1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
4/45
1,2
ESMT
M12S64164A
AC OPERATING TEST CONDITIONS (VDD = 2.5V ± 0.2V ，TA = 0 to 70 °C )
PARAMETER
VALUE
UNIT
0.9*VDDQ/0.2
V
Input timing measurement reference level
0.5*VDDQ
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
0.5*VDDQ
V
Input levels (Vih/Vil)
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
VERSION
-6
-7
-10
UNIT
NOTE
Row active to row active delay
tRRD(min)
12
14
20
ns
1
RAS to CAS delay
tRCD(min)
18
20
30
ns
1
Row precharge time
tRP(min)
18
20
30
ns
1
tRAS(min)
40
42
60
ns
1
Row active time
tRAS(max)
Row cycle time
100
us
@ Operating
tRC(min)
58
63
90
ns
1
@ Auto refresh
tRFC(min)
60
70
100
ns
1,5
Last data in to col. address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
1
1
CLK
CLK
2
3
CAS latency = 3
2
ea
4
CAS latency = 2
1
Number of valid
Output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
5/45
ESMT
M12S64164A
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
PARAMATER
CLK cycle time
CAS latency = 3
SYMBOL
tCC
CAS latency = 2
CLK to valid
output delay
CAS latency = 3
Output data
hold time
CAS latency = 3
CAS latency = 2
CAS latency = 2
-6
MIN
6
-7
MAX
1000
10
tSAC
tOH
MIN
7
-10
MAX
1000
10
MIN
10
MAX
1000
UNIT
NOTE
ns
1
ns
1,2
ns
2
12
5.5
6
7
6
6
8
2.5
2.5
2.5
2.5
2.5
2.5
CLK high pulse width
tCH
2.5
2.5
3
ns
3
CLK low pulse width
tCL
2.5
2.5
3
ns
3
Input setup time
tSS
1.5
1.5
2.5
ns
3
Input hold time
tSH
1
1
1.5
ns
3
CLK to output in Low-Z
tSLZ
0
0
0
ns
2
ns
-
CLK to output
in Hi-Z
Note:
CAS latency = 3
5.5
6
7
6
6
8
tSHZ
CAS latency = 2
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
6/45
ESMT
M12S64164A
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Refresh
CKEn-1
CKEn
H
X
H
L
Mode Register set
Auto Refresh
Entry
Self
Refresh
Exit
H
L
L
L
L
X
A11,
BA0,
A10/AP
A9~A0
BA1
OP CODE
L
L
L
H
X
X
H
X
L
H
X
H
H
X
H
X
X
X
V
H
L
H
X
V
CS RAS CAS
WE
DQM
L
H
Bank Active & Row Addr.
H
X
L
H
L
Auto Precharge Disable
Read &
Column Address Auto Precharge Enable
H
X
L
Auto Precharge Disable
Write &
Column Address Auto Precharge Enable
H
Burst Stop
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Precharge
Bank Selection
X
L
H
L
L
X
All Banks
Clock Suspend or
Active Power Down
Entry
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Exit
L
H
Entry
H
L
Note
X
V
Row Address
Column
L
Address
H
(A0~A7)
Column
L
Address
H
(A0~A7)
X
V
L
X
H
1,2
3
3
3
3
4
4,5
4
4,5
6
X
X
X
X
X
X
Precharge Power Down Mode
Exit
DQM
L
H
X
H
No Operating Command
H
X
X
H
X
X
X
L
H
H
H
V
X
X
X
7
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
Note:
1.OP Code : Operating Code
A0~A11 & BA0 ~ BA1: Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4. BA0 ~ BA1: Bank select addresses.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge , BA0 and BA1 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
7/45
ESMT
M12S64164A
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
BA0~BA1
A11~A10/AP
A9
Function
RFU
RFU
W.B.L
Test Mode
A8
A7
A6
TM
CAS Latency
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT = 0
BT = 1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
Reserved
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
Write Burst Length
A9
Length
1
0
1
Reserved
1
0
1
Reserved Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
Full Page Reserved
Full Page Length : 256
Note:
1. RFU (Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
8/45
ESMT
M12S64164A
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
9/45
ESMT
M12S64164A
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of setup and hold time around positive edge
of the clock for proper functionality and ICC specifications.
1. Apply power and start clock, Attempt to maintain CKE
= “H”, DQM = “H” and the other pins are NOP
condition at the inputs.
2. Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3. Issue precharge commands for all banks of the
devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “1CLK + tSS” before the high going edge of the clock,
then the SDRAM becomes active from the same clock edge
accepting all the input commands.
BANK ADDRESSES (BA0~BA1)
This SDRAM is organized as four independent banks of
1,048,576 words x 16 bits memory arrays. The BA0~BA1
inputs are latched at the time of assertion of RAS and
CAS to select the bank to be used for the operation. The
banks addressed BA0~BA1 are latched at bank active, read,
write, mode register set and precharge operations.
ADDRESS INPUTS (A0~A11)
The 20 address bits are required to decode the 1,048,576
word locations are multiplexed into 12 address input pins
(A0~A11). The 12 row addresses are latched along with
RAS and BA0~BA1 during bank active command. The 8 bit
column addresses are latched along with CAS , WE and
BA0~BA1 during read or with command.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and WE (The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A11
and BA0~BA1 in the same cycle as CS , RAS , CAS
and WE going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all banks
are in the idle state. The mode register is divided into
various fields into depending on functionality. The burst
length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
vendor specific options or test mode use A7~A8,
A10/AP~A11 and BA0~BA1. The write burst length is
programmed using A9. A7~A8, A10/AP~A11 and
BA0~BA1 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for
various burst length, burst type and CAS latencies.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high, The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock cycle like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting CS high. CS high disables
the command decoder so that RAS , CAS , WE and all
the address inputs are ignored.
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DEVICE OPERATIONS (Continued)
BANK ACTIVATE
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank address, a row access is initiated. The
read or write operation can occur after a time delay of
tRCD(min) from the time of bank activation. tRCD is the internal
timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock
cycles required between bank activate and read or write
command should be calculated by dividing tRCD(min) with
cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in
the same chip and shares part of the internal circuitry to
reduce chip area, therefore it restricts the activation of four
banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. tRRD(min) specifies the minimum time
required between activating different bank. The number of
clock cycles required between different bank activation must
be calculated similar to tRCD specification. The minimum time
required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
tRAS(min). Every SDRAM bank activate command must
satisfy tRAS(min) specification before a precharge command
to that active bank can be asserted. The maximum time any
bank can be in the active state is determined by tRAS(max)
and tRAS(max) can be calculated similar to tRCD specification.
and WE with valid column address, a write burst is
initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be
completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst
write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst
can also be terminated by using DQM for blocking data
and procreating the bank tRDL after the last data input to
be written into the active row. See DQM OPERATION
also.
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM
signal is important during burst interrupts of write with
read or precharge in the SDRAM. Due to asynchronous
nature of the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when the
complete burst write is required. Please refer to DQM
timing diagram also.
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
CS and RAS with WE being high on the positive edge
of the clock. The bank must be active for at least tRCD(min)
before the burst read command is issued. The first output
appears in CAS latency number of clock cycles after the
issue of burst read command. The burst length, burst
sequence and latency from the burst read command is
determined by the mode register which is already
programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the
initial address does not start from a boundary such that
number of outputs from each I/O are equal to the burst
length programmed in the mode register. The output goes
into high-impedance at the end of burst, unless a new burst
read was initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank
activate and CS , RAS , WE and A10/AP with valid
BA0~BA1 of the bank to be procharged. The precharge
command can be asserted anytime after tRAS(min) is
satisfy from the bank active command in the desired
bank. tRP is defined as the minimum number of clock
cycles required to complete row precharge is calculated
by dividing tRP with clock cycle time and rounding up to
the next higher integer. Care should be taken to make
sure that burst write is completed or DQM is used to
inhibit writing before precharge command is asserted.
The maximum time any bank can be active is specified
by tRAS(max). Therefore, each bank activate command.
At the end of precharge, the bank enters the idle state
and is ready to be activated again. Entry to power-down,
Auto refresh, Self refresh and Mode register set etc. is
possible only when all banks are in idle state.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive
clock cycles in adjacent addresses depending on burst
length and burst sequence. By asserting low on CS , CAS
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DEVICE OPERATIONS (Continued)
AUTO PRECHARGE
SELF REFRESH
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the timing
to satisfy tRAS(min) and “tRP” for the programmed burst length
and CAS latency. The auto precharge command is issued at
the same time as burst write by asserting high on A10/AP,
the bank is precharge command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode
for data retention and low power operation of SDRAM.
In self refresh mode, the SDRAM disables the internal
clock and all the input buffers except CKE. The refresh
addressing and timing is internally generated to reduce
power consumption. The self refresh mode is entered
All BANKS PRECHARGE
All banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS , and
WE with high on A10/AP after all banks have satisfied
tRAS(min) requirement, performs precharge on all banks. At
the end of tRP after performing precharge all, all banks are in
idle state.
from all banks idle state by asserting low on CS ,
RAS , CAS and CKE with high on WE . Once the self
refresh mode is entered, only CKE state being low
matters, all the other inputs including clock are ignored
to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed
by NOP’s for a minimum time of tRFC before the SDRAM
reaches idle state to begin normal operation. 4K cycles
of burst auto refresh is required immediately before self
refresh entry and immediately after self refresh exit.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal counter
increments automatically on every auto refresh cycle to
refresh all the rows. An auto refresh command is issued by
asserting low on CS , RAS and CAS with high on CKE
and WE . The auto refresh command can only be asserted
with all banks being in idle state and the device is not in
power down mode (CKE is high in the previous cycle). The
time required to complete the auto refresh operation is
specified by tRFC(min). The minimum number of clock cycles
required can be calculated by driving tRFC with clock cycle
time and them rounding up to the next higher integer. The
auto refresh command must be followed by NOP’s until the
auto refresh operation is completed. The auto refresh is the
preferred refresh mode when the SDRAM is being used for
normal data transactions. The auto refresh cycle can be
performed once in 15.6us.
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COMMANDS
Mode register set command
( CS , RAS , CAS , WE
= Low)
The device has a mode register that defines how the device operates. In this
command, A0 through A11 and BA0~BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state. During 2CLK
following this command, the device cannot accept any other commands.
Activate command
( CS , RAS = Low, CAS , WE = High)
The device has four banks, each with 4,096 rows.
This command activates the bank selected by BA1 and BA0 (BS) and a row
address selected by A0 through A11.
This command corresponds to a conventional DRAM’s RAS falling.
Precharge command
( CS , RAS , WE = Low, CAS = High )
This command begins precharge operation of the bank selected by BA1 and BA0
(BS). When A10 is High, all banks are precharged, regardless of BA1 and BA0.
When A10 is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the device can’t accept the activate command to the
precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
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Write command
( CS , CAS , WE = Low, RAS = High)
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
Read command
( CS , CAS = Low, RAS , WE = High)
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
CBR (auto) refresh command
( CS , RAS , CAS = Low, WE , CKE = High)
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
During tRFC period (from refresh command to refresh or activate command), the
device cannot accept any other command.
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Self refresh entry command
( CS , RAS , CAS , CKE = Low, WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the device exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Burst stop command
( CS , WE = Low, RAS , CAS = High)
This command terminates the current burst operation.
Burst stop is valid at every burst length.
No operation
( CS = Low, RAS , CAS , WE = High)
This command is not a execution command. No operations begin or terminate by
this command.
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BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1 ) Cl o c k S u sp e n d e d D u r in g W r i t e ( B L = 4 )
2 ) C lo c k S u s p e n d e d D u r i n g R e a d ( B L =4 )
CLK
CM D
WR
RD
CK E
Masked by C KE
I nt e r n al
CL K
DQ ( C L 2 )
D0
D1
D2
D3
DQ ( C L 3 )
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
N o t W r i tt e n
Q3
Su s pe nd ed D ou t
2. DQM Operation
2) Read Mas k (B L= 4)
1)W rite Mask (BL=4)
CLK
CMD
WR
RD
DQM
Ma s k e d b y D Q M
Ma s k e d b y D Q M
DQ(CL2)
D0
D1
D3
DQ(CL3)
D0
D1
D3
Q0
Hi- Z
Q2
Q3
Hi- Z
Q1
DQ M t o D at a -i n M ask = 0
Q2
Q3
DQ M to D at a- ou t M ask = 2
*Note2
3)DQM with clc ok su sp end ed (F ull Page Read )
CLK
CMD
RD
CKE
Inter nal
CLK
DQM
Hi- Z
DQ(CL2)
DQ(CL3)
Q0
Hi-Z
Hi-Z
Q1
Hi- Z
Q4
Q2
Hi-Z
Q6
Q7
Q8
Q9
Q7
Q8
Hi-Z
Q3
Q5
Q6
*Note: 1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
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3. CAS Interrupt (I)
* Not e 1
1) Re ad i nt e rr upt ed b y R ea d ( B L= 4)
CLK
CMD
RD
RD
ADD
A
B
D Q ( CL 2 )
Q A0
DQ ( C L 3 )
QB0
QB1
QB2
QB3
QA0
Q B0
QB1
QB2
QB3
tC C D
*N ote 2
2) W ri t e i n t e rr up t ed by W r it e ( B L = 2)
3 ) Wr it e i nt e rr u pt e d b y R e a d ( B L = 2)
CL K
CMD
WR
tC CD
ADD
DQ
WR
WR
t CC D
* N ote 2
A
B
DA 0
DB0
A
DB 1
t CD L
*N ote 3
D Q ( CL 2 )
DA0
DQ ( C L 3 )
DA0
RD
* No t e 2
B
DB 0
DB1
DB0
DB1
t CD L
*N ote 3
*Note:
1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt”, to stop burst read/write by CAS access; read and write.
2. tCCD: CAS to CAS delay. (=1CLK)
3. tCDL: Last data in to new column address delay. (=1CLK)
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4. CAS Interrupt (II) : Read Interrupted by Write & DQM
( a) CL =2 ,B L= 4
CLK
i)CMD
RD
WR
DQM
DQ
ii)CMD
D0
RD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
DQM
Hi-Z
DQ
iii)CMD
D0
RD
WR
DQM
Hi-Z
DQ
iv)CMD
D0
WR
RD
DQM
DQ
Q0
HHi -i Z
-Z
D0
D3
*Note1
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(b) CL =3 ,B L= 4
CLK
RD
i)CMD
WR
DQM
DQ
D0
ii)CMD
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
D3
D1
D2
WR
RD
DQM
DQ
D0
iii)CMD
WR
RD
DQM
D0
DQ
iv)CMD
RD
WR
DQM
Hi-Z
DQ
v)CM D
D0
RD
WR
DQM
Hi-Z
DQ
Q0
D0
D3
*Note1
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
CLK
CMD
*Note3
WR
*Note2
DQM
DQ
D0
D1
D2
D3
Ma s k e d b y D Q M
*Note:
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
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6. Precharge
1)Normal W rit e (BL=4)
2) Norm al R ead (B L= 4)
CLK
CLK
CMD
WR
DQ
D0
PRE
CMD
RD
PRE
CL=2
Q2
Q3
*Note2
D1
D2
DQ(CL2)
D3
tRD L
Q0
Q1
PRE CL= 3
CMD
*Note1
*Note2
DQ( CL3)
Q0
Q1
Q2
Q3
.
7. Auto Precharge
1)Normal W rit e (BL=4)
2) Normal Read (B L= 4)
CLK
CMD
DQ
CLK
CMD
WR
D0
D1
D2
DQ(CL2)
D3
tRDL
RD
D0
D1
D2
D3
D0
D1
D2
(min )
DQ(CL3)
D3
*Note3
Aut o Pr ech ar ge st ar t s
*Note3
Auto Pr ech arge st art s
*Note:
1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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8. Burst Stop & Interrupted by Precharge
1) W ri te B ur s t S t op ( BL= 8 )
1) W ri t e in t err up t ed by pr ec ha rg e ( B L= 4)
CLK
CLK
*N ote3
CM D
CM D
ST OP
WR
WR
PRE
t R DL
*N ote4
DQ M
DQ
DQ M
D0
D1
D3
D2
D4
t B DL
DQ
D5
D1
Mask Mask
*N ote1
2 )R e ad B ur s t S t op (B L= 4)
2 )R ea d i nt er ru pt ed by pr ec har ge (B L =4)
CL K
CMD
D0
CL K
RD
CMD
STO P
*N ote5
RD
PRE
*N ote2
DQ ( C L 2 )
Q0
Q1
* Not e 2
D Q( C L3)
Q0
Q1
D Q( C L2)
D Q ( CL 3 )
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
9. MRS
1 )M o d e R e g is t e r S e t
CLK
*N o t e 6
CMD
PRE
t RP
*Note:
ACT
M RS
2C LK
1. tBDL: 1 CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
3. Write burst is terminated. tRDL determinates the last data write.
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying tRAS min delay) with DQM.
6. PRE: All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
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10. Clock Suspend Exit & Power Down Exit
1) Cl o ck S u sp en d (= Ac t ive P ow er Do wn ) Exi t
2)P ower Down (= Pr ec harg e Powe r Down )
CLK
CLK
CKE
Inter nal
CLK
Internal
CLK
*Note1
CMD
tSS
CKE
tSS
*Note2
CMD
RD
NOP AC T
11. Auto Refresh & Self Refresh
1) A u t o Re f r es h & S e lf R ef r e s h
*N ote3
CLK
*N ote4
CM D
* No t e 5
PRE
CM D
AR
CKE
t RP
2 ) S el f Re f r es h
t RF C
*N ote6
CLK
*N ote4
CM D
SR
PRE
CMD
CKE
tRP
*Note:
tR F C
1. Active power down: one or more banks active state.
2. Precharge power down: all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
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12. About Burst Type Control
Sequential Counting
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Interleave Counting
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Basic
MODE
Random
MODE
Random Column Access
tCCD = 1 CLK
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
13. About Burst Length Control
Basic
MODE
Random
MODE
Interrupt
MODE
1
At MRS A210 = “000”
At auto precharge. tRAS should not be violated.
2
At MRS A210 = “001”
At auto precharge. tRAS should not be violated.
4
At MRS A210 = “010”
8
At MRS A210 = “011”
Full Page
At MRS A210 = “111”
At the end of the burst length, burst is warp-around.
Burst Stop
tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
RAS Interrupt
(Interrupted by
Precharge)
CAS Interrupt
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
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FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
CS
RAS
CAS
WE
BA
ADDR
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
H
L
X
H
H
L
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
BA
BA
BA
X
OP code
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
X
X
X
X
CA, A10/AP
RA
A10/AP
X
OP code
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
RA, RA10
X
X
X
X
CA, A10/AP
RA, RA10
X
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ACTION
NOP
NOP
ILLEGAL
ILLEGAL
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
Begin Read ; latch CA ; determine AP
Begin Write ; latch CA ; determine AP
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Note
2
2
4
5
5
2
2
3
2
3
3
2
3
2
2
Publication Date: Apr. 2009
Revision: 1.2
24/45
ESMT
Current
State
Read with
Auto
Precharge
Row
Activating
Refreshing
Mode
Register
Accessing
Abbreviations:
*Note:
M12S64164A
CS
RAS
CAS
WE
BA
ADDR
ACTION
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
NOP Æ Idle after tRP
NOP Æ Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRP
ILLEGAL
NOP Æ Row Active after tRCD
NOP Æ Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRFC
NOP Æ Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after 2clocks
NOP Æ Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
Note
2
2
2
4
2
2
2
2
AP = Auto Precharge
1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BA, depending on the state of the bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
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ESMT
M12S64164A
FUNCTION TRUTH TABLE (TABLE2)
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
CKE
( n-1 )
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
L
L
CKE
n
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
CS
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
L
X
X
X
X
X
RAS CAS
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
H
L
L
X
X
X
X
X
WE
ADDR
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
X
OP Code
X
X
X
X
X
ACTION
INVALID
Exit Self Refresh Æ Idle after tRFC (ABI)
Exit Self Refresh Æ Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh Æ ABI
Exit Self Refresh Æ ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
NOP
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
Note
6
6
7
7
8
8
8
9
9
Abbreviations: ABI = All Banks Idle, RA = Row Address
*Note:
6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
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Publication Date: Apr. 2009
Revision: 1.2
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ESMT
M12S64164A
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3, Burst Length = 1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
HIGH
CKE
tRAS
tRC
tSH
*Note1
CS
tRP
tRCD
tSS
tSH
RAS
tCCD
tSS
tSH
CAS
tSS
tSH
ADDR
Ra
Ca
Cb
Cc
*Note2,3
Rb
tSS
*Note2,3
*Note2,3
*Note4
*Note2
BA0, BA1
*Note2
BS
BS
BS
BS
BS
BS
A10/AP
Ra
*Note 3
*Note 3
*Note 3
*Note4
Rb
tSAC
tSH
DQ
Qa
tSLZ
Qc
Db
tSS
tOH
tSH
WE
tSS
tSS
tSH
DQM
Ro w Acti ve
Read
W rite
Read
Row Active
Precharge
:Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
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ESMT
Note:
M12S64164A
1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA0
BA1
Active & Read/Write
0
0
Bank A
0
1
Bank B
1
0
Bank C
1
1
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
0
1
BA0
BA1
Operating
0
0
Disable auto precharge, leave A bank active at end of burst.
0
1
Disable auto precharge, leave B bank active at end of burst.
1
0
Disable auto precharge, leave C bank active at end of burst.
1
1
Disable auto precharge, leave D bank active at end of burst.
0
0
Enable auto precharge , precharge bank A at end of burst.
0
1
Enable auto precharge , precharge bank B at end of burst.
1
0
Enable auto precharge , precharge bank C at end of burst.
1
1
Enable auto precharge , precharge bank D at end of burst.
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
BA0
BA1
Precharge
0
0
0
Bank A
0
0
1
Bank B
0
1
0
Bank C
0
1
1
Bank D
1
X
X
All Banks
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Publication Date: Apr. 2009
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ESMT
M12S64164A
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High level is necessary
CS
tRFC
tRP
tRFC
RAS
CAS
ADDR
Key
RAa
BA0
BA1
RAa
A10 /AP
DQ
High-Z
WE
DQM
High level is necessary
Precharge
Auto Refresh
(All Banks)
Auto Refresh
Mode Register Set
Row Active
(A-Bank)
: Don't care
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ESMT
M12S64164A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
*Note1
tRC
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca0
Cb0
Rb
BA0
BA1
A10/AP
Ra
Rb
CL =2
Qa0
Qa1
Qa2
Qb0
Qa3
Qb1
Qb2
Qb3
*Note3
DQ
CL =3
Qa0
Qa1
Qa2
tRDL
Qb0
Qa3
Qb1
*Note3
Qb2
Qb3
tRDL
WE
DQM
Row Active
( A - Bank )
Read
( A - Bank )
Precharge
( A - Bank )
Row Active
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
:Don't Care
*Note:
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
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Publication Date: Apr. 2009
Revision: 1.2
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ESMT
M12S64164A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca
Cb
Cd
Cc
BA0
BA1
A10/AP
Ra
tRDL
Qa0
CL =2
Qa1
Qb0
Qa0
Qa1
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
Qb1
Dc0
Dc1
Dd0
Dd1
DQ
CL =3
Qb0
tCDL
WE
*Note1
* Note3
DQM
Row Active
( A - Bank )
Read
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Precharge
(A - Bank)
:Don't Care
Note:
1.
2.
3.
To Write data before burst read ends. DQM should be asserted three cycles prior to write command to avoid bus
contention.
Row precharge will interrupt writing. Last data input, tRDL before row precharge, will be written.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
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Revision: 1.2
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ESMT
M12S64164A
Page Read Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
CS
RAS
*Note2
CAS
ADDR
RAa
RBb CAa
RCc CBb
RDd CCc
RAa
RBb
RCc
RDd
CDd
BA0
BA1
A10/AP
CL=2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
WE
DQM
Row Active
( A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Read
(B-Bank)
Row Active
(C-Bank)
Read
(C-Bank)
Row Active
(D-Bank)
Precharge
(A-B ank)
Precharge
(D-Bank)
Read
(D-Bank)
Precharge
(C-Bank)
Precharge
(B-Bank)
:Don't Care
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
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ESMT
M12S64164A
Page Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
*Note2
CAS
ADDR
RAa
RBb
RAa
RBb
CAa
CBb
RCc
RDd
RCc
RDd
CCc
CDd
BA0
BA1
A10/AP
DQ
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 D Bb3 DCc 0 DC c1 D Dd 0 DDd 1 CD d 2
tRDL
tCDL
WE
*Note1
DQM
Row Active
( A - Bank )
Write
(A-Bank)
Row Active
(B-Bank)
W rite
(B-Bank)
Row Active
(D-Bank)
Row Active
(C-Bank)
Write
(D-Bank)
Precharge
(All Banks)
W rite
(C-Bank)
: Don't care
*Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
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ESMT
M12S64164A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CDb
RDb
CAa
CBc
RBc
BA0
BA1
A10/AP
RAa
RBb
RAc
tCDL
CL =2
QAa0 QAa1 QAa2 QAa 3
*Note1
DDb0 Ddb1 DDb2 D Dd3
QBc0 QBc1 QBc2
DDb 0 Ddb1 DDb 2 DDd 3
QBc0 QBc1
DQ
CL =3
QAa0 QAa1 QAa 2 QAa3
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
W rite
(D-Bank)
Read
(B-Bank)
Row Active
(B-Bank)
:Don't Care
*Note:
1. tCDL should be met to complete write.
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ESMT
M12S64164A
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Ca
Cb
BA0
BA1
A10/AP
CL =2
QAa0 QAa1 QAa2 QAa3
DD b0 Ddb1 DDb2 DDd3
DQ
CL =3
QAa0 QAa1 QAa2 QAa 3
DDb0 Ddb1 DDb2 DDd3
WE
DQM
R ow Act ive
( A - Ba nk )
Read with
Auto Precharge
( A - Bank )
R ow Activ e
( D - B ank )
*Note:
W rite with
Auto Precharge
(D-Bank)
Auto Precharge
Start Point
Auto Precharge
Start Point
(D-Bank)
:D o n 't C a re
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
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ESMT
M12S64164A
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cc
Cb
BA0
BA1
A10/AP
Ra
DQ
Qa0
Qa1
Qa2
Qa3
Qb0
tSHZ
Qb1
Dc0
Dc2
tSHZ
WE
*Note1
DQM
Row Active
Read
Clock
Supension
Read
W rite
DQM
Read DQM
Write
DQM
W rite
Clock
S uspension
:Don't Care
*Note: 1. DQM is needed to prevent bus contention
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ESMT
M12S64164A
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAb
CAa
BA0
BA1
A10/AP
RAa
CL=2
1
1
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
DQ
CL=3
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb 3 QAb4 QAb5
WE
*Note1
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
:Don't Care
*Note:
1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
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ESMT
M12S64164A
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAb
CAa
BA0
BA1
A 10/AP
RAa
tRDL
tBDL
*Note1
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 D Ab1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
(A-Bank)
W rite
(A-Bank)
Burst Stop
W rite
(A-Bank)
Precharge
(A-Bank)
:Don't Care
*Note:
1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
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ESMT
M12S64164A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note2
tSS
CKE
tSS
tSS
*Note1
*Note3
CS
RAS
CAS
ADDR
Ra
Ca
BA0
BA1
A10/AP
Ra
tSHZ
DQ
Qa0
Qa1
Qa2
WE
DQM
Precharge
Power-Down
En try
Row Active
Prech arge
Power-Down
Exit
Active
Power-d own
Entry
Read
Precharge
Active
Power-down
Exit
: Don't care
*Note:
1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
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ESMT
M12S64164A
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note4
*Note2
t R FC min
*Note1
*Note6
CKE
*No te 3
tSS
CS
*Note5
RAS
*Note7
CAS
ADDR
BA0,BA1
A10/ AP
DQ
Hi-Z
Hi-Z
WE
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
*Note:
TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
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ESMT
M12S64164A
Auto Refresh Cycle
Mode Register Set Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
HIGH
HIGH
CKE
CS
tRFC
*Note2
RAS
*Note1
CAS
*Note3
ADDR
Key
Ra
HI-Z
HI-Z
DQ
WE
DQM
MRS
New
Com man d
New C om m an d
Auto Ref res h
:Don't Care
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note:
1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
41/45
ESMT
M12S64164A
PACKING DIMENSIONS
54-LEAD TSOP(II) SDRAM (400mil) (1:3)
-H-
D
54
SEE
DETAIL A
A
A2
28
0.21 REF
0.665 REF
B
A1
E1
PIN1
IDENTIFIER
E
O
-CB
L
L1
1
DETAIL "A"
27
-C-
b
c c1
-C-
0.10
e
b
b1
SEATING PLANE
SECTION B-B
Symbol
A
A1
A2
b
b1
c
c1
D
E
E1
L
L1
e
Θ
Dimension in mm
Min Norm Max
1.20
0.05 0.10 0.15
0.95 1.00 1.05
0.25
0.45
0.25 0.35 0.40
0.12
0.21
0.10 0.127 0.16
22.22 BSC
11.76 BSC
10.16 BSC
0.40 0.50 0.60
0.80 REF
0.80 BSC
0°
10°
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min Norm Max
0.047
0.002 0.004 0.006
0.037 0.039 0.041
0.010
0.018
0.010 0.014 0.016
0.005
0.008
0.004 0.005 0.006
0.875 BSC
0.463 BSC
0.400 BSC
0.016 0.020 0.024
0.031 REF
0.031 BSC
0°
10°
Publication Date: Apr. 2009
Revision: 1.2
42/45
ESMT
M12S64164A
PACKING
DIMENSIONS
54-BALL
SDRAM ( 8x8 mm )
Symbol
Dimension in mm
Min
Norm
Max
A
1.00
A1
0.20
0.25
0.30
A2
0.61
0.66
0.71
Φb
0.30
0.35
0.40
D
7.90
8.00
8.10
E
7.90
8.00
8.10
D1
6.40
E1
6.40
e
0.80
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Dimension in inch
Min
Norm
Max
0.039
0.008
0.010
0.012
0.024
0.026
0.028
0.012
0.014
0.016
0.311
0.315
0.319
0.311
0.315
0.319
0.252
0.252
0.031
Publication Date: Apr. 2009
Revision: 1.2
43/45
ESMT
M12S64164A
Revision History
Revision
Date
1.0
2007.08.16
Original
1.1
2008.08.28
1. Add the specification of speed grade -6 and -10
2. Modify tCC(max) from - to 1000 ns for speed grade -7
2009.04.27
1. Rename A13, A12 to BA0, BA1
2. Modify the test condition of IIL and ICC3N
3. Modify the description about self refresh operation
4. Modify type error
1.2
Elite Semiconductor Memory Technology Inc.
Description
Publication Date: Apr. 2009
Revision: 1.2
44/45
ESMT
M12S64164A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2009
Revision: 1.2
45/45