TI SN74CBT16212C

SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus Family
Undershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
Bidirectional Data Flow, With Near-Zero
Propagation Delay
Low ON-State Resistance (ron)
Characteristics (ron = 3 Ω Typical)
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 8 pF Typical)
Data and Control Inputs Provide
Undershoot Clamp Diodes
Low Power Consumption
(ICC = 5 µA Max)
VCC Operating Range From 4 V to 5.5 V
Data I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
S0
1A1
1A2
2A1
2A2
3A1
3A2
GND
4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
VCC
8A1
GND
8A2
9A1
9A2
10A1
10A2
11A1
11A2
12A1
12A2
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
description/ordering information
ORDERING INFORMATION
PACKAGE†
TA
SSOP − DL
−40°C
−40
C to 85
85°C
C
TSSOP − DGG
ORDERABLE
PART NUMBER
Tube
SN74CBT16212CDL
Tape and reel
SN74CBT16212CDLR
Tube
SN74CBT16212CDGG
Tape and reel
SN74CBT16212CDGGR
TOP-SIDE
MARKING
CBT16212C
CBT16212C
TVSOP − DGV
Tape and reel
SN74CBT16212CDGVR
CY212C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright  2004, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
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1
SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
description/ordering information (continued)
The SN74CBT16212C is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance
(ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT16212C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT16212C operates as a 24-bit bus switch, or as a 12-bit bus-exchange that provides data
exchanging between four signal ports. The select (S0, S1, S2) inputs control the data path of the bus-exchange
switch. When the bus-exchange switch is ON, the A port is connected to the B port, allowing bidirectional data
flow between ports. When the bus-exchange switch is disabled, a high-impedance state exists between the A
and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, each select input should be tied to GND
through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability
of the driver.
FUNCTION TABLE
(each 12-bit bus-exchange)
INPUTS
2
INPUTS/OUTPUTS
S0
FUNCTION
S2
S1
A1
A2
L
L
L
L
L
Z
Z
Disconnect
H
B1
Z
A1 port = B1 port
L
H
L
B2
Z
A1 port = B2 port
L
H
H
Z
B1
A2 port = B1 port
H
L
L
Z
B2
A2 port = B2 port
H
L
H
Z
Z
Disconnect
H
H
L
B1
B2
A1 port = B1 port
A2 port = B2 port
H
H
H
B2
B1
A1 port = B2 port
A2 port = B1 port
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• DALLAS, TEXAS 75265
SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
logic diagram (positive logic)
2
1A1
54
1B1
SW
SW
SW
3
53
SW
1A2
12A1
27
1B2
30
SW
12B1
SW
SW
28
29
SW
12A2
12B2
1
S0
56
S1
55
S2
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3
SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
simplified schematic, each FET switch (SW)
A
B
Undershoot
Protection Circuit
EN†
† EN is the internal enable signal applied to the switch.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA
Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN
MAX
VCC
VIH
Supply voltage
4
5.5
UNIT
V
High-level control input voltage
2
5.5
V
VIL
VI/O
Low-level control input voltage
0
0.8
V
Data input/output voltage
0
5.5
V
TA
Operating free-air temperature
−40
85
°C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Control inputs
VCC = 4.5 V,
VIKU
Data inputs
VCC = 5 V,
IIN
Control inputs
VCC = 5.5 V,
IOZ‡
VCC = 5.5 V,
Ioff
VCC = 0,
ICC
VCC = 5.5 V,
IIN = −18 mA
0 mA > II ≥ −50 mA,
VIN = VCC or GND,
VIN = VCC or GND
VO = 0 to 5.5 V,
VI = 0,
MIN
TYP†
Switch OFF
Switch OFF,
VIN = VCC or GND
MAX
UNIT
−1.8
V
−2
V
±1
µA
±10
µA
VO = 0 to 5.5 V,
II/O = 0,
VIN = VCC or GND,
VI = 0
10
µA
Switch ON or OFF
7.5
µA
VCC = 5.5 V,
VIN = 3 V or 0
One input at 3.4 V,
Other inputs at VCC or GND
2.5
mA
Cio(OFF)
VI/O = 3 V or 0,
Switch OFF,
Cio(ON)
VI/O = 3 V or 0,
VCC = 4 V,
TYP at VCC = 4 V
∆ICC§
Cin
Control inputs
Control inputs
ron¶
VCC = 4.5 V
3.5
pF
VIN = VCC or GND
8
pF
Switch ON,
VIN = VCC or GND
19
pF
VI = 2.4 V,
IO = −15 mA
8
12
IO = 64 mA
IO = 30 mA
3
6
VI = 0
3
6
Ω
VI = 2.4 V,
IO = −15 mA
5
10
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
VCC = 4 V
VCC = 5 V
± 0.5 V
MIN
MIN
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
S
A
7
1.5
ten
S
B
7.2
tdis
S
B
7.7
PARAMETER
tpd#
tpd(s)
MAX
0.24
UNIT
MAX
0.15
ns
6.4
ns
1.5
7
ns
1.5
7.5
ns
# The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
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5
SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
undershoot characteristics (see Figures 1 and 2)
PARAMETER
TEST CONDITIONS
VOUTU
VCC = 5.5 V,
Switch OFF,
† All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
VCC
Input
Generator
Ax
VS
DUT
2
VOH−0.3
VIN = VCC or GND
Input
90 %
(Open
Socket) 10 %
Bx
100 kΩ
MAX
UNIT
V
Figure 1. Device Test Setup
POST OFFICE BOX 655303
90 %
2 ns
5.5 V
2 ns
10 %
−2 V
20 ns
10 pF
Output
(VOUTU)
6
TYP†
11 V
100 kΩ
50 Ω
MIN
VOH
VOH − 0.3
Figure 2. Transient Input Voltage (VI) and Output
Voltage (VOUTU) Waveforms
(Switch OFF)
• DALLAS, TEXAS 75265
SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
7V
Input Generator
VI
S1
RL
VO
GND
50 Ω
50 Ω
VG2
CL
(see Note A)
RL
TEST
VCC
S1
RL
VI
CL
tpd(s)
5 V ± 0.5 V
4V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
50 pF
50 pF
tPLZ/tPZL
5 V ± 0.5 V
4V
7V
7V
500 Ω
500 Ω
GND
GND
50 pF
50 pF
0.3 V
0.3 V
tPHZ/tPZH
5 V ± 0.5 V
4V
Open
Open
500 Ω
500 Ω
VCC
VCC
50 pF
50 pF
0.3 V
0.3 V
Output
Control
(VIN)
V∆
3V
1.5 V
3V
1.5 V
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLZ
3.5 V
1.5 V
tPZH
tPHL
1.5 V
VOL
1.5 V
0V
tPZL
Output
Control
(VIN)
Open
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + V∆
VOL
tPHZ
1.5 V
VOH − V∆
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
74CBT16212CDGGRE4
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
74CBT16212CDGGRG4
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
74CBT16212CDGVRE4
ACTIVE
TVSOP
DGV
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
74CBT16212CDGVRG4
ACTIVE
TVSOP
DGV
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74CBT16212CDGGR
ACTIVE
TSSOP
DGG
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74CBT16212CDGVR
ACTIVE
TVSOP
DGV
56
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74CBT16212CDL
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74CBT16212CDLG4
ACTIVE
SSOP
DL
56
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74CBT16212CDLR
ACTIVE
SSOP
DL
56
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74CBT16212CDLRG4
ACTIVE
SSOP
DL
56
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.6
1.8
12.0
24.0
Q1
SN74CBT16212CDGGR
TSSOP
DGG
56
2000
330.0
24.4
SN74CBT16212CDGVR
TVSOP
DGV
56
2000
330.0
24.4
6.8
11.7
1.6
12.0
24.0
Q1
SN74CBT16212CDLR
SSOP
DL
56
1000
330.0
32.4
11.35
18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
8.6
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74CBT16212CDGGR
TSSOP
DGG
56
2000
367.0
367.0
45.0
SN74CBT16212CDGVR
TVSOP
DGV
56
2000
367.0
367.0
45.0
SN74CBT16212CDLR
SSOP
DL
56
1000
367.0
367.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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