FINTEK F81216

F81216
F81216D/DG
LPC to 4 UART Datasheet
Release Date: August, 2007
Version: V0.32P
F81216.
August, 2007
V0.32P
F81216
F81216 Datasheet Revision History
Version
Date
0.22P
2003/07/22
0.23P
2003/07/31
Page
14
Revision History
Updated WDT enable timer as power-on setting
24MHz clock input : 10 sec
48MHz clock input : 5 sec
0.24P
2003/09/12
3
Updated pin description(CLKIN: pin12)
0.25P
2003/09/16
32
Updated Application circuit
0.26P
2004/7/29
3
Revised pin 2 description
0.27P
2005/1/6
30
Added “Green Package” ordering information
0.28P
2005/4/25
22
Added Full Duplex Function for IR self test
(Bit 2 of IR1 control register index F1h)
0.29P
2006/1/10
-
Updated application circuit.
0.30P
2006/03/20
-
Modified UART Clock Select Register (F0h) bit 1:0
description. Reserved 01/10/11 clock selection.
0.31P
2007/7/5
-
Company readdress
0.32P
2007/8/20
6
Modify typo of pin type (Pin 43,44,45,46,47)
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
F81216.
August, 2007
V0.32P
F81216
Table of Content
1. General Description.......................................................................................................................................1
2. Feature List....................................................................................................................................................1
3. Pin Configuration ..........................................................................................................................................2
4. Pin Description..............................................................................................................................................3
4.1 ISA/LPC Interface ..................................................................................................................................3
4.2 UART Interface.......................................................................................................................................4
4.3 Power ......................................................................................................................................................7
5. Functional Description ..................................................................................................................................8
5.1 LPC Interface .......................................................................................................................................8
5.2 UART...................................................................................................................................................8
5.2.1 UART Port Register .....................................................................................................................9
5.3 IR Function ........................................................................................................................................13
5.4 Watch Dog Timer Function................................................................................................................13
5.4.1 Watchdog Port Register ..........................................................................................................14
5.5 Serial IRQ ..........................................................................................................................................14
5.5.1 Start Frame.................................................................................................................................15
5.5.2 IRQ/Data Frame.........................................................................................................................15
5.5.3 Stop Frame .................................................................................................................................16
6.
Register Description............................................................................................................................16
6.1 Global Control Register .....................................................................................................................19
6.1.1 Software Reset Register – index 02h .........................................................................................19
6.1.2 Logic Device Select Register – index 07h.................................................................................19
6.1.3 Device ID Register– index 20h, 21h..........................................................................................19
6.1.4 Vendor ID Register– index 23h, 24h..........................................................................................19
6.1.5 Clock Source Select Register – index 25h.................................................................................20
6.1.6 Test Mode Register – index 2Fh ................................................................................................20
6.2 UART 1 Device Control Register (LDN 0) ..........................................................................................20
6.2.1
Device Enable Register – index 30h...................................................................................20
6.2.2
I/O Port Select Register – index 60h...................................................................................20
6.2.3
I/O Port Select Register – index 61h...................................................................................21
6.2.4 IRQ Channel Select Register – index 70h ..............................................................................21
6.2.5 UART 1 Clock Select Register – index F0h ...........................................................................21
6.2.6 IR1 Control Register – index F1h...........................................................................................22
6.3 UART 2 Device Control Register (LDN 1) ..........................................................................................22
6.3.1
Device Enable Register – index 30h...................................................................................22
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6.3.2
I/O Port Select Register – index 60h...................................................................................22
6.3.3
I/O Port Select Register – index 61h...................................................................................23
6.3.4 IRQ Channel Select Register – index 70h ..............................................................................23
6.3.5 UART 2 Clock Select Register – index F0h ...........................................................................23
6.4 UART 3 Device Control Register (LDN 2) ..........................................................................................23
6.4.1
Device Enable Register – index 30h...................................................................................24
6.4.2
I/O Port Select Register – index 60h...................................................................................24
6.4.3
I/O Port Select Register – index 61h...................................................................................24
6.4.4 IRQ Channel Select Register – index 70h ..............................................................................24
6.4.5 UART 3 Clock Select Register – index F0h ...........................................................................25
6.5 UART 4 Device Control Register (LDN 3) ..........................................................................................25
6.5.1
Device Enable Register – index 30h...................................................................................25
6.5.2
I/O Port Select Register – index 60h...................................................................................25
6.5.3
I/O Port Select Register – index 61h...................................................................................25
6.5.4 IRQ Channel Select Register – index 70h ..............................................................................26
6.5.5 UART 4 Clock Select Register – index F0h ...........................................................................26
6.6 Watch Dog Timer Device Control Register (LDN 8) ........................................................................26
6.6.1
Device Enable Register – index 30h...................................................................................26
6.6.2
I/O Port Select Register – index 60h...................................................................................26
6.6.3
I/O Port Select Register – index 61h...................................................................................27
6.6.4
IRQ Channel Select Register – index 70h ..........................................................................27
6.6.5
Timer Status and Control Register – index F0h..................................................................27
6.6.6
Timer Count Number Register – index F1h........................................................................28
7. Electron Characteristic .............................................................................................................................29
7.1 Absolute Maximum Ratings ..............................................................................................................29
7.2 DC Characteristics ................................................................................................................................29
8. Ordering Information ...............................................................................................................................30
9. Package Dimensions ................................................................................................................................31
10. Application Circuit .................................................................................................................................32
F81216.
August, 2007
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F81216
1. General Description
The F81216 mainly provides 3 pure UART ports and one UART+ IR port through LPC.
Each UART includes 16-byte send/receive FIFO, a programmable baud rate generator,
complete modem control capability and an interrupt system.
One watch dog timer is provided for system controlling and the time interval can be
programmed by register or hardware power on setting pin. One clock 24/48MHz input is
necessary, and default is 24MHz.
Powered by 3.3V voltage, the F81216 is in the small
48pin LQFP package (7mm x 7mm).
2. Feature List
Supports LPC interface
Totally provides 4 UART (16550 asynchronous) ports
¾
3 Pure UART
¾
1 UART+IR
1 watch dog timer with WDTOUT# signal
1 frequency input 24/48MHz
Powered by 3Vcc
48-LQFP(7mm x 7mm)
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3. Pin Configuration
F81216D
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4. Pin Description
I/O8t5V-d100
- TTL level bi-directional pin with 8 mA source-sink capability, 5V tolerance, pull-down
100K ohms
I/O12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/OD12
- TTL level bi-directional pin, Open-drain outpu with 12 mA sink capability
PCI5V
- bi-direction pin, slew rate control, 5V tolerance.
OUT12
- Output pin with 12 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
INt
- TTL level input pin
INt5V
- TTL level input pin and 5V tolerance.
INts
- TTL level input pin and schmitt trigger
INts5V
- TTL level input pin and Schmitt trigger, 5V tolerance.
P
- Power
4.1 ISA/LPC Interface
Pin No.
Pin Name
Type
Description
1
PCIRST#
INts
System PCI reset active low.
2
WDT_OUT#
OD12
Watch dog timer output.
When pin 24 power on setting
PS_WDT=0(default), Watch Dog timer time interval setting is
programmed by register. Once power on setting PS_WDT=1,
watch dog timer time interval will be fixed to 10 sec.
4~7
LPC_LAD[3:0]
PCI5V
When in LPC mode, these signal lines communicate address,
control, and data information over the LPC bus between a host
and a peripheral.
8
LCLK
INts5V
In LPC mode, this pin acts as PCI clock input.
9
FRAME#
INts5V
In LPC mode, indicates start of a new cycle or termination of a
broken cycle.
10
SERIRQ
PCI5V
In LPC mode, Serial IRQ input/Output.
12
CLKIN
INt5V
Clock Input
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4.2 UART Interface
Pin No.
Pin Name
Type
Description
13
CTS4#
INt5V
Clear To Send is the modem control input.
14
DSR4#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
15
RTS4#
I/O8t5V-d100
UART 4 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
16
DTR4#
I/O8t5V-d100
UART 4 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
17
SIN4
INt5V
Serial Input.
Used to receive serial data through the
communication link.
18
SOUT4
I/O8t5V-d100
UART 4 Serial Output. Used to transmit serial data out to the
communication link.
PS_2E8_IRQD
Power setting pin to define the IRQD index.
Default PS_2E8_IRQD = 0, IRQF index is programmed by
register.
If PS_2E8_IRQD = 1, setting IRQF index to 0x2E8.
19
DCD4#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
20
RI4#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
21
CTS3#
INt5V
Clear To Send is the modem control input.
22
DSR3#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
23
RTS3#
I/O8t5V-d100
UART 3 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
24
PS_CONF_KE
Power on configuration setting pin. As for detail description,
Y0
please refer to register description.
DTR3#
I/O8t5V-d100
UART 3 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_WDT
Power on setting pin to enable the watch dog timer.
Default PS_WDT=0, WDT time programmed by register.
When PS_WDT=1, WDT time is defined as 10 sec.
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25
SIN3
INt5V
Serial Input.
Used to receive serial data through the
communication link.
26
SOUT3
I/O8t5V-d100
UART 3 Serial Output. Used to transmit serial data out to the
communication link.
PS_3E8_IRQC
Power setting pin to define the IRQC index.
Default PS_3E8_IRQC = 0, IRQF index is programmed by
register.
If PS_3E8_IRQC = 1, setting IRQC index to 0x3E8.
27
DCD3#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
28
RI3#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
31
CTS2#
INt5V
Clear To Send is the modem control input.
32
DSR2#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
33
RTS2#
I/O8t5V-d100
UART 2 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
34
PS_CONF_KE
Power on configuration setting pin. As for detail description,
Y1
please refer to register description.
DTR2#
I/O8t5V-d100
UART 2 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_2E0_IRQB
Power setting pin to define the IRQB index.
Default PS_2E0_IRQB = 0, IRQB index is programmed by
register.
If PS_2E0_IRQB = 1, setting IRQB index to 0x2E0.
35
SIN2
INt5V
Serial Input.
Used to receive serial data through the
communication link.
36
SOUT2
I/O8t5V-d100
UART 2 Serial Output. Used to transmit serial data out to the
communication link.
PS_2F8_IRQB
Power setting pin to define the IRQB index.
Default PS_2F8_IRQB = 0, IRQB index is programmed by
register.
If PS_2F8_IRQB = 1, setting IRQB index to 0x2F8.
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37
DCD2#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
38
RI2#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
39
CTS1#
INt5V
Clear To Send is the modem control input.
40
DSR1#
INt5V
Data Set Ready. An active low signal indicates the modem or
data set is ready to establish a communication link and transfer
data to the UART.
41
RTS1#
I/O8t5V-d100
UART 1 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
Power on configuration setting. Default PS_CONF_2E = 0,
PS_CONF_2E
setting the configuration to 0x4E. If PS_CONF_2E =1, setting
the configuration to 0x2E.
42
DTR1#
I/O8t5V-d100
UART 1 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to communicate.
PS_3E0_IRQA
Power setting pin to define the IRQA index.
Default PS_3E0_IRQA = 0, IRQB index is programmed by
register.
If PS_3E0_IRQA = 1, setting IRQA index to 0x3E0.
43
SIN1
INt5V
Serial Input.
Used to receive serial data through the
communication link.
44
SOUT1
I/O8t5V-d100
UART 1 Serial Output. Used to transmit serial data out to the
communication link.
Power setting pin to define the IRQA index.
PS_3F8_IRQA
Default PS_3F8_IRQA = 0, IRQA index is programmed by
register.
If PS_3F8_IRQA = 1, setting IRQA index to 0x3F8.
45
DCD1#
INt5V
Data Carrier Detect.
An active low signal indicates the
modem or data set has detected a data carrier.
46
RI1#
INt5V
Ring Indicator.
An active low signal indicates that a ring
signal is being received from the modem or data set.
47
IRRX1
INts5V
Infrared Receiver input.
48
IRTX1
OUT12
Infrared Transmitter Output.
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4.3 Power
Pin No.
Pin Name
Type
Description
11,30
VCC
P
3.3V power supply.
3, 29
GND
P
Ground.
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5. Functional Description
The F81216 totally provides 4 UART ports through LPC interface. Among 4 UART ports,
one ports can support serial infrared communication.
Besides, each UART includes 16-byte
send/receive FIFO, a programmable baud rate generator, completed modem control
capability and interrupt system.
One watch dog timer is provided for system controlling and the time interval can be
programmed by register or hardware power on setting pin.
This IC needs one clock 24/48MHz input, and default is 24MHz.
Powered by 3.3V voltage, the
F81216 is in 48 pin LQFP
5.1
LPC Interface
The F81216 can support LPC interface serving as a bus interface between host
(chipset) and peripheral (I/O chip)
by hardware trapping.
less pins and more efficient transmission.
This interface provides much
Data transfer on the LPC bus is serialized over a
4 bit bus. The general characteristics of the interface implemented in F81216 are listed as
below:
‹
One control line, namely LPC_FRAME#, which is used by the host to start or stop
transfers. No peripherals drive this signal.
‹
The LPC_LAD[3:0] bus, which communicates information serially.
The information
conveyed is cycle type, cycle direction, chip selection, address, data, and wait states.
‹
PCIRST# is an active low reset signal.
‹
An additional 33 MHz PCI clock is needed in the F81216 for synchronization.
‹
Interrupt requests are issued through LPC_SERIRQ.
5.2
UART
A Universal Asynchronous Receiver/Transmitter (UART) is used to implement serial
communication. The F81216 incorporates four fully function UART compatible with NS16550D.
The UART ports perform serial to parallel conversion on receiving characters and parallel to
serial conversion on transmitting characters. The controllable characteristics of the data
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transmission are baud rate, number of information bits per character, type of parity checking,
number of stop bits and breaking the transmission.
The serial format is a start bit, followed by
five to eight data bits, a parity bit(if programmable), and one, one and half, or two stop bits.
The
UART also includes completed modem control capability and interrupt system that may be
software trailed to the computing time required to handle the communication link.
The UART
also has a FIFO mode to reduce the number of interrupts presented to the CPU.
In the UART,
there is 16-byte FIFO for both receive and transmit mode.
5.2.1 UART Port Register
5.2.1.1
Receiver Buffer Register – Base + 0
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
RBR[7:0]
R/W
R
Description
The data received .
Read only when LCR[7] is 0
5.2.1.2
Transmitter Holding Register – Base + 0
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
THR[7:0]
R/W
W
Description
Data to be transmitted.
Write only when LCR[7] is 0
5.2.1.3
Divisor Latch ( LS ) – Base + 0
Power-on default [7:0] = 0x01h.
Bit
7:0
Name
DLL[7:0]
R/W
R/W
Description
Baud generator divisor low byte.
Access only when LCR[7] is 1.
5.2.1.4
Divisor Latch ( MS ) – Base + 1
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
DLM[7:0]
R/W
R/W
Description
Baud generator divisor high byte.
Access only when LCR[7] is 1.
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5.2.1.5
Interrupt Enable Register – Base + 1
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:4
Reserved
R/W
Return 0 when read. Access only when LCR[7] is 0
3
EDSSI
R/W
Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2
ELSI
R/W
Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1
ETBFI
R/W
Enable Transmitter Holding Register Empty Interrupt. Access only
when LCR[7] is 0.
0
ERBFI
R/W
Enable Received Data Available Interrupt. Access only when LCR[7]
is 0
5.2.1.6
Interrupt Identification Register – Base + 2
Power-on default [7:0] = 0x01h.
Bit
7
Name
FIFO_EN
R/W
R
Description
0 : FIFO is disabled
1 : FIFO is enabled.
6
FIFO_EN
R
0 : FIFO is disabled.
1 : FIFO is enabled.
5:4
Reserved
R
Return 0 when read.
3:1
IRQ_ID[2:0]
R
000 : Interrupt is caused by Modem Status
001 : Interrupt is caused by Transmitter Holding Register Empty
010 : Interrupt is caused by Received Data Available.
110 : Interrupt is caused by Character Timeout
011 : Interrupt is caused by Line Status..
0
IRQ_PENDN
R
1 : Interrupt is not pending.
0 : Interrupt is pending.
5.2.1.7
FIFO Control Register – Base + 2
Power-on default [7:0] = 0x00h.
Bit
7:6
Name
RCVR_TRIG[1:0]
R/W
W
Description
00 : Receiver FIFO trigger level is 1.
01 : Receiver FIFO trigger level is 4.
10 : Receiver FIFO trigger level is 8.
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11 : Receiver FIFO trigger level is 14.
5:3
Reserved
W
2
CLRTX
W
1 : Reset the transmitter FIFO.
1
CLRRX
W
1 : Reset the receiver FIFO.
0
FIFO_EN
W
0 : Disable FIFO
1 : Enable FIFO
5.2.1.8
Line Control Register – Base + 3
Power-on default [7:0] = 0x00h.
Bit
7
Name
DLAB
R/W
R/W
Description
0 : Divisor Latch can’t be accessed.
1 : Divisor Latch can be accessed via Base and Base+1.
6
SETBRK
R/W
1 : Transmit a break condition.
0 : Transmitter is in normal condition.
5:3
STKPAR
R/W
XX0 : Parity Bit is disable
EPS
001 : Parity Bit is odd.
PEN
011 : Parity Bit is even
101 : Parity Bit is logic 1
111 : Parity Bit is logic 0
2
STB
R/W
0 : Stop bit is one bit
1 : When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
1:0
WLS[1:0]
R/W
00 : Word length is 5 bit
01 : Word length is 6 bit
10 : Word length is 7 bit
11 : Word length is 8 bit
5.2.1.9
MODEM Control Register – Base + 4
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
LOOP
R/W
0 : UART in normal condition.
1 : UART is internal loop back
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3
OUT2
R/W
0 : All interrupt is disable.
1 : Interrupt is enabled/disabled by IER.
2
OUT1
R/W
Read from MSR[6] is loop back mode
1
RTS
R/W
0 : RTS# is forced to logic 1
1 : RTS# is forced to logic 0
0
DTR
R/W
0 : DTR# is forced to logic 1
1 : DTR# is forced to logic 0
5.2.1.10 Line Status Register – Base + 5
Power-on default [7:0] = 0x60h.
Bit
7
Name
RCR_ERR
R/W
R
Description
0 : No error in the FIFO when FIFO is enabled
1 : Error in the FIFO when FIFO is enabled.
6
TEMT
R
0 : Transmitter is in transmitting.
1 : Transmitter is empty.
5
THRE
R
0 : Transmitter Holding Register is not empty.
1 : Transmitter Holding Register is empty.
4
BI
R
0 : No break condition detected.
1 : A break condition is detected.
3
FE
R
0 : Data received has no frame error.
1 : Data received has frame error.
2
PE
R
0 : Data received has no parity error.
1 : Data received has parity error.
1
OE
R
0 : No overrun condition occur.
1 : A overrun condition occur.
0
DR
R
0 : No data is ready for read.
1 : Data is received .
5.2.1.11 MODEM Status Register – Base + 6
Power-on default [7:0] = 0xX0h.
Bit
7
Name
DCD
R/W
R
Description
Complement of DCD# input. In loop back mode, this bit is equivalent
to OUT2 in MCR.
6
RI
R
Complement of RI# input. In loop back mode , this bit is equivalent to
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OUT1 in MCR
5
DSR
R
Complement of DSR# input. In loop back mode , this bit is
equivalent to DTR in MCR
4
CTS
R
Complement of CTS# input. In loop back mode , this bit is equivalent
to RTS in MCR
3
DDCD
R
0 : No state changed at DCD#.
1 : State changed at DCD#.
2
TERI
R
0 : No Trailing edge at RI#.
1 : A low to high transition at RI#.
1
DDSR
R
0 : No state changed at DSR#.
1 : State changed at DSR#.
0
DCTS
R
0 : No state changed at CTS#.
1 : State changed at CTS#.
5.2.1.11 Scratch Register – Base + 7
Power-on default [7:0] = 0x00h.
Bit
7:0
5.3
Name
SCR_DATA[7:0]
R/W
R/W
Description
Scratch register.
IR Function
The F81216 infrared interface provides a two way wireless communications port using
infrared as the transmission medium. The IrDA 1.0 (SIR) is found in UART1 IrDA SIR specifies
asynchronous serial communication at baud rate up to 115.2Kbps. Each byte is sent serial LSB first
beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the
beginning of the serial bit time. A one is signaled by the absence of an infrared pulse during the bit
time. IRTX acts as a transmit pin and IRRX acts as a receiving one. As for detail description, please
refer to register description.
5.4
Watch Dog Timer Function
Watch dog timer is provided for system controlling. If time-out can trigger one signal to low
level, the signal default is tri-state (need external pull up resister).
The time interval has three ways:
One is the hardware power on setting to enable, timer set to 10 second (24MHz). If 48MHz
clock input, the timer is set to 5 second.
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Two is programmed by registers.
The other is set the base address into registers, and use the base address the control it.
The timer unit has three kinds: 10mS, 1S, 1Min.
5.4.1
Watchdog Port Register
5.4.1.1
Timer Status and Control Register – Base + 0
Power-on default [7:0] = 0x02 when DTR3#/PS_WDT is pull-up, else 0x0.
Bit
Name
R/W
Description
7:3
Reserved
R/W
Return 0 when read.
2:1
WDT_UNIT[1:0]
R/W
00 : Timer Unit is 10ms.
01 : Timer Unit is 1 second
10 : Timer Unit is 1 minute.
11 : reserved.
0
WDT_EVENT
R/W
When read
0 : no time out occur.
1 : time out has occurred.
when write
0 : no action
1 : clear the time out status.
5.4.1.2
Timer Count Number Register – Base + 1
Power-on default [7:0] = 0x0Ah when DTR3#/PS_WDT is pull-up , else 0x00h.
Bit
7:0
Name
WDT_CNT[7:0]
R/W
Description
R/W
The number of count for watchdog timer.
Write the same value to enable the timer, write 0 to disable timer.
5.5
Serial IRQ
F81216 supports a serial IRQ scheme.
Because more than one device may need to share
the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI
clock.
The serial interrupt is transferred on the SERIRQ signal, one cycle consisting of three
frames types: a start frame, several IRQ/Data frame, and one Stop frame.
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F81216
5.5.1 Start Frame
There are two modes of operation for the SERIRQ Start frame: Quiet mode and Continuous
mode.
In the Quiet mode, the peripheral drives the SERIRQ signal active low for one clock, and
then tri-states it.
This brings all the states machines of the peripherals from idle to active states.
The host controller will then take over driving SERIRQ signal low in the next clock and will continue
driving the SERIRQ low for programmable 3 to 7 clock periods.
This makes the total number of
clocks low for 4 to 8 clock periods. After these clocks, the host controller will drive the SERIRQ high
for one clock and then tri-states it.
In the Continuous mode, only the host controller initiates the
START frame to update IRQ/Data line information.
low for 4 to 8 clock periods.
The host controller drives the SERIRQ signal
Upon a reset, the SERIRQ signal is defaulted to the Continuous mode
for the host controller to initiate the first Start frame.
5.5.2 IRQ/Data Frame
Once the start frame has been initiated, all the peripherals must start counting frames based
on the rising edge of the start pulse.
Each IRQ/Data Frame is three clocks: Sample phase,
Recovery phase, and Turn-around phase. During the Sample phase, the peripheral drives SERIRQ
low if the corresponding IRQ is active.
left tri-stated.
If the corresponding IRQ is inactive, then SERIRQ must be
During the Recovery phase, the peripheral device drives the SERIRQ high.
During
the Turn-around phase, the peripheral device left the SERIRQ tri-stated. The IRQ/Data Frame has
a number of specific order, as shown in Table 5-1. The F81216 is only support IRQ3, IRQ4, IRQ5,
IRQ9, IRQ10, and IRQ11.
Table 5-1 IRQSER Sampling periods
IRQ/Data Frame
Signal Sampled
# of clocks past Start
1
IRQ0
2
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F81216
2
IRQ1
5
3
SMI#
8
4
IRQ3
11
5
IRQ4
14
6
IRQ5
17
7
IRQ6
20
8
IRQ7
23
9
IRQ8
26
10
IRQ9
29
11
IRQ10
32
12
IRQ11
35
13
IRQ12
38
14
IRQ13
41
15
IRQ14
44
16
IRQ15
47
17
IOCHCK#
50
18
INTA#
53
19
INTB#
56
20
INTC#
59
21
INTD#
62
32:22
Unassigned
95
5.5.3 Stop Frame
After all IRQ/Data Frames have completed, the host controller will terminate SERIRQ by
a Stop frame.
Only the host controller can initiate the Stop frame by driving SERIRQ low for 2 or 3
clocks.
If the Stop Frame is low for 2 clocks, the next SERIRQ cycle's Sample mode is the Quiet
mode.
If the Stop Frame is low for 3 clocks, the next SERIRQ cycle's Sample mode is the
Continuous mode.
6. Register Description
Registers are programmed by port 0x4E and 0x4F. 0x4E is the index port and 0x4F is the data port .
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To enable configuration registers programming, entry key must output twice to index port
continuously. The entry key is decided by power on setting pins RTS2#/PS_CONF_KEY1 and
RTS3#/PS_CONF_KEY0 as following:
RTS2#/PS_CONF_KEY1
RTS3#/PS_CONF_KEY0
Entry key
0
0
0x77 ( default )
0
1
0xA0
1
0
0x87
1
1
0x67
To exit configuration registers programming, output 0xAA to index port.
Sample code for configuration:
1. Clock in used 48MHz, UART 1~6 address (0x3f8, 0x2f8, 0x3e8, 0x2e8,IRQ(3, 4, 5 ,9, Entry
key is 0x77:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77);
//Entry configuration mode
outportb(0x4e, 0x25);
//Select register index 0x25
outportb(0x4f, 0x01);
//Set bit 0 to 1 select clock input to 48MHz
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x00);
//Select LDN 0
outportb(0x4e, 0x60);
//Select LDN 0 register index 0x60
outportb(0x4f, 0x03);
//Set UART 1 base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 0 register index 0x61
outportb(0x4f, 0xf8);
//Set UART 1 base address low byte to 0xf8
outportb(0x4e, 0x70);
//Select LDN 0 register index 0x70
outportb(0x4f, 0x03);
//Set UART 1 interrupt channel to IRQ 3
outportb(0x4e, 0x30);
//Select LDN 0 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 1
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x01);
//Select LDN 1
outportb(0x4e, 0x60);
//Select LDN 1 register index 0x60
outportb(0x4f, 0x02);
//Set UART 2 base address high byte to 0x02
outportb(0x4e, 0x61);
//Select LDN 1 register index 0x61
outportb(0x4f, 0xf8);
outportb(0x4e, 0x70);
//Set UART 2 base address low byte to 0xf8
//Select LDN 1 register index 0x70
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outportb(0x4f, 0x04);
//Set UART 2 interrupt channel to IRQ 4
outportb(0x4e, 0x30);
//Select LDN 1 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 2
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x02);
//Select LDN 2
outportb(0x4e, 0x60);
//Select LDN 2 register index 0x60
outportb(0x4f, 0x03);
//Set UART 3 base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 2 register index 0x61
outportb(0x4f, 0xe8);
//Set UART 3 base address low byte to 0xe8
outportb(0x4e, 0x70);
//Select LDN 2 register index 0x70
outportb(0x4f, 0x05);
//Set UART 3 interrupt channel to IRQ 5
outportb(0x4e, 0x30);
//Select LDN 2 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 3
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x03);
//Select LDN 3
outportb(0x4e, 0x60);
//Select LDN 3 register index 0x60
outportb(0x4f, 0x02);
//Set UART 4 base address high byte to 0x02
outportb(0x4e, 0x61);
//Select LDN 3 register index 0x61
outportb(0x4f, 0xe8);
//Set UART 4 base address low byte to 0xe8
outportb(0x4e, 0x70);
//Select LDN 3 register index 0x70
outportb(0x4f, 0x09);
//Set UART 4 interrupt channel to IRQ 9
outportb(0x4e, 0x30);
//Select LDN 3 register index 0x30
outportb(0x4f, 0x01);
//Enable UART 4
outportb(0x4e, 0xaa);
//Exit configuration mode
2. Set Watch Dog timer base address 0x300~0x301:
outportb(0x4e, 0x77);
outportb(0x4e, 0x77);
//Entry configuration mode
outportb(0x4e, 0x07);
//Select register index 0x07
outportb(0x4f, 0x08);
//Select LDN 8
outportb(0x4e, 0x60);
//Select LDN 8 register index 0x60
outportb(0x4f, 0x03);
//Set Watch Dog timer base address high byte to 0x03
outportb(0x4e, 0x61);
//Select LDN 8 register index 0x61
outportb(0x4f, 0x00);
//Set Watch Dog Timer base address low byte to 0x00
outportb(0x4e, 0x30);
//Select LDN 8 register index 0x30
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F81216
outportb(0x4f, 0x01);
//Enable Watch Dog Timer Device
outportb(0x4e, 0xaa);
//Exit configuration mode
3. Set Watch Dog timer to 20 second used base address 0x300~0x301:
outportb(0x300, 0x03); //Select unit to one second and clear time out status
outportb(0x301, 0x14);
outportb(0x301, 0x14);
6.1
//Set timer to 20 second and enable timer
Global Control Register
6.1.1 Software Reset Register – index 02h
Power-on default [7:0] = 0x00h
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
SWRST
R/W
Write 1 to reset configuration register. This bit is auto cleared.
6.1.2 Logic Device Select Register – index 07h
Power-on default [7:0] = 0x00h
Bit
7:0
Name
LDN[7:0]
R/W
R/W
Description
00h : Select UART 1 device configuration register
01h : Select UART 2 device configuration register
02h : Select UART 3 device configuration register
03h : Select UART 4 device configuration register
08h : Select Watchdog Timer device configuration register
6.1.3 Device ID Register– index 20h, 21h
Power-on default [7:0], 0x02h for index 20h, 0x08h for index 21h
Bit
7:0
Name
DEVID
R/W
R
Description
Return 0208h when read index 20h and 21h respectively, indicate the
device ID.
6.1.4 Vendor ID Register– index 23h, 24h
Power-on default [7:0], 0x19h for index 23h, 0x34h for index 24h
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F81216
Bit
7:0
Name
VENDID
R/W
R
Description
Return 1934h when read index 23h and 24h respectively, indicate the
vendor ID of Fintek.
6.1.5 Clock Source Select Register – index 25h
Power-on default [7:0], 0x00h
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
CLK_SEL
R/W
1 : The CLKIN is 48MHz
0 : The CLKIN is 24MHz.
This bit must program to indicate the frequency of the clock source, or
the device will not function correctly.
6.1.6 Test Mode Register – index 2Fh
Power-on default [7:0], 0000_0000b
Bit
7:0
Name
TESTMODE
R/W
R/W
Description
Test mode register, reserved for Fintek use only.
6.2 UART 1 Device Control Register (LDN 0)
6.2.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URA_EN
R/W
0 : Disable UART 1.
1 : Enable UART 1..
6.2.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pullup,
else 0x00h.
Bit
Name
R/W
Description
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F81216
7:0
URA_BASE[15:8]
6.2.3
R/W
UART 1 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT1/PS_3F8_IRQA is pull-up,
0xE0h when DTR1#/PS_3E0_IRQA is pull-up, else 0x00h.
Bit
7:0
Name
URA_BASE[7:0]
6.2.4
R/W
R/W
Description
UART 1 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URAIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URAIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURAIRQ[3:0]
6.2.5
R/W
Select the Serial IRQ channel.
UART 1 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:4
Reserved
R/W
Return 0 when read.
3
RXW4C_IRA
R/W
0 : No reception delay when SIR is changed from TX to RX.
1 : Reception delay 4 character-time when SIR is changed from TX
to RX.
2
TXW4C_IRA
R/W
0 : No transmission delay when SIR is changed from RX to TX.
1 : Transmission delay 4 character-time when SIR is changed from
RX to TX.
1:0
SELURACLK1
SELURACLK0
R/W
00 : UART 1 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
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6.2.6
IR1 Control Register – index F1h
Power-on default [7:0] = 0x44h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 010b when read.
4:3
IRA_MODE1
R/W
0X: Disable IR1 function.
IRA_MODE0
10 : Enable IR1 function, active pulse is 1.6uS.
11 : Enable IR1 function, active pulse is 3/16 bit time.
2
Half_Full_Duplex
R/W
0 : Full Duplex function for IR self test.
1 : Half Duplex function.
Return 1 when read.
1
TXINV_IRA
R/W
0 : IRTX1 is not inversed.
1 : Inverse the IRTX1.
0
RXINV_IRA
R/W
0 : IRRX1 is not inversed.
1 : Inverse the IRRX1.
6.3 UART 2 Device Control Register (LDN 1)
6.3.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull-up,
else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URB_EN
R/W
0 : Disable UART 2.
1 : Enable UART 2.
6.3.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pullup,
else 0x00h.
Bit
Name
R/W
Description
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7:0
URB_BASE[15:8]
6.3.3
R/W
UART 2 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT2/PS_2F8_IRQB is pull-up,
0xE0h when DTR2#/PS_2E0_IRQB is pull-up, else 0x00h.
Bit
7:0
Name
URB_BASE[7:0]
6.3.4
R/W
R/W
Description
UART 2 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull-up,
else 0x00h
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URBIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URBIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURAIRQ[3:0]
6.3.5
R/W
Select the Serial IRQ channel.
UART 2 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:2
Reserved
R/W
Return 0 when read.
1:0
SELURACLK1
R/W
00 : UART 2 clock source is 1.8462MHz ( 24MHz/13 )
SELURACLK0
01/10/11 selection reserved.
6.4 UART 3 Device Control Register (LDN 2)
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6.4.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URC_EN
R/W
0 : Disable UART 3.
1 : Enable UART 3.
6.4.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URC_BASE[15:8]
R/W
6.4.3
Description
UART 3 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = E8h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URC_BASE[7:0]
R/W
6.4.4
Description
UART 3 I/O Port Address low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x05h when SOUT3/PS_3E8_IRQC is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:6
Reserved
R/W
Return 0 when read.
5
URCIRQ_MODE
R/W
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
4
URCIRQ_SHAR
R/W
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURCIRQ[3:0]
R/W
Select the Serial IRQ channel.
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F81216
6.4.5
UART 3 Clock Select Register – index F0h
Power-on default [7:0] = 0000_0000b.
Bit
Name
R/W
Description
7:2
Reserved
R/W
Return 0 when read.
1:0
SELURCCLK1
R/W
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
SELURCCLK0
01/10/11 selection reserved.
6.5 UART 4 Device Control Register (LDN 3)
6.5.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
URD_EN
R/W
0 : Disable UART 4.
1 : Enable UART 4.
6.5.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URD_BASE[15:8]
R/W
6.5.3
Description
UART 4 I/O Port Address high byte.
I/O Port Select Register – index 61h
Power-on default [7:0] = 0xE8h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:0
Name
R/W
URD_BASE[7:0]
R/W
Description
UART 4 I/O Port Address low byte.
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F81216
6.5.4
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x09h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:6
5
Reserved
URDIRQ_MODE
R/W
R/W
4
URDIRQ_SHAR
R/W
Return 0 when read.
0 : PCI IRQ sharing mode
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
3:0
SELURDIRQ[3:0]
R/W
6.5.5
Select the Serial IRQ channel.
UART 4 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:2
Reserved
R/W
Return 0 when read.
1:0
SELURDCLK1
R/W
00 : UART 4 clock source is 1.8462MHz ( 24MHz/13 )
SELURDCLK0
6.6
01/10/11 selection reserved.
Watch Dog Timer Device Control Register (LDN 8)
6.6.1
Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
Name
R/W
Description
7:1
Reserved
R/W
Return 0 when read.
0
WDT_EN
R/W
0 : Disable Watchdog Timer.
1 : Enable Watchdog Timer.
6.6.2
I/O Port Select Register – index 60h
Power-on default [7:0] = 0x04h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
WDT_BASE[15:8]
R/W
R/W
Description
I/O Base high byte.
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6.6.3
I/O Port Select Register – index 61h
Power-on default [7:0] = 0x42h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
R/W
WDT_BASE[7:0]
R/W
6.6.4
Description
I/O Base low byte.
IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x00h.
Bit
Name
R/W
Description
7:5
Reserved
R/W
Return 0 when read.
4
WDTIRQ_EN
R/W
0 : Time out is asserted only via WDT_OUT#.
1 : Time out is asserted via IRQ and WDT_OUT#.
3:0
SELWDTIRQ[3:0]
R/W
In LPC mode , select the Serial IRQ channel.
In ISA mode , select one of six IRQ pins .
03h : use serial IRQ channel 3 in LPC mode or use ISA_IRQA in ISA
mode.
04h : use serial IRQ channel 4 in LPC mode or use ISA_IRQB in ISA
mode.
05h : use serial IRQ channel 5 in LPC mode or use ISA_IRQC in ISA
mode.
09h : use serial IRQ channel 9 in LPC mode or use ISA_IRQD in ISA
mode.
0Ah : use serial IRQ channel 10 in LPC mode or use ISA_IRQE in
ISA mode.
0Bh : use serial IRQ channel 11 in LPC mode or use ISA_IRQF in
ISA mode.
Otherwise will disable the interrupt.
6.6.5
Timer Status and Control Register – index F0h
Power-on default [7:0] = 0x02h when DTR3#/PS_WDT is pull-up , else 0x00h.
Bit
Name
R/W
Description
7:3
Reserved
R/W
Return 0 when read.
2:1
WDT_UNIT[1:0]
R/W
00 : Timer Unit is 10ms.
01 : Timer Unit is 1 second
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F81216
10 : Timer Unit is 1 minute.
11 : reserved.
0
WDT_EVENT
R/W
When read
0 : no time out occur.
1 : time out has occurred.
when write
0 : no action
1 : clear the time out status.
6.6.6
Timer Count Number Register – index F1h
Power-on default [7:0] = 0x0Ah when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
WDT_CNT[7:0]
R/W
Description
R/W
The number of count for watchdog timer.
Write the same value twice to enable the timer, otherwise will disable
timer.
-28-
August, 2007
V0.32P
F81216
7. Electron Characteristic
7.1
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage
-0.5 to 4.0
V
Input Voltage
-0.5 to 5.5
V
Operating Temperature
0 to +70
°C
Storage Temperature
-55 to +150
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the
life and reliability of the device.
7.2 DC Characteristics
((Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA
Input Low Voltage
VIL
0.8
Input High Voltage
VIH
2.0
Output Low Current
IOL
10
Output High Current
IOH
Input High Leakage
Input Low Leakage
V
V
12
mA
VOL = 0.4V
-10
mA
VOH = 2.4V
ILIH
+10
µA
VIN = VDD
ILIL
-10
µA
VIN = 0V
-12
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level
input
Input Low Threshold Voltage
Vt-
0.5
0.8
Input High Threshold Voltage
Vt+
1.6
2.0
Output Low Current
IOL
10
12
Output High Current
IOH
V
VDD = 3.3 V
V
VDD = 3.3 V
mA
VOL = 0.4 V
-10
mA
VOH = 2.4V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
-12
-29-
1.1
2.4
August, 2007
V0.32P
F81216
7.2 DC Characteristics, continued
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
mA
VOL = 0.4V
mA
VOH = 2.4V
mA
VOL = 0.4V
mA
VOL = 0.4V
OUT12t - TTL level output pin with source-sink capability of 12 mA
Output Low Current
IOL
Output High Current
IOH
12
16
-14
-12
OD8 - Open-drain output pin with sink capability of 8 mA
Output Low Current
IOL
6
8
OD16 - Open-drain output pin with sink capability of 16 mA
Output Low Current
IOL
12
16
I/OOD16ts - TTL level bi-directional pin, can select to OD or OUT by register, with 16 mA
source-sink capability
Input Low Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 3.3 V
Output Low Current
IOL
6
8
mA
VOL = 0.4 V
Output High Current
IOH
-12
mA
VOH = 2.4V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0V
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
-16
INt - TTL level input pin
2.0
V
INts - TTL level Schmitt-triggered input pin
Input Low Threshold Voltage
Vt-
0.5
0.8
1.1
V
VDD = 3.3V
Input High Threshold Voltage
Vt+
1.6
2.0
2.4
V
VDD = 3.3V
Input High Leakage
ILIH
+10
µA
VIN = VDD
Input Low Leakage
ILIL
-10
µA
VIN = 0 V
8. Ordering Information
Part Number
Package Type
Production Flow
F81216D
48 pin LQFP (Normal)
Commercial, 0°C to +70°C
F81216DG
48 pin LQFP (Green Package)
Commercial, 0°C to +70°C
-30-
August, 2007
V0.32P
F81216
9. Package Dimensions
48pin-LQFP
HD
D
25
36
Dimension in inch
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
24
37
E
48
HE
13
1
e
b
Min.
12
0
Nom.
Max.
Dimension in mm
Min.
Nom.
Max.
---
---
1.60
0.05
---
0.15
1.35
1.40
1.45
0.17
0.20
0.27
0.09
---
0.20
7.00
7.00
0.50
9.00
9.00
0.45
0.60
0.75
1.00
---
0.08
---
0
3.5
7
Notes:
c
A2
Seating Plane
See Detail F
A
A1
y
L
L1
Detail F
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
Feature Integration Technology Inc.
Headquarters
Taipei Office
3F-7, No 36, Tai Yuan St.,
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-5600168
TEL : 866-2-8227-8027
FAX : 886-3-5600166
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this datasheet belong to their respective owner
-31-
August, 2007
V0.32P
10. Application Circuit
(Power On Setting Pin)
VCC3V
IRTX
IRRX
RI1#
DCD1#
SOUT1
SIN1
DTR1#
RTS1#
DSR1#
CTS1#
RI2#
DCD2#
C2
0.1U
PCIRST#
WDT_OUT#
GND
LAD3
LAD2
LAD1
LAD0
LCLK
LFRAM#
SERIRQ
VCC
CLKIN
F81216D
CTS4#
DSR4#
RTS4#
DTR4#
SIN4
SOUT4
DCD4#
RI4#
CTS3#
DSR3#
RTS3#
DTR3#
CLK24IN
1
2
PIN_3 3
PIN_4
4
PIN_5
5
PIN_6
6
PIN_7
7
PIN_8
8
PIN_9
9
PIN_10
10
PIN_11
11
PIN_12 VCC3V
12
R12
R13
R14
R15
1k
1k
1k
PIN_44
4.7K
PIN_42
R11
4.7K
PIN_41
R10
4.7K
PIN_36
R9
4.7K
PIN_34
R8
4.7K
PIN_33
R7
4.7K
PIN_26
R6
4.7K
PIN_24
R5
4.7K
PIN_23
R4
4.7K
SOUT2
SIN2
DTR2#
RTS2#
DSR2#
CTS2#
VCC
GND
RI3#
DCD3#
SOUT3
SIN3
36
35
34
33
32
31
30
29
28
27
26
25
PIN_36
PIN_35
PIN_34
PIN_33
PIN_32
PIN_31
PIN_30
PIN_29
PIN_28
PIN_27
PIN_26
PIN_25
1k
R16
R17
R18
R19
R20
R21
1k
1k
1k
1k
1k
1k
R2 on and R12 off: UART 4 addr:0x2e8 IRQ9; off:UART 4 disabled.
R5 on and R15 off: UART 3 addr:0x3e8 IRQ5; off:UART 3 disabled.
R8 on and R18 off: UART 2 addr:0x2f8 irq4; R7 on, R17 off and R8 off, R18
on : UART 2 addr:0x2e0 IRQ4; R7 off, R17 on and R8 off, R18 on:UART 2
disabled.
VCC3V
R11 on and R21 off: UART 1 addr:0x3f8 irq3; R10 on, R20 off and R11 off, R21
on: UART 1 addr:0x3e0 IRQ3; R10 off, R20 on and R11 off, R21 on:UART 1
disabled.
C1
0.1U
R4 on and R14 off: Watch Dog Timer enabled and setting to 10 second when the
clock input is 24Mhz. If the clock input is 48Mhz , the timer is setting to
5 second.
off :disabled.
13
14
15
16
17
18
19
20
21
22
23
24
LAD3
LAD2
LAD1
LAD0
PCICLK
LFRAME#
SERIRQ
PIN_1
PIN_2
DCD2#
SIN2
DSR2#
CTS2#
RI2#
SOUT2
DTR2#
RTS2#
R16 is 0 when R6=1, R16 is 1 when R6=0.
R13 is 0 when R3=1, R13 is 1 when R3=0.
R19 is 0 when R9=1, R19 is 1 when R9=0.
PIN_13
PIN_14
PIN_15
PIN_16
PIN_17
PIN_18
PIN_19
PIN_20
PIN_21
PIN_22
PIN_23
PIN_24
PCIRST#
WDT_OUT#
48
47
46
45
44
43
42
41
40
39
38
37
U1
R3
4.7K
PIN_38
PIN_37
VCC3V
R1
4.7K
R2
PIN_18
PIN_48
PIN_47
PIN_46
PIN_45
PIN_44
PIN_43
PIN_42
PIN_41
PIN_40
PIN_39
RTS1#
DTR1#
SOUT1
RI1#
CTS1#
DSR1#
SIN1
DCD1#
IRRX
IRTX
RTS4#
DTR4#
SOUT4
RI4#
CTS4#
DSR4#
SIN4
DCD4#
DCD3#
SIN3
DSR3#
CTS3#
RI3#
SOUT3
DTR3#
RTS3#
Entry Key
On:1
0x4e/0x4f
0x77
Off:0
0x2e/0x2f
0x77
0
0x4e/0x4f
0xa0
1
0x2e/0x2f
0xa0
0
0
0x4e/0x4f
0x87
0
1
0x2e/0x2f
0x87
1
1
0
0x4e/0x4f
0x67
1
1
1
0x2e/0x2f
0x67
R6
R3
R9
Address
0
0
0
0
0
1
0
1
0
1
1
1
Title
Feature Integration Technology Inc.
Size
B
Date:
Document Number
F81216D
Tuesday , January 10, 2006
Rev
0.21
Sheet
1
of
2
U2
VCC5V
RTS1#
DTR1#
C3
0.1USOUT1
RI1#
CTS1#
DSR1#
SIN1
DCD1#
20
16
15
13
19
18
17
14
12
11
VCC
U3
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS1
DTR1
SOUT1RI1
CTS1
DSR1
SIN1DCD1
P1
RI1
DTR1
CTS1
SOUT1RTS1
SIN1DSR1
DCD1
-12V
5
9
4
8
3
7
2
6
1
RTS3#
DTR3#
SOUT3
C4
0.1U RI3#
CTS3#
DSR3#
SIN3
DCD3#
20
16
15
13
19
18
17
14
12
11
DB9
RS232
(SOP20)
RTS2#
DTR2#
SOUT2
C5
0.1U RI2#
CTS2#
DSR2#
SIN2
DCD2#
20
16
15
13
19
18
17
14
12
11
VCC
(UART1)
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
1
5
6
8
2
3
4
7
9
10
+12V
RTS3
DTR3
SOUT3RI3
CTS3
DSR3
SIN3DCD3
P2
RI3
DTR3
CTS3
SOUT3RTS3
SIN3DSR3
DCD3
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART3)
U5
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
RS232
(SOP20)
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
RS232
(SOP20)
U4
VCC5V
VCC
1
5
6
8
2
3
4
7
9
10
+12V
VCC5V
RTS2
DTR2
SOUT2RI2
CTS2
DSR2
SIN2DCD2
P3
RI2
DTR2
CTS2
SOUT2RTS2
SIN2DSR2
DCD2
-12V
5
9
4
8
3
7
2
6
1
RTS4#
DTR4#
SOUT4
RI4#
C6
0.1U CTS4#
DSR4#
SIN4
DCD4#
20
16
15
13
19
18
17
14
12
11
DB9
VCC
+12V
DA1
DA2
DA3
RY 1
RY 2
RY 3
RY 4
RY 5
DY 1
DY 2
DY 3
RA1
RA2
RA3
RA4
RA9
GND
-12V
RS232
(SOP20)
(UART2)
1
5
6
8
2
3
4
7
9
10
+12V
RTS4
DTR4
SOUT4RI4
CTS4
DSR4
SIN4DCD4
P4
RI4
DTR4
CTS4
SOUT4RTS4
SIN4DSR4
DCD4
-12V
5
9
4
8
3
7
2
6
1
DB9
(UART4)
VCC3V
JP1
1
2
3
4
5
IRRX
IRTX
C7
HEADER 5
0.1U
(IrDA)
Title
Feature Integration Technology Inc.
Size
B
Date:
Document Number
UART
Tuesday , January 10, 2006
Rev
0.2
Sheet
2
of
2