F71869A
Super I/O + Hardware Monitor
Release Date:October, 2011
Version: V0.19P
F71869A
F71869A Datasheet Revision History
Version
Date
0.10P
2010/04
0.11P
2010/05
0.12P
2010/06
0.13P
2010/07
Page
45, 46
47-136
19
47, 48
65, 66
142-144
10-20
70
90, 91
60, 61
10
140
13, 21
56
74
129, 130
132
133
148
147
50
13, 21
8, 12, 47
0.14P
2010/08
0.15P
2010/08
52
56
58~62
59
60
61, 62
122~126
135
12-13
12-21
131
0.16P
2010/09
0.17P
2011/03
77
140
19
121
112
139-140
150
64
77
60
127
Revision History
Preliminary version
1. Update CIR/CPT function description
2. Update Register
1. Modify pin54 description
2. Add scan code and OVT function description
3. Update RS485 enable register description ⎯ Index F0h
4. DC Characteristics
5. Update Pin Description
6. Update OVT register ⎯ Index 02h
7. Update Fan3 control register ⎯ Index 9Ah
8. Add Multi-Function Select Register 5 ⎯ Index 2Ch
9. Correct Pin Type
10. Add Intel DSW Delay Select Register⎯ Index FCh
11. Update STRAP_PROTECT description
12. Update Configuration Port Select Register ⎯ Index 27h
13. Add Voltage Protection Power Good Select Register ⎯ Index 3Fh
14. Add CIR Registers (CR08)
15. Update ERP PSOUT deb-register ⎯ Index E5h;
ERP S5 Delay Register ⎯ Index E7h
16. Update ERP WDT Timer ⎯ Index EEh
17. Update Application Circuit ⎯ S5# (S4#) , SUS_ACK# (3VA)
1. Update Application Circuit – Correct VIN5 pin name
1. Update Global Control Registers
2. Modify description for STRAP_PROTECT
3. Update GPIO for Scan Code function
4. Update GPIO Device Configuration Registers (LDN CR06)
5. Update UART IRQ Sharing Register ⎯ Index 26h bit 3
6. Update Multi-Function Select Register 1 ~ 5 ⎯ Index 28h ~ 2Ch
7. Add WDT Clock Divisor High Byte ⎯ Index 29h
8. Add WDT Clock Divisor Low Byte ⎯ Index 2Ah
9. Add WDT Clock Fine Tune Count ⎯ Index 2Bh, 2Ch
10. Update GPIO 35 ~ 37 Scan Code Function Registers
11. Update ERP WDT Control register ⎯ Index EDh
Update for LAB version
1. Correct FDC/GPIO PWR Type
2. Correct PWR Type VCC to 3VCC
3. Add WDT Enable Register 30h and Base Address High/Low Register
60h and 61h
4. Add 2D – 2Fh in Voltage reading and limit register
5. Remove PCIRSTIN_N in VDDOK Delay Register ⎯ Index F5h bit 2
6. Correct RSTCON# pin description
7. Update GPIO4 Drive Enable Register -Index B3h bit 5~7
8. Add Auto Swap Register - Index FEh (Powered by VBAT) bit 3
9. Correct VDDOK Delay Register - Index F5h PWROK unit
10. Update Reference Circuit – Add C58
1. Made Clarification & Modification
2. Update Wakeup Control Register - Index 2Dh bit5 description
3. Add Voltage reading and limit - Index 30h, 31h
4. Modify Multi-Function Select Register 3 ⎯ Index 2Ah bit 1:0
5. Modify GPIO5 KBC Emulation Control Register 2 ⎯ Index AFh bit7
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description
63
18, 19
112
0.18P
2011/06
0.19P
2011/10
150, 154
17, 18
148
58
149
-
6. Correct Multi-Function Select Register 5 ( Index 2Ch bit3:1
default velue
7. Modify SCL & SDA Types and Description (pin 57/58/59/60)
8. Modify Auto Swap Register ( Index FEh, bit 7
1. Made Clarification & Modification
2. Update Application Circuits
3. Update FANCTL1~3 Pin Description
4. Add Top Marking Specification
5. Update Multi-Function Select Register 1⎯ Index 28h bit7 Description
6. Update Package Dimension
1.Made Clarification & Modification
2.GPIO Pin Status Register – Index F2h, bit 5 & 4
3.Update Index no.(GPIO7 Output Data Register – Index 81h)
4.Update Index no.(GPIO7 Pin Status Register – Index 82h)
5.Update Index no.(GPIO7 Drive Enable Register – Index 83h)
6.Update Index no.(User Wakeup Code Register – Index FFh)
7.SMB Protocol Select – Index EFh, bit3-0
8.Update Top Marking Specification Description
Please note that all data and specifications are subject to change without notice. All the trade marks of
products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICAT
These products are not designed for use in life support appliances, devices, or systems where malfunction of
these products can reasonably be expected to result in personal injury. Customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any
damages resulting from such improper use or sales.
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Table of Content
1. General Description...............................................................................................................6
2. Feature List ...........................................................................................................................7
3. Pin Configuration.................................................................................................................10
4. Pin Description .................................................................................................................... 11
4.1 Power Pins ................................................................................................................12
4.2 LPC Interface ............................................................................................................12
4.3 FDC ...........................................................................................................................12
4.4 UART and SIR...........................................................................................................14
4.5 Parallel Port...............................................................................................................16
4.6 Hardware Monitor ......................................................................................................17
4.7 ACPI Function Pins ...................................................................................................18
4.8 Power Saving and Others..........................................................................................20
4.9 KBC Function ............................................................................................................21
5. Function Description............................................................................................................22
5.1 Power on Strapping Option........................................................................................22
5.2 Hardware Monitor ......................................................................................................22
5.3 ACPI Function ...........................................................................................................36
5.4 Power Timing Control Sequence ...............................................................................38
5.5 S3_Gate#, S3P5_Gate# and S0P5_Gate# Timing....................................................39
5.6 AMD TSI and Intel PECI 3.0 Functions .....................................................................41
5.7 ErP Power Saving Function.......................................................................................42
5.8 CIR Function .............................................................................................................46
5.9 Intel Cougar Point Timing (CPT)................................................................................47
5.10 Scan Code Function ..................................................................................................48
5.11 Over Voltage Protection.............................................................................................48
6. Register Description ............................................................................................................49
6.1 Global Control Registers ...........................................................................................54
6.2 FDC Registers (CR00) ..............................................................................................64
6.3 UART1 Registers (CR01) ..........................................................................................67
6.4 UART2 Registers (CR02) ..........................................................................................68
6.5 Parallel Port Register (CR03) ....................................................................................69
6.6 Hardware Monitor Registers (CR04) .........................................................................70
6.7 KBC Registers (CR05) ............................................................................................ 110
6.8 GPIO Registers (CR06)........................................................................................... 111
6.9 Watch Dog Timer Registers (CR07) ........................................................................130
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6.10 CIR Registers (CR08)..............................................................................................132
6.11 PME, ACPI, and ERP Power Saving Registers (CR0A) ..........................................133
7. Electrical Characteristics ...................................................................................................144
7.1 Absolute Maximum Ratings.....................................................................................144
7.2 DC Characteristics ..................................................................................................144
8. Ordering Information .........................................................................................................147
9. Top Marking Specification..................................................................................................147
10.Package Dimensions (128-LQFP) ...................................................................................148
11.Application Circuit ............................................................................................................149
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1. General Description
The F71869A which is the featured IO chip for PC system is equipped with one IEEE 1284
Parallel Port, two UART Ports, one 80 port (multi with COM2), Hardware Keyboard Controller,
SIR, CIR with RC6 and SMK QP protocols and one FDC. The F71869A integrates with
hardware monitor, 9 sets of voltage sensor, 3 sets of creative auto-controlling fans and 3
temperature sensor pins for the accurate dual current type temperature measurement for CPU
thermal diode or external transistors 2N3906. Others, the F71869A supports newest AMD TSI
and Intel PECI 3.0 interfaces and INTEL Ibex PEAK SMBus for temperature sensing and
provides the power sequence controller function for AMD platform.
The F71869A provides flexible features for multi-directional application. For instance, the
F71869A provides 58 GPIO pins (multi-pin), IRQ sharing function also designed in UART
feature for particular usage and accurate current mode H/W monitor will be worth in
measurement of temperature, provides 3 modes fan speed control mechanism included Manual
Mode/Stage Auto Mode/Linear Auto Mode for users’ selection.
A power saving function which is in order to save the current consumption when the system is in
the soft off state is also integrated a power saving function. The power saving function supports that
system boot-on not only by pressing the power button but also by the wake-up event. When the
system enters the S4/S5 state, F71869A can cut off the VSB power rail which supplies power
source to the devices like the LAN chip, the chipset, the SIO, the audio codec, DRAM, and etc. The
PC system can be simulated to G3-like state when system enters the S4/S5 states. At the G3-like
state, the F71869A consumes the 5VSB power rail only. The integrated two control pins are utilized
to turn on or off VSB power rail in the G3-like status. The turned on VSB rail is supplied to a wake
up device to fulfill a low power consumption system which supports a wake up function.
These features as above description will help you more and improve product value. Finally,
the F71869A is powered by 3.3V voltage, with the LPC interface in the green package of
128-LQFP (14*14).
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2. Feature List
General Functions
¾Comply with LPC Spec. 1.0
¾Support DPM (Device Power Management), ACPI
¾Support AMD power sequence controller
¾Provides one FDC, two UARTs, Hardware KBC and Parallel Port
¾H/W monitor functions
¾Support AMD TSI Interface, Intel PECI 3.0 interface, Intel Block Read/Write SMBus Interface
¾Support CIR with RC6 and SMK QP protocols
¾Support Intel Cougar Point Timing
¾58 GPIO Pins for flexible application
¾24/48 MHz clock input
¾Packaged in 128-LQFP and powered by 3.3VCC
FDC
¾Compatible with IBM PC AT disk drive systems
¾Variable write pre-compensation with track selectable capability
¾Support vertical recording format
¾DMA enable logic
¾16-byte data FIFOs
¾Support floppy disk drives and tape drives
¾Detects all overrun and under run conditions
¾Built-in address mark detection circuit to simplify the read electronics
¾Completely compatible with industry standard 82077
¾360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
UART
¾Two high-speed 16C550 compatible UART with 16-byte FIFOs
¾Fully programmable serial-interface characteristics
¾Baud rate up to 115.2K
¾Support IRQ sharing
¾Support Ring-In Wakeup
Infrared
¾Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
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Parallel Port
¾One PS/2 compatible bi-directional parallel port
¾Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
¾Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
¾Enhanced printer port back-drive current protection
Keyboard Controller
¾LPC interface support serial interrupt channel 1, 12.
¾Two 16bit Programmable Address fully decoder, default 0x60 and 0x64.
¾Support two PS/2 interface, one for PS/2 mouse and the other for keyboard.
¾Keyboard’s scan code support set1, set2.
¾Programmable compatibility with the 8042.
¾Support both interrupt and polling modes.
¾Fast Gate A20 and Hardware Keyboard Reset.
Hardware Monitor Functions
¾3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors
¾Temperature range -40℃~127℃
¾9 sets voltage monitoring (6 external and 3 internal powers)
¾Voltage monitor supports Over Voltage Protection (OVP)
¾High limit signal (PME#) for Vcore level
¾3 fan speed monitoring inputs
¾3 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans)
¾The Fan PWM output frequency can be programmed to 23.5K or 220Hz for LCD backlight adjustment
¾Stage auto mode ( 2-Limit and 3-Stage)/Linear auto mode/Manual mode
¾Issue PME# and OVT# hardware signals output
¾Case intrusion detection circuit
¾WATCHDOG comparison of all monitored values
Power Saving Controller
¾ACPI Timing and Power Control
¾Wake-up Supported
Integrate AMD TSI Interface
Integrate Intel PECI 3.0 Spec.
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Integrate Intel Cougar Point Timing
Support AMD Power Sequence Controller
Intel Block Read/Write SMBus Interface
System volume control
¾GPIO 35~37, GPIO 50~54 can control the system volume up/down/mute by LPC interface.
¾Windows OSD can detect the system volume control input without any driver installation.
80-Port Interface
¾Monitor 0x80 Port and output the value via signals defined for 7-segment display.
¾High nibble and low nibble are outputted interleaved at 1KHz frequency.
¾80-Port output by LPT or COM2 interface.
Package
¾128-pin LQFP (14*14) Green Package
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3. Pin Configuration
Figure1. F71869A pin configuration (14 *14)
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4. Pin Description
I/O12st,5v
I/O16t,u47k
I/OD12st,5v
I/OD14st,5v
I/OD16st,5v
ILv /OD12st,5v
I/OOD12t
I/OOD12t,5v
I/OOD8st,5v
I/OOD12st,5v
I/OOD24st,5v
ILv/OD8,S1
OOD12,5v
OOD16,5v
O12
O16
O18
O20
O30
O12,5v
O8t5v,u47k
OD12
OD14,5v
OD12,5v
OD24,5v
OD12,5v,u10k
OD16,5v,u10k
INt5v
INst,u47k
INst
INst,lv
INst,5v
AIN
AOUT
P
- TTL level bi-directional pin with schmitt trigger, output with 12 mA sink capability,
5V tolerance.
- TTL level bi-directional pin with 16 mA source-sink cap ability. With internal 47k
pull-up.
- TTL level bi-directional pin with schmitt trigger, Open-drain output with 12 mA
sink capability, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 14 mA
sink capability, 5V tolerance.
- TTL level bi-directional pin with schmitt trigger, Open-drain output with 16 mA
sink capability, 5V tolerance.
- Low level bi-directional pin with schmitt trigger, Open-drain output with 12 mA
sink capability, 5V tolerance.
- TTL level bi-directional pin, can be selected to OD or OUT by register, with 12
mA source-sink capability.
- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA
source-sink capability, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 8 mA sink
capability, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA
sink capability, 5V tolerance.
- TTL level bi-directional pin with schmitt trigger, can be selected to OD or OUT by
register, with 24 mA sink capability, 5V tolerance.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 8mA drive and
1mA sink capability.
- OD or OUT selected by register with 12 mA sink capability, 5V tolerance.
- OD or OUT selected by register with 16 mA sink capability, 5V tolerance.
- Output pin with 12 mA source-sink capability.
- Output pin with 16 mA source-sink capability.
- Output pin with 18 mA source-sink capability.
- Output pin with 20 mA source-sink capability.
- Output pin with 30 mA source-sink capability.
- Output pin with 12 mA source-sink capability, 5V tolerance.
- Output pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 14 mA sink capability, 5V tolerance.
- Open-drain output pin with 12 mA sink capability, 5V tolerance.
- Open-drain output pin with 24 mA sink capability, 5V tolerance.
- Open-drain output pin with 12 mA sink capability, pull-up 10k ohms, 5V
tolerance.
- Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V
tolerance.
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger. With internal pull-up 47k resistor.
- TTL level input pin and schmitt trigger
- TTL low level input pin (VIH Æ 0.9V, VIL Æ 0.6V.)
- TTL level input pin and schmitt trigger, 5V tolerance.
- Input pin(Analog).
- Output pin(Analog).
- Power.
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4.1
F71869A
Power Pins
Pin No.
4,37
Pin Name
3VCC
Type
P
45
5VSB(5VA)
P
68
I_VSB3V
P
86
88
99
20, 48, 73, 117
VBAT
AGND(D-)
3VSB
GND
P
P
P
P
4.2
LPC Interface
Pin No.
29
30
31
Pin Name
LRESET#
LDRQ#
SERIRQ
Type
INst,5v
O16
I/O16t-u47k
PWR
3VCC
3VCC
3VCC
32
LFRAM#
INst-u47k
3VCC
33-36
LAD[0:3]
I/O16t-u47k
3VCC
38
PCICLK
INst
3VCC
39
CLKIN
INst
3VCC
4.3
Pin No.
7
8
9
Description
Power supply voltage input with 3.3V (Support OVP)
5V stand by power input. Nomally the 5V stand by
power source is from ATX Power directly.
3.3V internal standby power regulates from 5VSB,
couple this pin with capacitor (0.1u) to ground for inter
capacitance compensation. Besides, this pin can be an
output pin to provide little current for Battery
application when system enters ERP (G3’ like) state.
(Detail pleaser refer application circuit)
Battery voltage input
Analog GND
Analog Stand-by power supply voltage input 3.3V
Digital GND
Description
Reset signal. It can connect to PCIRST# signal on the host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a broken
cycle.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a
peripheral.
33MHz PCI clock input.
System clock input. According to the input frequency
24/48MHz.
FDC
Pin Name
GPIO30
Type
I/OD14st,5v
DENSEL#
OD14,5v
GPIO31
I/OD14st,5v
MOA#
OD14,5v
GPIO32
I/OD14st,5v
DRVA#
OD14,5v
PWR
3VCC
3VCC
3VCC
Description
Default General Purpose IO.
Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
FDC function is selected by register setting.
Default General Purpose IO.
Motor A On. When set to 0, this pin enables disk drive 0.
This is an open drain output.
FDC function is selected by register setting.
Default General Purpose IO.
Drive Select A. When set to 0, this pin enables disk drive A.
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This is an open drain output.
FDC function is selected by register setting.
GPIO33
10
11
I/OD14st,5v
WDATA#
OD14,5v
GPIO34
I/OD14st,5v
DIR#
OD14,5v
GPIO35
I/OD14st,5v
STEP#
OD14,5v
GPIO36
I/OD14st,5v
3VCC
Default General Purpose IO.
3VCC
Write data. This logic low open drain writes pre-compensation
serial data to the selected FDD. An open drain output.
FDC function is selected by register setting.
Default General Purpose IO.
3VCC
Direction of the head step motor. An open drain output. Logic
1 = outward motion
Logic 0 = inward motion
FDC function is selected by register setting.
Default General Purpose IO. (Suppot scan / make code
setting).
Step output pulses. This active low open drain output produces
a pulse to move the head to another track.
FDC function is selected by register setting.
3VCC
Default General Purpose IO. (Suppot scan code setting).
3VCC
Head select. This open drain output determines which disk
drive head is active.
Logic 1 = side 0
Logic 0 = side 1
FDC function is selected by register setting.
Default General Purpose IO. (Suppot scan code setting).
12
13
14
HDSEL#
OD14,5v
GPIO37
I/OD14st,5v
WGATE#
OD14,5v
GPIO50
I/OOD12st,5v
RDATA#
INst,5v
GPIO51
I/OOD12st,5v
TRK0#
INst,5v
GPIO52
I/OOD12st,5v
INDEX#
INst,5v
GPIO53
I/OOD12st,5v
WPT#
INst,5v
GPIO54
I/OOD12st,5v
3VCC
15
3VCC
16
3VCC
17
3VCC
18
19
3VCC
Write enable. An open drain output.
FDC function is selected by register setting.
Default General Purpose IO. Support volume up control from
LPC (Suppot scan code setting).
The read data input signal from the FDD.
FDC function is selected by register setting.
Default General Purpose IO. Support volume down control
from LPC (Suppot scan code setting).
Track 0. This Schmitt-triggered input from the disk drive is
active low when the head is positioned over the outermost
track.
FDC function is selected by register setting.
Default General Purpose IO. Support mute control from LPC
(Suppot scan code setting).
This Schmitt-triggered input from the disk drive is active low
when the head is positioned over the beginning of a track
marked by an index hole.
FDC function is selected by register setting.
Default General Purpose IO. Support PWM up for FANCTL3
(Suppot scan code setting).
Write protected. This active low Schmitt input from the disk
drive indicates that the diskette is write-protected.
FDC function is selected by register setting.
Default General Purpose IO. Support PWM down for
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DSKCHG#
4.4
Pin No.
INst,5v
UART and SIR
Pin Name
Type
GPIO42
I/OOD12t,5v
IRTX
O12
GPIO43
I/OOD12t,5v
IRRX
INst,5v
118
DCD1#
INst,5v
119
RI1#
INst,5v
120
CTS1#
INst,5v
DTR1#
O8t5v,u47k
FAN40_100
INt,5v
RTS1#
O8t5v-u47k
STRAP_PROT
ECT
INt,5v
DSR1#
INst,5v
SOUT1
O8t5v,u47k
STRAP4E_2E
INt,5v
27
28
121
122
123
124
125
126
FANCTL3 (Suppot scan code setting).
Diskette change. This signal is active low at power on and
whenever the diskette is removed.
FDC function is selected by register setting.
SIN1
INst,5v
DCD2#
INst,5v
PWR
Description
Default General Purpose IO.
3VCC
Infrared Transmitter Output. The function is selected by
register setting.
Default General Purpose IO.
3VCC Infrared Receiver input. The function is selected by register
setting.
Data Carrier Detect. An active low signal indicates the
3VCC
modem or data set has detected a data carrier.
Ring Indicator. An active low signal indicates that a ring
I_VSB3V
signal is being received from the modem or data set.
3VCC Clear To Send is the modem control input.
UART 1 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to
communicate. Internal 47k ohms pulled high and disable
after power on strapping.
3VCC Power on strapping pin:
1(Default): (Internal pull high)
Power on fan speed default duty is 40%.(PWM)
0: (External pull down)
Power on fan speed default duty is 100%.(PWM)
UART 1 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
3VCC Power on Strapping pin for over voltage protection function.
1: Default is alarm mode (disabled). Voltage protection
function is enabled via setting the related register.
0: Force mode which is always enabled after power on.
Data Set Ready. An active low signal indicates the modem
3VCC or data set is ready to establish a communication link and
transfer data to the UART.
UART 1 Serial Output. Used to transmit serial data out to
the communication link. Internal 47k ohms pulled high and
disable after power on strapping.
3VCC
Power on strapping:
1(Default): Configuration register 4E
3VCC
3VCC
0: Configuration register 2E
Serial Input. Used to receive serial data through the
communication link.
Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier.
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The function is selected by register setting.
O18
GPIO20
I/OOD8st,5v
RI2#
INst,5v
SEGF
O18
GPIO21
I/OOD8st,5v
CTS2#
INst,5v
SEGA
O18
GPIO22
I/OOD8st,5v
Clear To Send is the modem control input.
The function is selected by register setting.
SEGA for 7-segment display. (Select by pin 5 power on
strapping)
Default General Purpose IO.
GPIO23
I/OOD8st,5v
Default General Purpose IO.
DTR2#
O8t5v,u47k
SEGD
O18
GPIO24
I/OOD8st,5v
RTS2#
O8t5v,u47k
SEGC
O18
GPIO25
I/OOD8st,5v
127
128
1
2
3
DSR2#
INst,5v
L#
O30
GPIO26
I/OOD8st,5v
SOUT2
O8t,5v,u47k
Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set.
The function is selected by register setting.
I_VSB3V
SEGF for 7-segment display. (Select by pin 5 power on
strapping)
Default General Purpose IO.
3VCC
3VCC
3VCC
SEGB
O18
STRAP_DPORT
INt,5v
GPIO27
I/OOD8st,5v
SIN2
INst,5v
UART 2 Data Terminal Ready. An active low signal informs
the modem or data set that controller is ready to
communicate. The function is selected by register setting.
SEGD for 7-segment display. (Select by pin 5 power on
strapping)
Default General Purpose IO.
UART 2 Request To Send. An active low signal informs the
modem or data set that the controller is ready to send data.
The function is selected by register setting.
SEGC for 7-segment display. (Select by pin 5 power on
strapping)
Default General Purpose IO.
3VCC
3VCC
5
6
SEGG for 7-segment display. (Select by pin 5 power on
strapping)
Default General Purpose IO.
SEGG
3VCC
Data Set Ready. An active low signal indicates the modem
or data set is ready to establish a communication link and
transfer data to the UART. The function is selected by
register setting.
L# for 7-segment display. (Select by pin 5 power on
strapping)
Default General Purpose IO.
UART 2 Serial Output. Used to transmit serial data out to
the communication link. The function is selected by register
setting.
SEGB for 7-segment display. (Select by pin 5 power on
strapping)
Strap for 80 Port. Default internal Pull High for 80 Port
Enable.
Default General Purpose IO.
Serial Input. Used to receive serial data through the
communication link. The function is selected by register
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F71869A
setting.
SEGE
4.5
Pin No.
100
101
102
103
104
105
106
Parallel Port
Pin Name
Type
SLCT
INst,5v
GPIO60
I/OOD12t,5v
PE
INst,5v
GPIO61
I/OOD12t,5v
BUSY
INst,5v
GPIO62
I/OOD12t,5v
ACK#
INst,5v
GPIO63
I/OOD12t,5v
SLIN#
I/OOD12st,5v
INIT#
I/OOD12st,5v
GPIO64
I/OOD12t,5v
PWR
3VCC
Description
An active high input on this pin indicates that the printer is
selected. Refer to the description of the parallel port for
definition of this pin in ECP and EPP mode.
Default General Purpose IO.
3VCC
An active high input on this pin indicates that the printer has
detected the end of the paper. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP
mode.
Default General Purpose IO.
3VCC
An active high input indicates that the printer is not ready to
receive data. Refer to the description of the parallel port for
definition of this pin in ECP and EPP mode.
Default General Purpose IO.
3VCC
An active low input on this pin indicates that the printer has
received data and is ready to accept more data. Refer to the
description of the parallel port for the definition of this pin in
ECP and EPP mode.
Default General Purpose IO.
3VCC
3VCC
Output line for detection of printer selection. Refer to the
description of the parallel port for the definition of this pin in
ECP and EPP mode.
Output line for the printer initialization. Refer to the
description of the parallel port for the definition of this pin in
ECP and EPP mode.
Default General Purpose IO.
An active low input on this pin indicates that the printer has
encountered an error condition. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP
mode.
ERR#
INst,5v
GPIO65
I/OOD12t,5v
Default General Purpose IO.
I/OOD12st,5v
An active low output from this pin causes the printer to auto
feed a line after a line is printed. Refer to the description of
the parallel port for the definition of this pin in ECP and EPP
mode.
AFD#
107
GPIO66
108
SEGE for 7-segment display. (Select by pin 5 power on
strapping)
O18
STB#
3VCC
3VCC
Default General Purpose IO.
I/OOD12t,5v
I/OOD12st,5v
3VCC
An active low output is used to latch the parallel data into the
printer. Refer to the description of the parallel port for the
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V0.19P
F71869A
definition of this pin in ECP and EPP mode.
GPIO67
I/OOD12t,5v
Default General Purpose IO.
PD0
I/O12st,5v
Parallel port data bus bit 0. Refer to the description of the
parallel port for the definition of this pin in ECP and EPP
mode.
GPIO70
I/OOD12t,5v
110
PD1
GPIO71
111
PD2
GPIO72
112
PD3
GPIO73
113
PD4
GPIO74
114
PD5
GPIO75
115
PD6
GPIO76
116
PD7
GPIO77
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
I/OOD12t,5v
I/O12st,5v
I/OOD12t,5v
109
4.6
3VCC
Default General Purpose IO.
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
3VCC
Parallel port data bus bit 1.
Default General Purpose IO.
Parallel port data bus bit 2.
Default General Purpose IO.
Parallel port data bus bit 3.
Default General Purpose IO.
Parallel port data bus bit 4.
Default General Purpose IO.
Parallel port data bus bit 5.
Default General Purpose IO.
Parallel port data bus bit 6.
Default General Purpose IO.
Parallel port data bus bit 7.
Default General Purpose IO.
Hardware Monitor
Pin No.
Pin Name
Type
93
VIN6
AIN
94
VIN5
AIN
PWR
I_VSB3V
I_VSB3V
I_VSB3V
95
VIN4 (VDIMM)
AIN
96
VIN3 (VDDA)
AIN
97
VIN2 (VLDT)
AIN
98
VIN1 (Vcore)
AIN
21
FANIN1
INs t , 5 v
3VCC
22
FANCTL1
OOD12,5v
AOUT
3VCC
23
FANIN2
INs t , 5 v
3VCC
I_VSB3V
I_VSB3V
I_VSB3V
Description
Voltage input 6. This pin support OVP function, and default
is disable.
Voltage input 5. This pin support OVP function, and default
is disable.
Voltage input 4 or VDIMM input used in AMD platform. The
input voltage level for timing control usage must be over 1V
after voltage divider.
Voltage input 3 or VDDA input used in AMD platform. The
input voltage level for timing control usage must be over 1V
after voltage divider.
Voltage input 2 or VLDT input used in AMD platform. The
input voltage level for timing control usage must be over 1V
after voltage divider.
Voltage Input for Vcore. The input voltage level for timing
control usage must be over 0.7V.
Fan 1 tachometer input.
Fan 1 control output. It is also a trap pin to select a PWM or
a DAC output, except being an output pin. It defaults to be
a voltage output by pulling down 100k internally. It is set as
a PWM output as connected a 4.7K resistor and pulled
high to 3.3V.
Fan 2 tachometer input.
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24
25
FANCTL2
OOD12,5v
AOUT
GPIO40
I/OOD12st,5v
FANIN3
INs t , 5 v
GPIO41
I/OOD12st,5v
3VCC
3VCC
3VCC
26
57
FANCTL3
OOD12,5v
AOUT
CIR_LED#
OD12,5v
SCL
ILv/OD12st,5v
PECI
ILv/OD8,S1
I_VSB3V
I_VSB3V
58
63
67
SDA
ILv/OD12st,5v
WDTRST#
OD12,5v
GPIO14
I/OOD12st,5v
OVT#
OD12,5v
I_VSB3V
I_VSB3V
79
PME#
OD12,5v
I_VSB3V
89
D3+
AIN
I_VSB3V
90
D2+
AIN
I_VSB3V
91
D1+(CPU)
AIN
I_VSB3V
92
VREF
AOUT
I_VSB3V
4.7
Fan 2 control output. It is also a trap pin to select a PWM or
a DAC output, except being an output pin. It defaults to be
a voltage output by pulling down 100k internally. It is set as
a PWM output as connected a 4.7K resistor and pulled
high to 3.3V.
Default General Purpose IO.
Fan 3 speed input. This function is selected by register
setting.
Default General Purpose IO. This pin default function is
GPIO function. Please take care of the application if user
wants to implement FANCTL function.
Fan 3 control output. It is also a trap pin to select a PWM or
a DAC output, except being an output pin. It defaults to be
a voltage output by pulling down 100k internally. It is set as
a PWM output as connected a 4.7K resistor and pulled
high to 3.3V. The PWM output frequency can be
programmed to 220Hz for LCD backlight control.
LED for CIR to indicate receiver is receiving data.
SMBUS Interface CLOCK pin. Clock output for AMD TSI &
Intel PCH (IBX Peak).
Intel PECI hardware monitor interface. When
TIMING_GPIO pin is set in GPIO function (INTEL mode).
PECI function can be set by the register.
SMBUS Interface DATA pin. AMD TSI & Intel PCH (IBX
Peak) data pin.
Watch dog timer signal output.
General Purpose IO. GPIO function is selected by register
setting
Over temperature signal output.
Generated PME event. It supports the PCI PME# interface.
This signal allows the peripheral to request the system to
wake up from the S3 state.
Thermal diode/transistor temperature sensor input for
system use.
Thermal diode/transistor temperature sensor input.
CPU thermal diode/transistor temperature sensor input.
This pin is for CPU use.
Voltage sensor output.
ACPI Function Pins
Pin No.
Pin Name
Type
PWR
59
GPIO10
I/OOD12st,5v
I_VSB3V
PCI_RST4#
O12,5v
Description
Default General Purpose IO. GPIO function is selected by
register setting
It is an output buffer of LRESET#. This function is selected
by register setting.
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SMBUS Interface CLOCK pin. Clock output for AMD TSI &
Intel PCH (IBX Peak).
Default General Purpose IO.
It is an output buffer of LRESET#. This function is selected
by register setting.
SMBUS Interface DATA pin. AMD TSI & Intel PCH (IBX
Peak) data pin.
Default General Purpose IO.
SCL
ILv /OD12st,5v
GPIO11
I/OOD12st,5v
PCI_RST5#
O12,5v
SDA
ILv /OD12st,5v
GPIO12
I/OOD12st,5v
RSTCON#
INs t , 5 v
GPIO15
I/OOD12st,5v
LED_VSB
OD12,5v
ALERT#
OD12,5v
GPIO16
I/OOD12st,5v
LED_VCC
OD12,5v
CPU_PWGD
OD12,5v
GPIO17
I/OOD12st,5v
74
PCIRST1#
OD12,5v
75
PCIRST2#
O12,5v
I_VSB3V
It is an output buffer of LRESET#.
76
PCIRST3#
O12,5v
I_VSB3V
It is an output buffer of LRESET#.
77
S5#
INst,5v
I_VSB3V
S5# signal input.
ATXPG_IN
INst,5v
60
61
64
65
66
78
80
GPIO44
I/OOD12st,5v
PSIN#
INts,5v
GPIO45
I/OOD12st,5v
PSOUT#
OD12,5v
I_VSB3V
I_VSB3V
GPIO46
I/OOD12st,5v
S3#
INst,5v
PS_ON#
OD12,5v
Default General Purpose IO.
Power LED for VSB. This function is selected by register
setting.
Alert a signal when temperature over limit setting. This
function is selected by register setting.
Default General Purpose IO.
Power LED for VCC. This function is selected by register
setting.
CPU Power Good signal output
(Detected by VIN1~VIN4 level good)
I_VSB3V
General Purpose IO. GPIO function is selected by register
setting
I_VSB3V It is an output buffer of LRESET#.
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
83
Reset button input. This function is selected by register
setting.
I_VSB3V
I_VSB3V
81
82
I_VSB3V
GPIO47
I/OOD12st,5v
84
PWOK
OD12,5v
VBAT
85
RSMRST#
OD12,5v,u10k
VBAT
ATX Power Good input.
General Purpose IO. GPIO function is selected
setting.
Main power switch button input.
General Purpose IO. GPIO function is selected
setting.
Panel Switch Output. This pin is low active
output. It is power on request output#.
General Purpose IO. GPIO function is selected
setting.
by register
by register
and pulse
by register
S3# Input is Main power on-off switch input.
Power supply on-off control output. Connect to ATX power
supply PS_ON# signal.
General Purpose IO. GPIO function is selected by register
setting.
PWOK function, It is power good signal of VCC, which is
delayed 400ms (default) as VCC arrives at 2.8V.
Resume Reset# function, It is power good signal of VSB,
which rises delayed 66ms as VSB arrives at 2.8V and falls
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87
COPEN#
4.8
INst,5v
VBAT
Power Saving and Others
Pin No.
Pin Name
Type
PWR
42
EVENT_IN0#
INt s , 5 v
I_VSB3V
43
ERP_CTRL0#
OD12
I_VSB3V
44
ERP_CTRL1#
OD12
I_VSB3V
DPWROK
OD12,5v
I_VSB3V
46
TIMING_3
OD12,5v
SLP_SUS#
INst,lv
I_VSB3V
47
49
50
51
52
as VSB drops to 2.6V. There is an option to set RSMRST#
rises at 3.05V and falls at 2.95V.
Case Open Detection #. This pin is connected to a
specially designed low power CMOS flip-flop backed by
the battery for case open state preservation during power
loss.
TIMING_4
OD12,5v
CIRWB#
INst,5v
GPIO01
I/OOD12t
CIRTX#
O20
GPIO02
I/OOD12t
CIRRX#
INs t . 5 v
GPIO03
I/OOD12t
STRAP_TIMING
INst,5v
SUS_ACK#
OOD16,5v
I_VSB3V
I_VSB3V
I_VSB3V
I_VSB3V
TIMING_2
OD12,5v
Strap Pin for AMD and Intel Cougar Point timing. Internal
pull high with AMD timing (Default).
This pin must wait SUS_WARN# signal for entering DSW
power state.
I_VSB3V
53
Description
Wake-up event input. The signal input wakes the system
up from the sleep state.
Standby power rail control pin 0. This pin controls an
external PMOS to turn on or off the standby power rail. In
the S5 state, the default is set to 1 to cut off the standby
power rail.
Standby power rail control pin 1. This pin controls an
external PMOS to turn on or off the standby power rail. In
the S5 state, the default is set to 1 to cut off the standby
power rail.
Resume Reset# function, It is power good signal of VSB,
which is delayed 66ms as VSB arrives at 4.4V. Couple this
pin to PCH when system supports Intel DSW state
function.
Active high. Timing sequence 3 of power on/off sequence
pins. The external pull high resistor is required.
(Detected by VIN3 level good)
For Intel CPT DSW function. Connect to PCH SLP_SUS
pin.
Active high. Timing sequence 4 of power on/off sequence
pins. The external pull high resistor is required.
(Detected by VIN1 level good)
CIR wide-band receiver input. (For Learning use)
General Purpose IO. GPIO function is selected by register
setting
CIR Transmitter to transmit data.
General Purpose IO. GPIO function is selected by register
setting
CIR long-range receiver input
General Purpose IO. GPIO function is selected by register
setting
Active high. Timing sequence 2 of power on/off sequence
pins. The external pull high resistor is required.
(Detected by VIN4 level good)
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F71869A
SUS_WARN#
INst,5v
I_VSB3V
54
TIMING_1
OD12,5v
S3P5_Gate#
OD12
I_VSB3V
55
SLOTOCC#
INst,5v
GPIO04
OD12,5v
S3_Gate#
OD12
56
I_VSB3V
GPIO05
I/OOD12st,5v
WDTRST#
OD12,5v
S0P5_Gate#
OD24,5v
62
I_VSB3V
4.9
GPIO13
I/OOD24st,5v
BEEP
OD24,5v
This pin asserts low when the PCH is planning to enter the
DSW power state. It can detect 5VDUAL level with delay
setting supported.
Active high. Timing sequence 1 of power on/off sequence
pins. The external pull high resistor is required.
(Output detected by VCCOK(VDDOK) level good, ref
Figure 15 )
Status Pin2 for S0#/S3#/S5# states application. (Default
function)
In S0# Æ S3P5_Gate# pin status is Tri-state.
In S3# ( S3P5_Gate # pin status is Low level.
In S5# ( S3P5_Gate # pin status is Tri-state, and can be
programmed Low level.
CPU SLOTOCC# input.
General Purpose IO. GPIO function is selected by register
setting
Status Pin1 for S0#/S3#/S5# states application. (Default
function)
In S0# ( S3_Gate# pin status is Tri-state.
In S3# ( S3_Gate# pin status is Low level.
In S5# ( S3_Gate# pin status is Tri-state.
General Purpose IO. GPIO function is selected by register
setting
Watch dog timer signal output.
S0P5_Gate# for S0#/S3#/S5# states application.
In S0# (S0P5_Gate# pin status is Low-state.
In S3# (S0P5_Gate# pin status is Tri-state.
In S5# Æ S0P5_Gate# pin status is Tri-state, and can be
programmed Low-state.
General Purpose IO. GPIO function is selected by register
setting
Beep pin.
KBC Function
Pin No.
Pin Name
Type
PWR
Description
Keyboard reset. This pin is high after system reset. Internal
pull high 3.3V with 10k ohms. (KBC P20)
Gate A20 output. This pin is high after system reset. Internal
pull high 3.3V with 10k ohms. (KBC P21)
40
KBRST#
OD16,5v,u10k
3VCC
41
GA20
OD16,5v,u10k
3VCC
69
KDATA
I/OD16st,5V
I_VSB3V
Keyboard Data.
70
KCLK
I/OD16st,5V
I_VSB3V
Keyboard Clock.
71
MDATA
I/OD16st,5V
I_VSB3V
PS2 Mouse Data.
72
MCLK
I/OD16st,5V
I_VSB3V
PS2 Mouse Clock.
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5. Function Description
5.1
Power on Strapping Option
The F71869A provides eight pins for power on hardware strapping to select functions. There is
a form to describe how to set the functions you want.
Pin No.
52
121
124
22
24
26
5
122
5.2
Table1. Power on trap configuration
Symbol
Value
Description
1
AMD Timing (Default)
STRAP_TIMING
0
Intel Cougar Point Timing
Power on Fan speed default duty is 40% (PWM)
1
FAN40_100
(Default)
0
Power on Fan speed default duty is 100%(PWM)
1
Configuration Register I/O port is 4E/4F. (Default)
STRAP4E_2E
0
Configuration Register I/O port is 2E/2F.
FANCTRL1 is PWM mode. Connect a 4.7K
1
FANCTL1
resistor and pull high to 3.3V.
0
FANCTLR1 is DAC mode. (Default)
FANCTRL2 is PWM mode. Connect a 4.7K
1
resistor and pull high to 3.3V.
FANCTL2
0
FANCTLR2 is DAC mode. (Default)
FANCTRL3 is PWM mode. Connect a 4.7K
1
resistor and pull high to 3.3V.
FANCTL3
0
FANCTLR3 is DAC mode. (Default)
1
Enable 80 Port (Default)
STRAP_DPORT
0
Disable 80 Port
Default is alarm mode (disabled). Voltage
1
protection function is enabled via setting the
STRAP_PROTECT
related register.
Force mode which is always enabled after power
0
on.
Hardware Monitor
For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is 2.048V.
Therefore the voltage under 2.048V (ex: 1.5V) can be directly connected to these analog
inputs. The voltage higher than 2.048V should be reduced by a factor with external resistors
so as to obtain the input range. Only 3VCC/VSB/VBAT is an exception for it is main power of
the F71869A. Therefore 3VCC/VSB/VBAT can directly connect to this chip’s power pin and
need no external resistors. There are two functions in this pin with 3.3V. The first function is
to supply internal analog power of the F71869A and the second function is that voltage with
3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The internal serial
resistors are two 150K ohm, so that the internal reduced voltage is half of +3.3V.
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There are four voltage inputs in the F71869A and the voltage divided formula is shown as
follows:
VIN = V+12 V ×
R2
R1 + R 2
where V+12V is the analog input voltage, for example.
If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which is
within the tolerance. As for application circuit, it can be refer to the figure shown as follows.
Voltage Inputs
150K
(directly connect to the chip)
3VCC/VSB
VIN (Lower than 2.048V)
VIN3.3
(directly connect to the chip)
150K
VIN1(Max2.048V)
VIN(Higher than 2.048V)
R1
R2
8-bit ADC
with
8 mV LSB
VREF
R
10K, 1%
D+
Typical BJT
Connection
D-
Typical Thermister
Connection
RTHM
10K, 25 C
2N3906
Figure 2. Hardware monitor configuration
The F71869A monitors three remote temperature sensors. These sensors can be measured
from -40°C to 127°C. More detail please refer register description.
Table 2. Remote-sensor transistor manufacturers
5.2.1.
Manufacturer
Model Number
Panasonic
2SB0709 2N3906
Philips
PMBT3906
Table Range:
Table 3. Display range is from -40°C to 127°C in 2’s complement format.
Temperature
Digital Output
-40°C
1101 1000
-1°C
1111 1111
1°C
0000 0001
90°C
0101 1010
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5.2.2.
127°C
1111 1111
Open
1000 0000
Monitor Temperature from “Thermistor”
The F71869A can connect three thermistors to measure environment temperature or
remote temperature. The specification of thermistor should be considered to (1) ß value is
3435K (2) resistor value is 10K ohm at 25ºC. In the Figure 2, the thermistor is connected by
a serial resistor with 10K ohm, then being connected to VREF.
5.2.3.
Monitor Temperature from “Thermal diode”
Also, if the CPU, GPU or external circuits provide thermal diode for temperature
measurement, the F71869A is capable to these situations. The build-in reference table is for
PNP 2N3906 transistor. In the Figure 2, the transistor is directly connected into temperature
pins.
5.2.4.
ADC Noise Filtering
The ADC is integrating type with inherently good noise rejection. Micro-power operation
places constraints on high-frequency noise rejection; therefore, careful PCB board layout
and suitable external filtering are required for high-accuracy remote measurement in
electronically noisy environment. High frequency EMI is best filtered at D+ and D- with an
external 2200pF capacitor. Too high capacitance may introduce errors due to the rise time of
the switched current source. Nearly all noise sources tested cause the ADC measurement
to be higher than the actual temperature, depending on the frequency and amplitude.
5.2.5.
Monitor Temperature from “SMBus device”
F71869A provides SMBus block read/write compatible Platform Control Hub (PCH) EC
SMBus protocol, and provides byte read/write protocol to read CPU and chipset thermal
temperature information.
For byte read /write protocol, F71869A supports 4-suit device
address to read or write from device information. For block read/write, F71869A support 1
suits device address and maximum 17 byte count for read protocol to read from device
information, and 4 byte count for write protocol to write information to device.
5.2.6.
Monitor Temperature from “PECI”
F71869A support Intel PECI1.1/PECI3.0/PECI_Request/PECI_Available interfaces to
read temperature from PECI device.
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5.2.7.
Temperature OVT# Signal
There is a mode of temperature (t1 to t4) OVT function, and refer t1 to t4 temperature in
the below Figure.
Over temperature event will trigger OVT# that shown as figure 3. In hysteresis mode,
when monitored temperature exceeds the high temperature threshold value, OVT# will be
asserted until the temperature goes below the hysteresis temperature.
T
OVT
THYST
OVT#
t1
t2
t3
t4
Figure 3
5.2.8. Temperature PME#
PME# interrupt for temperature is shown as figure 4. Temperature exceeding high limit
(low limit) or going below high hysteresis (low hysteresis) will cause an interrupt if the
previous interrupt has been reset by writing “1” all the interrupt Status Register.
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F71869A
T OVT
T Hhys
T HIGH
T Hhys
PME#
(pulse mode)
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are written 1
Figure 4 Hysteresis mode illustration
5.2.9. Fan Speed Count
Inputs are provided by the signals from fans equipped with tachometer outputs. The level of
these signals should be set to TTL level, and maximum input voltage cannot be over 5V. If the
input signals from the tachometer outputs are over the 5V, the external trimming circuit should
be added to reduce the voltage to obtain the input specification.
Determine the fan counter according to:
Count =
1.5 × 10 6
RPM
In other words, the fan speed counter has been read from register, the fan speed can be
evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer
output per round.
RPM =
1.5 × 10 6
Count
As the register description of datasheet, the parameter “Count” register provides 12-bit
resolution for RPM counting. In Fintek design, the value of parameter “Count” is from 4096 ~
64 (5 bit filter). Therefore the RPM measure capability is from 366 ~ 23438 rpm.
Above example is for 2 pulses tachometer (Normal 4 Phases fan) output per round. If you
use 8 Phases fan, means output 4 pulses per round. The RPM measure capability is from 183
~ 11719 rpm.
5.2.10. Fan Speed Control
The F71869A provides 2 fan speed control methods: one is DAC FAN control and the other
is PWM duty cycle.
1.
DAC Fan Control
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The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V. The
output DC voltage is amplified by external OP circuit, thus to reach maximum FAN
OPERATION VOLTAGE, 12V. The output voltage will be given as followed:
Output_vol tage (V) = 3.3 ×
Programmed 8bit Register Value
255
And the suggested application circuit for DAC fan control would be:
+12V
8
R
4.7K
3
2
+
PMOS
Q1
D1
1N4148
1
-
R
4.7K
LM358
4
DC OUTPUT VOLTAGE
U1A
JP1
R
10K
R
3
2
1
C
47u
C
0.1u
CON3
R
3.6K
27K
FANIN MONITOR
R
10K
Figure 5 DAC fan control application circuit
2.
PWM duty Fan Control
The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is
set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be
represented as follows.
Duty_cycle(%) =
Programmed 8bit Register Value
× 100%
255
+12V
R1
R2
G
PNP Transistor
D
NMOS
S
+
-
C
FAN
Figure 6 +12/5V PWM fan control application circuit
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5.2.11. Fan Speed Control Mechanism
There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto
mode 3. Linear auto mode. More detail, please refer the description of registers.
Each fan can be controlled by up to 8 kinds of temperature inputs: (1) D1+ temperature (2)
D2+ temperature (3) D3+ temperature (4) PECI temperature (5) 4 suits SMBus master
temperature. Each fan would make the maximum temperature comparison form those
inputs with the expected speed, and decide the suitable fan speed. Please refer below
figure 7.
PECI
(T0)
D1+ T
(T1)
D2+ T
(T2)
D3+ T
(T3)
IBX
Byte1
IBX
Byte3:2
Expected
speed1
Fan1
Expected
speed 2
Fan2
Expeted
speed 3
Fan3
IBX
Byte4
IBX
Byte5
Figure 7 Relative temperature fan control
Manual mode
For manual mode, it generally acts as software fan speed control.
Auto mode
In auto mode, the F71869A provides automatic fan speed control related to temperature
variation of CPU/GPU or the system. The F71869A can provide four temperature boundaries and five
intervals, and each interval has its related fan speed count. All these values should be set by BIOS
first. Take FAN1 for example, the 4 temperature boundaries could be set from register 0xA6 to 0xA9
and the five intervals for fan speed control could be set from register 0xAA to 0xAE. And the
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hysteresis setting (0 ~ 15°C) could also be found in register 0x98.
The Manual Mode and Auto Mode could be selected by register 0x96h.
There are two kinds of auto mode: stage auto mode and linear auto mode. The “FAN1_
INTERPOLATION_EN” in register 0xAFh is used for linear auto mode enable. The following
examples explain the differences for stage auto mode and linear auto mode.
Stage auto mode
In this mode, the fan keeps in a same speed for each temperature interval. And there are two
types of fan speed setting: PWM Duty and RPM %.
A. Stage auto mode (PWM Duty)
Set the temperature limits as 70°C, 60°C, 50°C, 40°C and the duty as 100%, 90%, 80%, 70%, 60%
Figure 8 Stage mode fan control illustration-2
a. Once the temperature is under 40°C, the lowest fan speed keeps in the 60% PWM duty.
b. Once the temperature is over 40°C, 50°Cand 60°C, the fan speed will vary from 70%, 80% to 90%
PWM duty and increasing with the temperature level.
c. For the temperature higher than 70°C, the fan speed keeps in 100% PWM duty.
d. If set the hysteresis is 3°C (default 4°C), once the temperature becomes lower than 67°C, the fan
speed would reduce to 90% PWM duty.
B. Stage auto mode (RPM%)
Set the temperature as 70°C, 60°C, 50°C, 40°C and the corresponding fan speed is 6,000 rpm,
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5,400 rpm, 4,800 rpm, 4,200 rpm, and 3,600 rpm (assume the Max Fan Speed is 6,000 rpm).
Figure 9 Stage mode fan control illustration-3
a. Once the temperature is lower than 40°C, the lowest fan speed keeps in 3,600 rpm (60% of full
speed).
b. Once the temperature is higher than 40°C, 50°C and 60°C, the fan speed will vary from 4,200 rpm
to 5,400 rpm and increasing with the temperature level.
c. For the temperature higher than 70°C, the fan speed keeps in the full speed 6,000 rpm.
d. If the hysteresis is set as 3°C (default 4°C), once temperature gets lower than 67°C, the fan speed
would reduce to 5,400 rpm.
Linear auto mode
F71869A also supports linear auto mode. The fan speed would increase or decrease linearly with
the temperature. There are also PWM Duty and RPM% modes for it.
A. Linear auto mode (PWM Duty)
Set the temperature as 70°C, 60°C, 50°C and 40°C and the duty is 100%, 80%, 70%, 60% and
50%.
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Figure 10 Linear mode fan control illustration-1
a. Once the temperature is lower than 40°C, the lowest fan speed keeps in the 50% PWM duty
b. Once the temperature becomes higher than 40°C, 50°C and 60°C, the fan speed will vary from
50% to 80% PWM duty linearly with the tempreature variation. The temp.-fan speed monitoring
flash interval is 1sec.
c.
Once the temperature goes over 70°C, the fan speed will directly increase to 100% PWM duty
(full speed).
d. If set the hysteresis is 5°C (default is 4°C), once the temperature becomes lower than 65°C
(instead of 70°C), the fan speed will reduce from 100% PWM duty and decrease linearly with the
temperature.
B. Linear auto mode (RPM%)
Set the temperature as 70°C, 60°C, 50°C, 40°C and the corresponding fan speed is 6,000 rpm,
4,800 rpm, 4,200 rpm, 3,600 rpm and 3,000 rpm (assume the Max Fan Speed is 6,000 rpm).
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Figure 11 Linear mode fan control illustration-2
a. Once the temperature is lower than 40°C, the lowest fan speed keeps in 3,000 rpm (50% of full
speed).
b. Once the temperature is over 40°C,50°C and 60°C, the fan speed will vary from 3,000 to 4,800
rpm almost linearly with the temperature variation because the temp.-fan speed monitoring flash
interval is 1sec.
c.
Once the temperature goes over 70°C, the fan speed will directly increase to full speed 6,000
rpm.
d. If the hysteresis is 5°C (default is 4°C), once the temperature becomes lower than 65°C (instead
of 70°C), the fan speed wull reduce from full speed and decrease linearly with the temperature.
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Fan Speed Control with Multi-temperature.
F71869A supports Multi-temperature for one fan control. This function works with linear
auto mode can extend two linear slopes for one Fan control. As the graph below, this
machine can support more silence fan control in low temperature environment and faster
fan speed in high temperature segment. More detail setting please refers to the registers.
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In the figure below, TFan1 is the scaled temperature for fan1. T1 is the real temperature
for the fan1 sensor. Ta is another temperature data which can be used for linearly scale up
or scale down the fan1 speed curve. Tb would be the point which starts the temperature
scaling. The slope for the temperature curve over and under Tb would be Ctup and Ctdn.
In application, we can set the Ta as the 2nd sensor temperature and Tb as the
temperature which starts the scaling. So if the 2nd sensor temperature Ta is higher or lower
than Tb, the fan1 speed would be changed with it.
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EX: Ta = T1, Tb = 60, Ctu = 1, Ctd = 1/4
5.2.12. FAN_FAULT#
Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed
within a programmable period (default is 11 seconds) or when fan stops with respect to
PWM duty-cycle which should be able to turn on the fan. There are two conditions may
cause the FAN_FAULT# event.
(1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected
count in time.
11 sec(default)
Current Fan Count
Expected Fan Count
100%
Duty-cycle
Fan_Fault#
Figure 12 FAN_FAULT# event
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(2). After the period of detecting fan full speed, PWM_Duty > Min. Duty, fan count is still in
0xFFF.
5.3
ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the
use of power in a computer. It lets computer manufacturer and user to determine the
computer’s power usage dynamically.
There are three ACPI states that are of primary concern to the system designer and they are
designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this
state. The other two are called sleep states and reflect different power consumption when
power-down. S3 is a state that the processor is powered down but the last procedural state is
being stored in memory which is still active. S5 is a state that memory is off and the last
procedural state of the processor has been stored to the hard disk. Take S3 and S5 as
comparison, since memory is fast, the computer can quickly come back to full-power state, the
disk is slower than the memory and the computer takes longer time to come back to full-power
state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.
It is anticipated that only the following state transitions may happen:
S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.
Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is
necessary to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only
as an immediate state during state transition from S5→S0. It isn’t allowed in the normal state
transition.
The below diagram described the timing, the always on and always off, keep last state could be
set in control register. In keep last state mode, one register will keep the status of before power
loss. If it is power on before power loss, it will remain power on when power is resumed,
otherwise, if it is power off before power loss, it will remain power off when power is resumed.
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VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
Figure 13 Default timing: Always off
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
Figure 14 Optional timing: Always on
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PCI Reset and PWOK Signals
The F71869A supports 5 output buffers for 5 reset signals.
+3.3V
Delay
PWOK
LRESET#
Buffer
PCIRST1~5#
ATXPG
So far as the PWOK issue is as the figure above. PWOK is delayed 400ms (default) as VCC
arrives 2.8V, and the delay timing can be programmed by register. An additional delay could be
added to PWOK (0ms, 100ms, 200ms and 400ms). If RSTCION# and PCIRST4#/PCIRST5# are
enabled, RSTCON# could be programmed to be asserted via PWROK or PCIRST4#/PCIRST5#.
5.4
Power Timing Control Sequence
The F71869A offers 4 timing pins which are designed for AMD platform power sequence
control including VDIMM, VDDA, Vcore, and VLDT (default) or other timing application
purposes. All the timings on/off are relative to S3#/S5# and can be programmed by the register
0x0AF7. As shown in the below figure, the default timings of TIMING_1~4 are displayed in blue
lines, and all the timings are enabled in the S0 state except TIMING_1. However, TIMING_2~4
can be programmed to enable in the S3 state, and TIMING_1 can also be programmed to
disable in the S3 state, like the dotted blue line shown in the figure below.
VDDOK_D400 is the PWOK delay timing from VDD3VOK. The default setting is that delay
400ms, there are 100ms, 200ms, and 300ms for option. It can be set in the register 0x0AF5.
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S5
S0
S3
S0
S3
S5
S5#
S3#
PSON#
ATXPWGD
VDDOK_D400
TIMING_1
TIMING_2
TIMING_3
TIMING_4
CPU_PWGD
Figure 15 Timing on/off sequence
5.5
S3_Gate#, S3P5_Gate# and S0P5_Gate# Timing
The F71869A provides three additional timing switching pins which are named as S3_Gate#,
S3P5_Gate# and S0P5_Gate#. They can be applied in the certain applications about power switch
which depends on the ACPI states. The detail timing can be referred in the following diagrams.
The default timing of S0P5_Gate# in the S5 state is low, but it can be programmed high by the
register 0x0AF6.
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S5
S0
S3
F71869A
S5#
S3#
10us
10us
PSON#
VDD3V
VDDOK
VDDOK_D400
400ms
ATXPG
PWROK
S0P5_Gate#
could be programmed low
S3_Gate#
S3P5_Gate#
could be programmed low
Figure 16 Timing chart of S5->S0->S3
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S3
S0
S5
S5#
S3#
10us
10us
PSON#
VDD3V
VDDOK
VDDOK_D400
400ms
ATXPG
PWROK
S0P5_Gate#
S3_Gate#
S3P5_Gate#
could be programmed low
Figure 17 Timing chart of S3->S0->S5
5.6
AMD TSI and Intel PECI 3.0 Functions
The F71869A provides Intel PECI/AMD TSI interfaces for new generational CPU temperature
sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading
from AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More detail,
please refer register description.
VDDIO
300
AMD
CPU
300
SIC
SCL
SID
SDA
F71869A
Figure 18 AMD TSI typical application
In Intel PECI interface, the F71869A can connect to CPU directly. The F71869A can read the
temperature data from CPU, than the fan control machine of F71869A can implement the Fan to
cool down CPU temperature. The application circuit is as below.
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Intel
F71869A
CPU
PECI
avoid pre-BIOS floating
PECI
100K
Figure 19 INTEL PECI Typical Application
In Intel PECI 3.0 Spec., it’s including below commands. The F71869A integrated most of
those commands for future advantage application. More detail, please refer the register
descriptions.
F71869A
Support
V
V
V
V
V
V
5.7
PECI 3.0 Command
Name
Ping( )
GetTemp( )
GetDIB( )
RdIAMSR( )
WrIAMSR( )
RdPCIConfigLocal( )
WrPCIConfigLocal( )
RdPCIConfig( )
WrPCIConfig( )
RdPkgConfig( )
WrPkgConfig( )
PECI 1.0 Command
Name
Ping( )
GetTemp( )
Status
Not Available in Mobile/DT
Not Available in Mobile/DT
Not Available in Mobile/DT
Not Available in Mobile/DT
ErP Power Saving Function
The two pins, ERP_CTRL0# and ERP_CTRL1#, which control the standby power rail on/off to
fulfill the purpose which decreases the power consumption when the system in the sleep state or
the soft-off state. These two pins connected to the external PMOSs and the defaults are high in the
sleep state in order to cut off all the standby power rails to save the power consumption. If the
system needs to support wake-up function, the two pins can be programmable to set which power
rail is turned on. The programmable register is powered by battery. So, the setting is kept even the
AC power is lost when the register is set. At the power saving state (FINTEK calls it G3-like state),
the F71869A consumes 5VSB power rail only to realize a low power consumption system. Below is
ErP function’s timing graphs.
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5.8
F71869A
CIR Function
The F71869A is compatible with Microsoft Windows Vista and Windows 7 IR Receiver or
Transceiver Emulation Device which supports RC6 & QP protocol. It Supports 1 IR transceiver
functions for blaster application and 1 IR receiver with long range frequency and another with wide
band application. In power function, The F71869A supports Vista and Windows 7 wakeup
programming function when the PC is in the S3 state. The F71869A decode IR protocol via the
same Vista and Windows 7 wakeup programming key. The F71869A is asserted PME or PSOUT to
wakeup PC system. Where wake up programming function is reference from Microsoft Vista and
windows 7 remote controller specification.
The F71869A supports 1 IR transceiver function for blaster application and two IR receivers
for long range frequency and wideband application. The wide-band receiver is necessary to
support IR learning, IR-blasting and set-top box control.
The long-range receiver is a receiver which has the following characteristics:
1. Works at a distance of 10 meters.
2. Demodulates the signal inside the receiver part
3. Has a BPF which works with carriers from 32-60 kHz.
The wide-band receiver is a receiver part which has the following characters:
1. Works at a distance of approximately 5 centimeters.
2. Does not demodulate the signal inside the receiver part
3. Works with carriers from 32-60 kHz. (Probably doesn’t have a BPF, but still has the
same (or wider) range.
About IR information, reference Microsoft Windows Vista / 7 IR receiver or transceiver
emulation device spec.
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5.9
Intel Cougar Point Timing (CPT)
F71869A
The F71869A supports Intel Cougar Point Chipset timing for Sandy Bridge. There are 4 pins
for CPT control: SUS_WARN#, SUS_ACK#, SLP_SUS# and DPWROK.
For entering Intel Deep Sleep Well (DSW) state, the PCH will assert SUS_WARN# and turn off
5VDUAL. After the level of 5VDUAL is lower than 1.05V, F71869A will assert SUS_ACK# to inform
PCH it is ready for entering DSW. Finally, PCH will ramp down the internal VccSUS and assert
SLP_SUS# to F71869A. F71869A will turn off the 5VSB and 3VSB by ERP_CTRL0# and enter the
DSW state.
To exit DSW state, PCH will de-assert SLP_SUS#, turn on the SUS rail FETs and ramp up
internal 1.05V VccSUS. After the SUS rails voltages are up, RSMRST# will be desserted and the
PCH will release SUS_WARN# so that the 5VDUAL will ramp up.
Because the DSW function is controlled by F71869A instead of controlled by PCH directly,
there will be more wakeup events such as LAN, KB/Mouse, SIO RI# wake up rather than the 3
wakeup events (RTC, Power Button and GPIO27) for Intel DSW.
In order to achieve lower power consumption, F71869A provides the ERP_CTRL1# to turn off
the V3A so that the system can enter the Fintek G3’ state.
The block diagram below shows how the connection and control method for F71869A and
PCH.
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5.10 Scan Code Function
F71869A has 8 GPIO pins (GPIO 35~37, GPIO 50~54) support scan code. These pins can not
only be set to volume up/down, mute and PWM up/down but also any function keys on keyboard.
Because the protocol for these 5 pins is scan code, so we don’t need a driver to connect this
function to OS. If the button for the GPIO has been pressed continuesly over nearly 1 second
(delay time), the GPIO will repeatedly sending this function in an interval of 50 ms (repeat time).
The delay time could be set from 0.5 to 1.5 sec. The repeat time could be set from 50, 100, 250 to
500 ms.
5.11 Over Voltage Protection
F71869A over voltage protection function could protect the damage from voltage spikes via
over voltage protection (OVP) function. Voltage protection function is enabled via setting the
related register. When force mode occurs, the system would shut down and then can not boot at
all. Only re-plugging the power code (cut off VSB) could re-activate or re-boot the system at the
force mode. Please see below table for detail information:
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6. Register Description
The configuration register is used to control the behavior of the corresponding devices. To
configure the register, using the index port to select the index and then writing data port to alter
the parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down
the SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key
0x87 must be written to the index port. To disable configuration, write exit key 0xAA to the index
port. Following is a example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87
(enable configuration)
-o 4e aa
(disable configuration)
The Following is a register map (total devices) grouped in hexadecimal address order, which shows
a summary of all registers and their default value. Please refer each device chapter if you want
more detail information.
Global Control Registers
“-“ Reserved or Tri-State
Global Control Registers
Register
0x[HEX]
Default Value
Register Name
MSB
LSB
02
Software Reset Register
-
-
-
-
-
-
-
0
07
Logic Device Number Register (LDN)
0
0
0
0
0
0
0
0
20
Chip ID Register 1
0
0
0
1
0
0
0
0
21
Chip ID Register 2
0
0
0
0
0
1
1
1
23
Vendor ID Register 1
0
0
0
1
1
0
0
1
24
Vendor ID Register 2
0
0
1
1
0
1
0
0
25
Software Power Down Register
-
-
-
-
0
0
0
0
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26
UART IRQ Sharing Register
0
-
0
-
0
0
0
0
27
Configuration Port Select Register
1/0
0
1/0
1/0
-
-
-
1/0
28
Multi-function Select Register1
0
0
1
1
1
0
0
0
29
Multi-function Select Register2
0
1
1
0
1
1
1
1
29
WDT Clock Divisor High Byte
-
-
-
-
0
0
1
1
2A
Multi-function Select Register3
0
0
0
0
1
1
1
1
2A
WDT Clock Divisor Low Byte
1
1
1
0
0
1
1
1
2B
Multi-function Select Register4
0
0
0
0
1
1
1
1
2B
WDT Clock Fine Tune Count High Byte
-
-
-
-
-
-
-
-
2C
Multi-function Select Register 5
0
0
0
0
0
0
0
0
2C
WDT Clock Fine Tune Count Low Byte
-
-
-
-
-
-
-
-
2D
Wakeup Control Register
0
0
1
0
1
0
0
0
Device Configuration Registers
“-“ Reserved or Tri-State
FDC Device Configuration Registers (LDN CR00)
Register
0x[HEX]
Default Value
Register Name
MSB
LSB
30
FDC Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
1
61
Base Address Low Register
1
1
1
1
0
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
1
1
0
74
DMA Channel Select Register
-
-
-
-
-
0
1
0
F0
FDD Mode Register
0
-
-
0
1
1
1
0
F2
FDD Drive Type Register
-
-
-
-
-
-
1
1
F4
FDD Selection Register
-
-
-
0
0
-
0
0
UART1 Device Configuration Registers (LDN CR01)
Register
0x[HEX]
Default Value
Register Name
MSB
LSB
30
UART1 Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
1
61
Base Address Low Register
1
1
1
1
1
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
1
0
0
F0
RS485 Enable Register
-
-
0
0
-
-
-
-
UART2 Device Configuration Registers (LDN CR02)
Register
Register Name
Default Value
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0x[HEX]
MSB
LSB
30
UART2 Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
0
61
Base Address Low Register
1
1
1
1
1
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
0
1
1
F0
RS485 Enable Register
-
-
-
0
0
0
-
-
F1
SIR Mode Control Register
-
-
0
0
0
1
0
0
Parallel Port Device Configuration Registers (LDN CR03)
Register
Default Value
Register Name
0x[HEX]
MSB
LSB
30
Parallel Port Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
1
61
Base Address Low Register
0
1
1
1
1
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
1
1
1
74
DMA Channel Select Register
-
-
-
0
-
0
1
1
F0
PRT Mode Select Register
0
1
0
0
0
0
1
0
Hardware Monitor Device Configuration Registers (LDN CR04)
Register
Default Value
Register Name
0x[HEX]
MSB
LSB
30
H/W Monitor Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
0
61
Base Address Low Register
1
0
0
1
0
1
0
1
70
IRQ Channel Select Register
-
-
-
-
0
0
0
0
KBC Device Configuration Registers (LDN CR05)
Register
Default Value
Register Name
0x[HEX]
MSB
LSB
30
KBC Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
0
0
61
Base Address Low Register
0
1
1
0
0
0
0
0
70
KB IRQ Channel Select Register
-
-
-
-
0
0
0
1
72
Mouse IRQ Channel Select Register
-
-
-
-
1
1
0
0
F0
Clock Select Register
1
0
-
-
-
-
1
1
FE
Swap Register
1
-
-
0
0
0
0
1
FF
User Wakeup Code Register
0
0
1
0
1
0
0
1
GPIO Device Configuration Registers (LDN CR06)
Register
0x[HEX]
Default Value
Register Name
MSB
51
LSB
Oct., 2011
V0.19P
F71869A
30
GPIO Device Enable Register
-
-
-
-
-
-
-
0
60
Base Address High Register
0
0
0
0
0
0
0
0
61
Base Address Low Register
0
0
0
0
0
0
0
0
70
GPIRQ Channel Select Register
-
-
-
-
0
0
0
0
F0
GPIO Output Enable Register
-
-
0
0
0
0
0
0
F1
GPIO Output Data Register
-
-
1
1
1
1
1
1
F2
GPIO Pin Status Register
-
-
-
-
-
-
-
-
F3
GPIO Drive Enable Register
-
-
0
0
0
0
0
0
E0
GPIO1 Output Enable Register
0
0
0
0
0
0
0
0
E1
GPIO1 Output Data Register
1
1
1
1
1
1
1
1
E2
GPIO1 Pin Status Register
-
-
-
-
-
-
-
-
E3
GPIO1 Drive Enable Register
0
0
0
0
0
0
0
0
E4
GPIO1 PME Enable Register
0
0
0
0
0
0
0
0
E5
GPIO1 Detect Edge Select Register
0
0
0
0
0
0
0
0
E6
GPIO1 PME Status Register
0
0
0
0
0
0
0
0
D0
GPIO2 Output Enable Register
0
0
0
0
0
0
0
0
D1
GPIO2 Output Data Register
1
1
1
1
1
1
1
1
D2
GPIO2 Pin Status Register
-
-
-
-
-
-
-
-
D3
GPIO2 Drive Enable Register
0
0
0
0
0
0
0
0
C0
GPIO3 Output Enable Register
0
0
0
0
0
0
0
0
C1
GPIO3 Output Data Register
1
1
1
1
1
1
1
1
C2
GPIO3 Pin Status Register
-
-
-
-
-
-
-
-
B0
GPIO4 Output Enable Register
-
-
-
-
0
0
0
0
B1
GPIO4 Output Data Register
-
-
-
-
1
1
1
1
B2
GPIO4 Pin Status Register
-
-
-
-
-
-
-
-
B3
GPIO4 Drive Enable Register
-
-
-
-
0
0
0
0
B4
GPIO4 PME Enable Register
-
-
-
-
0
0
0
0
B5
GPIO4 Detect Edge Select Register
-
-
-
-
0
0
0
0
B6
GPIO4 PME Status Register
-
-
-
-
0
0
0
0
A0
GPIO5 Output Enable Register
-
-
-
0
0
0
0
0
A1
GPIO5 Output Data Register
-
-
-
1
1
1
1
1
A2
GPIO5 Pin Status Register
-
-
-
-
-
-
-
-
A4
GPIO5 PME Enable Register
0
0
0
0
0
0
0
0
A5
GPIO5 Detect Edge Select Register
0
0
0
0
0
0
0
0
A6
GPIO5 PME Status Register
0
0
0
0
0
0
0
0
A9
GPIO5 KBC Emulation Control Register 1
0
0
0
0
0
0
0
0
AB
GPIO5 KBC Emulation Make Code Register
0
0
0
0
0
0
0
0
52
Oct., 2011
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AC
GPIO5 KBC Emulation Prefix Code Register
1
1
1
0
0
0
0
0
AD
GPIO5 KBC Emulation Status Register 1
0
0
0
0
0
0
0
0
AE
GPIO5 KBC Emulation Status Register 2
0
0
0
0
0
0
0
0
AF
GPIO5 KBC Emulation Control Register 2
0
1
0
0
0
0
0
0
90
GPIO6 Output Enable Register
0
0
0
0
0
0
0
0
91
GPIO6 Output Data Register
1
1
1
1
1
1
1
1
92
GPIO6 Pin Status Register
-
-
-
-
-
-
-
-
80
GPIO7 Output Enable Register
0
0
0
0
0
0
0
0
81
GPIO7 Output Data Register
1
1
1
1
1
1
1
1
82
GPIO7 Pin Status Register
-
-
-
-
-
-
-
-
83
GPIO7 Drive Enable Register
0
0
0
0
0
0
0
0
WDT Device Configuration Registers (LDN CR07)
Register
Default Value
Register Name
0x[HEX]
MSB
LSB
F0
Watchdog Timer Enable Register
-
-
-
-
-
-
-
1
F2
BUS Manual Register
0
0
0
0
0
0
0
0
F3
Key Data Register
0
0
0
0
0
0
0
0
F4
BUSIN Status Register
-
-
-
-
-
-
-
-
F5
WDT Unit Select Register
-
0
-
0
0
0
0
0
F6
WDT Count Register
0
0
0
0
1
0
1
0
F7
Watchdog Timer PME Register
0
0
0
-
-
-
-
0
CIR Configuration Register (LDN CR08)
Register
0x[HEX]
Default Value
Register Name
MSB
LSB
30
CIR Device Enable Register
-
-
-
-
-
-
-
0
60
Base Address High Register
0
0
0
0
0
0
0
0
61
Base Address Low Register
0
0
0
0
0
0
0
0
70
CIR IRQ Channel Select Register
-
-
-
-
0
0
0
0
F0
Reserved
-
-
-
-
-
-
-
-
F1
Reserved
-
-
-
-
-
-
-
-
F8
Reserved
0
0
0
0
0
0
0
0
F9
Reserved
0
0
0
0
0
0
0
0
FA
Reserved
1
0
0
0
0
0
0
0
FB
Reserved
0
0
1
1
1
0
1
1
FC
Reserved
0
0
0
0
0
0
0
0
FD
Reserved
0
0
0
0
0
0
0
0
FE
Reserved
0
0
0
0
0
0
0
0
PME, ACPI, and ERP Power Saving Device Configuration Registers (LDN CR0A)
53
Oct., 2011
V0.19P
F71869A
Register
Default Value
Register Name
0x[HEX]
MSB
LSB
30
PME Device Enable Register
-
-
-
-
-
-
-
0
E0
ERP Enable Register
0
-
-
-
-
-
0
0
E1
ERP Control Register
1
1
0
0
1
1
0
0
E2
ERP Control Register
-
0
1
1
1
1
0
-
E3
ERP PSIN Deb-Register
0
0
0
1
0
0
1
1
E4
ERP RSMRST Deb-Register
0
0
0
0
1
0
0
1
E5
ERP PSOUT Deb-Register
1
1
0
0
0
1
1
1
E6
ERP PSON Deb-Register
0
0
0
0
1
0
0
1
E7
ERP S5 Delay Register
0
1
1
0
0
0
1
1
E8
Wakeup Enable Register
0
-
0
0
1
0
0
0
E9
ERP S3 Delay Register
0
0
0
0
1
1
1
1
EC
ERP Mode Select Register
0
0
0
-
-
-
-
-
ED
ERP WDT Control Register
-
-
-
-
-
-
0
0
EE
ERP WDT Timer
-
-
-
-
-
-
-
0
F0
PME Event Enable Register 1
0
0
0
0
0
0
0
0
F1
PME Event Status Register 1
-
-
-
-
-
-
-
-
F2
PME Event Enable Register 2
-
-
-
0
-
0
0
0
F3
PME Event Status Register 2
-
-
-
-
-
-
-
-
F4
Keep Last State Select Register
0
0
0
0
0
1
1
0
F5
VDDOK Delay Select Register
0
0
0
1
1
1
0
0
F6
PCIRST Control Register
0
0
0
1
1
1
1
1
F7
Power Sequence Control Register
1
0
0
0
0
1
1
0
F8
LED VCC Control Register
0
0
0
0
0
0
0
0
F9
LED VSB Control Register
-
0
0
0
0
0
0
0
FA
LED VSB Additional Control Register
-
0
0
0
-
0
0
0
FC
Intel DSW Delay Register
-
-
-
-
0
1
1
1
FE
RI De-bounce Select Register
0
0
-
0
-
-
0
0
6.1
Global Control Registers
6.1.1
Software Reset Register ⎯ Index 02h
Bit
Name
R/W Default
Description
7-1
Reserved
-
-
Reserved
0
SOFT_RST
R/W
0
Write 1 to reset the register and device powered by VDD ( 3VCC ).
54
Oct., 2011
V0.19P
F71869A
6.1.2
Bit
Logic Device Number Register (LDN) ⎯ Index 07h
Name
R/W Default
Description
00h: Select FDC device configuration registers.
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
7-0
LDN
R/W
00h
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select WDT device configuration registers.
0ah: Select PME & ACPI device configuration registers.
6.1.3 Chip ID Register 1 ⎯ Index 20h
Bit
Name
7-0
Chip_ID1
R/W Default
R
Description
10h
Chip ID1
6.1.4 Chip ID Register 2 ⎯ Index 21h
Bit
Name
7-0
Chip_ID2
R/W Default
R
Description
07h
Chip ID2
6.1.5 Vendor ID Register 1 ⎯ Index 23h
Bit
Name
7-0
Vendor_ID1
R/W Default
R
Description
19h
Vendor ID1
6.1.6 Vendor ID Register 2 ⎯ Index 24h
Bit
Name
7-0
Vendor_ID2
R/W Default
R
34h
Description
Vendor ID2
6.1.7 Software Power Down Register ⎯ Index 25h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved.
3
SOFTPD_PRT
R/W
0
Set “1” to power down Parallel Port. The clock will stop.
55
Oct., 2011
V0.19P
F71869A
2
SOFTPD_UR2
R/W
0
Set “1” to power down UART 2. The clock will stop.
1
SOFTPD_UR1
R/W
0
Set “1” to power down UART 1. The clock will stop.
0
SOFTPD_FDC
R/W
0
Set “1” to power down FDC. The clock will stop.
6.1.8 UART IRQ Sharing Register ⎯ Index 26h
Bit
Name
7
CLK24M_SEL
R/W
0
6
Reserved
-
-
5
R/W Default
DPORT_DEC_SEL R/W
0
Description
0: CLKIN is 48MHz
1: CLKIN is 24MHz
Reserved.
0: The debug port address is 0x80.
1: The debug port address is UART2 base address.
4
Reserved
-
-
Reserved.
3
CLK_TUNE_EN
R/W
0
Set “1” to switch index 0x29 ~ 0x2C to WDT clock fine tune registers.
2
TX_DEL_1BIT
R/W
0
1
IRQ_MODE
R/W
0
0
IRQ_SHAR
R/W
0
0: UART transmits data immediately after writing THR.
1: UART transmits data delay one bit time after writing THR.
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
6.1.9 Configuration Port Select Register ⎯ Index 27h
Bit
Name
R/W Default
Description
1: Alarm mode. Voltage protection is default disabled.
7
OVP_MODE
R/W
-
0: Force mode. Voltage protection is default enabled.
This bit is power on strapped by RTS1#/STRAP_PROTECT. Pull down
to select force mode.
Debug port output select.
6
TEMP_OUT_EN
R/W
0
0: 80 port data.
1: Temperature fetched by hardware mmonitor.
56
Oct., 2011
V0.19P
F71869A
0: Disable debug port.
5
DPORT_EN
R/W
-
1: Enable debug port.
This bit is power on strapped by
GPIO26/SOUT2/SEGB/STRAP_DPORT. Pull down to disable.
0: The configuration register port is 2E/2F.
4
PORT_4E_EN
R/W
-
1: The configuration register port is 4E/4F.
This register is power on trapped by SOUT1/ Config4E_2E. Pull down
to select port 2E/2F.
3-1
Reserved
-
-
Reserved.
This bit is the pin status of TIMING_GPIO pin.
0
TIMING_EN
R
-
0: Disable power sequence control.
1: Enable power sequence control.
6.1.10 Multi-Function Select Register 1⎯ Index 28h (Powered by VSB3V)
Bit
Name
R/W Default
Description
Select GPIO5/GPIO3 reset signal.
7
FDC_GP_RST_SEL R/W
0
0: Reset by internal VSB3V power good.
1: Reset by LRESET#.
6
5
4
Reserved
PWR_
S3_Gate#_EN
PWR_
S3P5_Gate#_EN
R/W
0
Reserved
0: S3_Gate#/GPIO05/WDTRST# functions as GPIO05/WDTRST#
R/W
1
determined by GPIO05_EN.
1: S3_Gate#/GPIO05/WDTRST# functions as S3_Gate#.
0: S3P5_Gate#/SLOTOCC#/GPIO04 functions as
R/W
1
SLOTOCC#/GPIO04 determined by GPIO04_EN.
1: S3P5_Gate#/SLOTOCC#/GPIO04 functions as S3P5_Gate#.
0: S3_Gate#/GPIO05/WDTRST# functions as WDTRST if PWR_
3
GPIO05_EN
R/W
1
S3_Gate#_EN is not set.
1: S3_Gate#/GPIO05/WDTRST# functions as GPIO05 is PWR_
S3_Gate#_EN is not set.
0: S3P5_Gate#/SLOTOCC#/GPIO04 functions as SLOTOCC# if
2
GPIO04_EN
R/W
0
PWR_ S3P5_Gate#_EN is not set.
1: S3P5_Gate#/SLOTOCC#/GPIO04 functions as GPIO04 if PWR_
S3P5_Gate#_EN is not set.
57
Oct., 2011
V0.19P
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1
PIN60_LVL_SEL
R/W
0
0
PIN59_LVL_SEL
R/W
0
0: Pin 60 input level is TTL level.
1: Pin 60 input level is low level (0.6V/0.9V).
0: Pin 59 input level is TTL level.
1: Pin 59 input level is low level (0.6V/0.9V).
6.1.11 Multi-Function Select Register 2 ⎯ Index 29h (Powered by VBAT CLK_TUNE_EN = 0)
Bit
Name
R/W Default
Description
CPU_PWGD/GPIO17 function select.
7
GPIO17_EN
R/W
0
0: The pin function is CPU_PWGD.
1: The pin function is GPIO17.
GPIO16/LED_VCC function select.
6
GPIO16_EN*
R/W
1
0: The pin function is LED_VCC.
1: The pin function is GPIO16.
This bit is powered by VBAT.
GPIO15/LED_VSB/ALERT# function select.
{LED_VSB_EN, GPIO15_EN}
5
GPIO15_EN
R/W
1
1x: The pin function is LED_VSB.
01: The pin function is GPIO15.
00: The pin function is ALERT#.
WDTRST#/GPIO14 function select.
4
GPIO14_EN
R/W
0
0: The pin function is WDTRST#.
1: The pin function is GPIO14.
S0P5_Gate#/GPIO13/BEEP function select.
If S0P5_Gate#_EN is set , the ping function is S0P5_Gate#, The pin
function is determined by
3
GPIO13_EN
R/W
1
{ S0P5_Gate#_EN, GPIO13_EN}
1x: The pin function is S0P5_Gate#.
01: The pin function is GPIO13.
00: The pin function is BEEP.
GPIO12/ RSTCON#/FANCTL1 function select.
2
GPIO12_EN
R/W
1
0: The pin function is FANCTL1.
1: The pin function is GPIO12.
58
Oct., 2011
V0.19P
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GPIO11/PCIRST5#/SDA function select.
If IBX_ALT_EN is set , the ping function is SDA, otherwise the pin
1
GPIO11_EN
R/W
1
function is determined by this bit:
0: The pin function is PCIRST5#.
1: The pin function is GPIO11.
GPIO10/PCIRST4#/SCL function select.
If IBX_ALT_EN is set , the ping function is SCL, otherwise the pin
0
GPIO10_EN
R/W
1
function is determined by this bit:
0: The pin function is PCIRST4#.
1: The pin function is GPIO10.
6.1.12 WDT Clock Divisor High Byte ⎯ Index 29h (Powered by VBAT, CLK_TUNE_EN = 1)
Bit
7
6-4
3-0
Name
WDT_TUNE_STAR
T
Reserved
WDT_CLK_DIV[11:
8]
R/W Default
W
-
-
-
Description
Write “1” to this bit to start count internal 500KHz period (10 times).
Reserved.
This is the high nibble of 12-bit divisor for WDT clock. The clock used
R/W
3h
for WDT is 10Hz which is divided by internal 10KHz clock. Program
this divisor to fine tune clock.
6.1.13 Multi-Function Select Register 3 ⎯ Index 2Ah (Powered by VBAT, CLK_TUNE_EN = 0)
Bit
Name
R/W Default
Description
Parallel Port/GPIO function select.
7
LPT_GP_EN
R/W
0
0: Pin 100 ~ 116 functions as Parallel Port.
1: Pin 100 ~ 116 functions as GPIO6 and GPIO7.
Alternative IBX pin enable.
6
IBX_ALT_EN
R/W
0
0: Disable IBX alternative pins.
1: Enable IBX alternative pins. See GPIO11_EN and GPIO10_EN for
detail.
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Oct., 2011
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GPIO15/LED_VSB/ALERT# function select.
{LED_VSB_EN, GPIO15_EN}
5
LED_VSB_EN
R/W
0
1x: The pin function is LED_VSB.
01: The pin function is GPIO15.
00: The pin function is ALERT#.
RSTCON# Enable Register:
4
RSTCON_PIN_EN R/W
0
0: The pin function of GPIO12/ RSTCON#/FANCTL1 is GPIO12/
FANCTL1
1: The pin function of GPIO12/RSTCON#/FANCTL1 is RSTCON#.
S0P5_Gate#/GPIO13/BEEP function select.
If S0P5_Gate#_EN is set , the ping function is S0P5_Gate#, The pin
function is determined by
3
S0P5_Gate# _EN R/W
1
{ S0P5_Gate#_EN, GPIO13_EN}
1x: The pin function is S0P5_Gate#.
01: The pin function is GPIO13.
00: The pin function is BEEP.
2
FDC_GP_EN
R/W
1
Set “1” will disable FDC and change the FDC pins to GPIOs.
= 0 set pin5, 6 to be SOUT2 and SIN2
1
UR2_GP_EN2
R/W
1
= 1 will change pin5, 6 (SOUT2 and SIN2) to GPIOs.
Set UR2_GP_EN1 and UR2_GP_EN2 will also disable UART2 I/O
port.
= 0 will change pin 1, 2, 3, 126, 127 and 128 to be DTR2#, RTS2#,
DSR2#, DCD2#, RI2# and CTS2#.
0
UR2_GP_EN1
R/W
1
= 1 will change pin 1, 2, 3, 126, 127 and 128 to be GPIO.
Set UR2_GP_EN1 and UR2_GP_EN2 will also disable UART2 I/O
port.
6.1.14 WDT Clock Divisor Low Byte ⎯ Index 2Ah (Powered by VBAT, CLK_TUNE_EN = 1)
Bit
Name
R/W Default
Description
This is the high nibble of 12-bit divisor for WDT clock. The clock used
7-0
WDT_CLK_DIV[7:0] R/W
E7h
for WDT is 10Hz which is divided by internal 10KHz clock. Program
this divisor to fine tune clock.
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6.1.15 Multi-Function Select Register 4 ⎯ Index 2Bh (Powered by VSB3V, CLK_TUNE_EN = 0)
Bit
Name
R/W Default
Description
PSON#/GPIO47 function select.
7
GPIO47_EN
R/W
0
0: The pin function is PSON#.
1: The pin function is GPIO47.
PSOUT#/GPIO46 function select.
6
GPIO46_EN
R/W
0
0: The pin function is PSOUT#.
1: The pin function is GPIO46.
PSIN#/GPIO45 function select.
5
GPIO45_EN
R/W
0
0: The pin function is PSIN#.
1: The pin function is GPIO45.
ATXPG_IN/GPIO44 function select.
4
GPIO44_EN
R/W
0
0: The pin function is ATXPG_IN.
1: The pin function is GPIO44.
GPIO43/IRRX function select.
3
GPIO43_EN
R/W
1
0: The pin function is IRRX.
1: The pin function is GPIO43.
GPIO42/IRTX function select.
2
GPIO42_EN
R/W
1
0: The pin function is IRTX.
1: The pin function is GPIO42.
FANCTRL3/GPIO41 function select.
1
GPIO41_EN
R/W
1
0: The pin function is FANCTRL3.
1: The pin function is GPIO41.
FANIN3/GPIO40 function select.
0
GPIO40_EN
R/W
1
0: The pin function is FANIN3.
1: The pin function is GPIO40.
6.1.16 WDT Clock Fine Tune Count ⎯ Index 2Bh (Powered by VSB3V, CLK_TUNE_EN = 1)
Bit
Name
R/W Default
Description
7
WDT_TUNE_ST
W
-
This bit will be one if the counting action is in process.
6-4
Reserved
-
-
Reserved.
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This is the high nibble of 12-bit count for WDT clock fine tune.
3-0
CLK_TUNE_CNT[1
1:8]
R/W
-
Hardware use 48MHz clock to count the internal 500KHz clock 10
times. The ideal value will be 960. The error is used to calculate the
divisor for WDT clock.
6.1.17 Multi-Function Select Register 5 ⎯ Index 2Ch (Powered by I_VSB3V, CLK_TUNE_EN = 0)
Bit
Name
R/W Default
Description
Enable pin 60 SDA function.
7
TSI_PIN60_EN
R/W
0
0: The pin function is GPIO11/PCI_RST5#.
1: The pin function is SDA.
Enable pin 59 SCL function.
6
TSI_PIN59_EN
R/W
0
0: The pin function is GPIO10/PCI_RST4#.
1: The pin function is SCL.
Enable pin 58 SDA function.
5
TSI_PIN58_EN
R/W
0
0: The pin function is PECI.
1: The pin function is SDA.
Enable pin 57 SCL function.
4
TSI_PIN57_EN
R/W
0
0: The pin function is CIR_LED#.
1: The pin function is SCL.
CIRRX#/GPIO03 function select.
3
GPIO03_EN
R/W
0
0: The pin function is CIRRX#.
1: The pin function is GPIO03.
CIRTX#/GPIO02function select.
2
GPIO02_EN
R/W
0
0: The pin function is CIRTX#.
1: The pin function is GPIO02.
CIRWB#/GPIO01 function select.
1
GPIO01_EN
R/W
0
0: The pin function is CIRWB#.
1: The pin function is GPIO01.
0
Reserved
R/W
0
Reserved
6.1.18 WDT Clock Fine Tune Count ⎯ Index 2Ch (Powered by VSB3V, CLK_TUNE_EN = 1)
Bit
Name
R/W Default
Description
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This is the high nibble of 12-bit count for WDT clock fine tune.
7-0
CLK_TUNE_CNT[7
:0]
R/W
-
Hardware use 48MHz clock to count the internal 500KHz clock 10
times. The ideal value will be 960. The error is used to calculate the
divisor for WDT clock.
6.1.19 Wakeup Control Register ⎯ Index 2Dh (Powered by VBAT)
Bit
Name
R/W Default
7
SLOT_PWR_SEL R/W
0
6
VSBOK_HYS_DIS R/W
0
Description
0: SLOTOCC# is pull-up to VSB3V.
1: SLOTOCC# is pull-up to VBAT.
Set “1” to disable VSBOK hysteresis.
0: VSB3V power good level is 3.05V and not good level is 2.95V.
1: VSB3V power good level is 2.8V and not good level is 2.5V.
By VSBOK_HYS_DIS and VSBOK_LVL_SEL, RSMRST# falling edge
5
VSBOK_LEVEL
_SEL
R/W
1
could be determined:
00: when VSB3V is lower than 2.95V.
01: when VSB3V is lower than 2.5V.
10: when VSB3V is lower than 3.05V.
11: when VSB3V is lower than 2.8V.
4
KEY_SEL_ADD
R/W
0
3
WAKEUP_EN
R/W
1
This bit is added to add more wakeup key function.
0: disable keyboard/mouse wake up.
1: enable keyboard/mouse wake up.
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This registers select the keyboard wake up key. Accompanying with
KEY_SEL_ADD, there are eight wakeup keys:
2-1
KEY_SEL
R/W
KEY_SEL_ADD
KEY_SEL
0
00
Ctrl + Esc
0
01
Ctrl + F1
0
10
Ctrl + Space
0
11
Any Key
1
00
Windows Wakeup
1
01
Windows Power
1
10
Ctrl + Alt + Space
1
11
Space
00
Wakeup Key
This register selects the mouse wake up key.
0
MO_SEL
R/W
0
0: Wake up by click.
1: Wake up by click and movement.
6.2
FDC Registers (CR00)
6.2.1 FDC Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
FDC_EN
R/W
1
Description
Reserved
0: disable FDC.
1: enable FDC.
6.2.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of FDC base address.
6.2.3 Base Address Low Register ⎯ Index 61h
Bit
7-0
Name
R/W Default
BASE_ADDR_LO R/W
F0h
Description
The LSB of FDC base address.
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6.2.4 IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELFDCIRQ
R/W
06h
Description
Reserved.
Select the IRQ channel for FDC.
6.2.5 DMA Channel Select Register ⎯ Index 74h
Bit
Name
R/W Default
7-3
Reserved
-
-
2-0
SELFDCDMA
R/W
010
Description
Reserved.
Select the DMA channel for FDC.
6.2.6 FDD Mode Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7
FDC_SW_PD
R/W
0
Write “1” to software power down FDC.
6-5
Reserved
-
-
Reserved.
4
FDC_SW_WP
R/W
0
Write “1” to this bit will force FDC to write protect. Otherwise, write
protect is controlled by hardware pin WP#.
00: Model 30 mode.
3-2
IF_MODE
R/W
11
01: PS/2 mode.
10: Reserved.
11: AT mode (default).
1
FDMAMODE
R/W
1
0
EN3MODE
R/W
0
0: enable burst mode.
1: non-busrt mode (default).
0: normal floppy mode (default).
1: enhanced 3-mode FDD.
6.2.7 FDD Drive Type Register ⎯ Index F2h
Bit
Name
R/W Default
7-2
Reserved
-
-
1-0
FDD_TYPE
R/W
11
Description
Reserved.
FDD drive type.
6.2.8 FDD Selection Register ⎯ Index F4h
Bit
Name
7-5
Reserved
R/W Default
-
-
Description
Reserved.
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Data rate table select, refer to table A.
00: select regular drives and 2.88 format.
4-3
FDD_DRT
R/W
00
01: 3-mode drive.
10: 2 mega tape.
11: reserved.
2
Reserved
-
-
1-0
FDD_DT
R/W
00
Reserved.
Drive type select, refer to table B.
TABLE A
Data Rate Table Select
FDD_DRT[1]
Data Rate
FDD_DRT[0]
0
DATARATE0
MFM
FM
0
0
500K
250K
1
0
1
300K
150K
0
1
0
250K
125K
0
1
1
1Meg
---
1
0
0
500K
250K
1
0
1
500K
250K
0
1
0
250K
125K
0
1
1
1Meg
---
1
0
0
500K
250K
1
0
1
2Meg
---
0
1
0
250K
125K
0
1
1
1Meg
---
1
1
1
0
Drive Type
FDD_DT1
DENSEL
DATARATE1
0
0
Selected Data Rate
FDD_DT0
0
DRVDEN0
DENSEL
0
Remark
4/2/1 MB 3.5”
2/1 MB 5.25”
1/1.6/1 MB 3.5” (
0
1
DATARATE1
1
0
DENSEL#
1
1
DATARATE0
TABLE B
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6.3
UART1 Registers (CR01)
6.3.1 UART 1 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
UR1_EN
R/W
1
Description
Reserved
0: disable UART 1.
1: enable UART 1.
6.3.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of UART 1 base address.
6.3.3 Base Address Low Register ⎯ Index 61h
Bit
7-0
Name
R/W Default
BASE_ADDR_LO R/W
F8h
Description
The LSB of UART 1 base address.
6.3.4 IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELUR1IRQ
R/W
4h
Description
Reserved.
Select the IRQ channel for UART 1.
6.3.5 RS485 Enable Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7-6
Reserved
-
-
Reserved.
5
RS485_INV
-
-
Write “1” will invert the RTS# if RS485_EN is set.
0: RS232 driver.
4
RS485_EN
R/W
0
1: RS485 driver. RTS# drive high when transmitting data, otherwise is
kept low.
3-0
Reserved
-
-
Reserved.
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6.4
UART2 Registers (CR02)
6.4.1 UART 2 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
UR2_EN
R/W
1
Description
Reserved
0: disable UART 2.
1: enable UART 2.
6.4.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
02h
Description
The MSB of UART 2 base address.
6.4.3 Base Address Low Register ⎯ Index 61h
Bit
7-0
Name
R/W Default
BASE_ADDR_LO R/W
F8h
Description
The LSB of UART 2 base address.
6.4.4 IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELUR2IRQ
R/W
3h
Description
Reserved.
Select the IRQ channel for UART 2.
6.4.5 RS485 Enable Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7-6
Reserved
-
-
Reserved.
5
RS485_INV
-
-
Write “1” will invert the RTS# if RS485_EN is set.
0: RS232 driver.
4
RS485_EN
R/W
0
1: RS485 driver. RTS# drive high when transmitting data, otherwise is
kept low.
0: No reception delay when SIR is changed form TX to RX.
3
RXW4C_IR
R/W
0
1: Reception delays 4 characters time when SIR is changed form TX
to RX.
0: No transmission delay when SIR is changed form RX to TX.
2
TXW4C_IR
R/W
0
1: Transmission delays 4 characters time when SIR is changed form
RX to TX.
1-0
Reserved
-
-
Reserved.
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6.4.6 SIR Mode Control Register ⎯ Index F1h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
Reserved
-
-
Reserved.
5
Reserved
-
-
Reserved.
00: disable IR function.
4-3
IRMODE
R/W
00
01: disable IR function.
10: IrDA function, active pulse is 1.6uS.
11: IrDA function, active pulse is 3/16 bit time.
0: SIR is in full duplex mode for Loopback test. TXW4C_IR and
2
HDUPLX
R/W
1
RXW4C_IR are of no use.
1: SIR is in half duplex mode.
6.5
1
TXINV_IR
R/W
0
0
RXINV_IR
R/W
0
0: IRTX is in normal condition.
1: inverse the IRTX.
0: IRRX is in normal condition.
1: inverse the IRRX.
Parallel Port Register (CR03)
6.5.1 Parallel Port Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
PRT_EN
R/W
1
Description
Reserved
0: disable Parallel Port.
1: enable Parallel Port.
6.5.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of Parallel Port base address.
6.5.3 Base Address Low Register ⎯ Index 61h
Bit
7-0
Name
R/W Default
BASE_ADDR_LO R/W
78h
Description
The LSB of Parallel Port base address.
6.5.4 IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-5
Reserved
-
-
3-0
SELPRTIRQ
R/W
7h
Description
Reserved.
Select the IRQ channel for Parallel Port.
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6.5.5 DMA Channel Select Register ⎯ Index 74h
Bit
Name
7-5
Reserved
4
R/W Default
-
ECP_DMA_MODE R/W
0
3
Reserved
-
-
2-0
SELPRTDMA
R/W
011
Description
Reserved.
0: non-burst mode DMA.
1: enable burst mode DMA.
Reserved.
Select the DMA channel for Parallel Port.
6.5.6 PRT Mode Select Register ⎯ Index F0h
Bit
Name
R/W Default
Description
Interrupt mode in non-ECP mode.
7
SPP_IRQ_MODE R/W
0
0: Level mode.
1: Pulse mode.
6-3
ECP_FIFO_THR
R/W
1000
ECP FIFO threshold.
000: Standard and Bi-direction (SPP) mode.
001: EPP 1.9 and SPP mode.
010: ECP mode (default).
2-0
PRT_MODE
R/W
010
011: ECP and EPP 1.9 mode.
100: Printer mode.
101: EPP 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP1.7 mode.
6.6
Hardware Monitor Registers (CR04)
6.6.1
Hardware Monitor Configuration Registers ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
HM_EN
R/W
1
Description
Reserved
0: disable Hardware Monitor.
1: enable Hardware Monitor.
6.6.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
02h
Description
The MSB of Hardware Monitor base address.
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6.6.3 Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Default
7-0 BASE_ADDR_LO
R/W
95h
Description
The LSB of Hardware Monitor base address.
6.6.4 IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELHMIRQ
R/W
0000
Description
Reserved.
Select the IRQ channel for Hardware Monitor.
Before the device registers, the following is a register map order which shows a summary of all
registers. Please refer each one register if you want more detail information.
Register CR01 ~ CR03 Æ Configuration Registers
Register CR0A ~ CR0F Æ PECI/TSI Control Register
Register CR10 ~ CR37 Æ Voltage Setting Register
Register CR40 ~ CR4F Æ PECI 3.0 Command and Register
Register CR60 ~ CR8E Æ Temperature Setting Register
Register CR90 ~ CRDF Æ Fan Control Setting Register
ÆFan1 Detail Setting CRA0 ~ CRAF
ÆFan2 Detail Setting CRB0 ~ CRBF
ÆFan3 Detail Setting CRC0 ~ CRCF
6.6.5 Configuration Register ⎯ Index 01h
Bit
Name
R/W Default
Description
7-3
Reserved
-
0
Reserved
2
POWER_DOWN
R/W
0
Hardware monitor function power down.
1
FAN_START
R/W
1
0
V_T_START
R/W
1
Set one to enable startup of fan monitoring operations; a zero puts the
part in standby mode.
Set one to enable startup of temperature and voltage monitoring
operations; a zero puts the part in standby mode.
6.6.6 Configuration Register ⎯ Index 02h
Bit
Name
7
Reserved
6
R/W Default
R/W
0
CASE_BEEP_EN R/W
0
Description
Dummy register.
0: Disable case open event output via BEEP.
1: Enable case open event output via BEEP.
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5-4
OVT_MODE
R/W
0
00: The OVT# will be low active level mode.
01: The OVT# will be low pulse mode.
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
Dummy register.
3
Reserved
R/W
0
2
CASE_SMI_EN
R/W
0
1-0
ALERT_MODE
R/W
0: Disable case open event output via PME.
1: Enable case open event output via PME.
00: The ALERT# will be low active level mode.
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
0
6.6.7 Configuration Register ⎯ Index 03h
Bit
Name
R/W Default
7-1
Reserved
R/W
0
0
CASE_STS
R/W
1
Description
Reserved
Case open event status. Write 1 to clear if case open event cleared.
(This bit is powered by VBAT.)
6.6.8 NEW TSI Mode Enable Register Index 07h
Bit
Name
7-1
Reserved
0
R/W Default
0
-
0
New_TSI_MODE R/W
Description
Reserved
Set this bit to enable TSI new mode. Please check CR0A for more
detail.
6.6.9 Configuration Register ⎯ Index 08h
Bit
Name
R/W Default
Description
When AMD TSI or Intel PCH SMBus is enabled, this byte is used as
7-1
SMBUS_ADDR
R/W
7’h26 SMBUS_ADDR. SMBUS_ADDR[7:1] is the slave address sent by the
embedded master to fetch the temperature.
0
6.6.10
Reserved
-
-
Reserved
Configuration Register ⎯ Index 09h
Bit
Name
R/W Default
7-1
I2C_ADDR
R/W
0
0
Reserved
R/W
0
Description
I2C_ADDR[7:1] is the slave address sent by the embedded master
when using a block write command
Reserved
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6.6.11 Configuration Register ⎯ Index 0Ah
Bit
Name
7
BETA_EN
R/W
0
6
INTEL_MODEL
R/W
1
5
Reserved
-
0
4
MXM_MODE
R/W
0
3-2
VTT_SEL
R/W
0
1
TSI_EN
R/W Default
R/W
0
Description
0: disable the T1 beta compensation.
1: enable the T1 beta compensation.
0: AMD model.
1: Intel model.
Reserved.
Reserved
PECI (Vtt) voltage select.
00: Vtt is 1.23V
01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
0: Disable the TSI function via PECI / CIR_LED / PCI_RST4# /
PCI_RST5# pins.
1: Enable the TSI function via PECI / CIR_LED / PCI_RST4# /
PCI_RST5# pins.
This bit accompanies with INTEL_MODEL, IBX_ALT_EN, PECI_EN,
and it determines the availability of AMD TSI, Intel PCH SMBus, or
PECI.
Setting (CR07[0]-- NEW_TSI_MODE = 0)
INTEL
_MOD
EL
(CR0
A,
bit6)
TSI_
EN
(CR0
0
0
1
1
1
0
1
0
1
1
A,
PECI_
EN
(CR0A,
bit0)
IBX_ALT_
EN
(CR2A, bit6
in global
configurati
on register)
PE
CI
AMD
TSI
Intel
PCH
SMBus
X
X
1
1
0
X
X
X
1
X
N
N
Y
Y
N
N
Y
N
N
N
N
N
N
Y
Y
PE
CI
AMD
TSI
Intel
PCH
SMBus
N
N
Y
Y
N
N
N
N
Y
Y
N
Y
N
N
N
bit1)
Setting (CR07[0]-- NEW_TSI_MODE = 1)
0
PECI_EN
R/W
0
INTEL TSI_
PECI_
IBX_ALT_
_MOD
EN
EN
EN
EL
(CR0 (CR0A, (CR2A, bit6
bit0)
in global
(CR0
A,
A,
bit1)
configurati
bit6)
on register)
0
0
X
X
0
1
X
X
1
0
1
X
1
1
1
1
1
1
0
X
0: Disable PECI function via PECI pin
1: Enable PECI function via PECI pin
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6.6.12 Configuration Register ⎯ Index 0Bh
Bit
Name
R/W Default
Description
Select the Intel CPU socket number.
0000: no CPU presented. PECI host will use Ping() command to find
CPU address.
7-4
CPU_SEL
R/W
0
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 0, i.e. PECI address is 0x31.
0100: CPU is in socket 0, i.e. PECI address is 0x32.
1000: CPU is in socket 0, i.e. PECI address is 0x33.
Others are reserved.
3-1
Reserved
-
0
0
DOMAIN1_EN
R/W
0
Reserved.
If the CPU is selected as dual core. Set this register 1 to read the
temperature of domain1.
6.6.13 Configuration Register ⎯ Index 0Ch
Bit
Name
R/W Default
Description
TCC Activation Temperature.
When PECI is enabled, the absolute value of CPU temperature is
7-0
TCC_TEMP
R/W
8’h55 calculated by the equation:
CPU_TEMP = TCC_TEMP + PECI Reading.
The range of this register is -128 ~ 127.
6.6.14 Configuration Register ⎯ Index 0Dh
Bit
Name
R/W Default
Description
TSI Temperature offset for CPU
7-0
TSI_OFFSET
R/W
8’h00 When AMD TSI or Intel PCH SMBus is enabled, this byte is used as
the offset to be added to the temperature reading of CPU.
6.6.15 Configuration Register ⎯ Index 0Fh
Bit
Name
R/W Default
Description
7-6
Reserved
-
0
Reserved.
5
Reserved
R/W
1
Dummy Register
4-2
Reserved
-
0
Reserved.
1-0
DIG_RATE_SEL
R/W
0
Digital temperatures monitoring rate for PECI, AMD TSI, or Intel PCH
SMBus. The rate is calculated by 20Hz/(DIG_RATE_SEL + 1).
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6.6.16 Voltage-Protect Shut Down Enable Register ⎯ Index 10h
Bit
Name
R/W Default
Description
7
Reserved
-
0
Reserved.
6
V6_VP_EN
R/W
0
Voltage-Protect shut down enable for VIN6
5
V5_VP_EN
R/W
0
Voltage-Protect enable for VIN5
4-1
Reserved
-
0
Reserved
0
V0_VP_EN
R/W
0
Voltage-Protect shut down enable for 3VCC
6.6.17 Voltage-Protect Status Register (Powered by VBAT) ⎯ Index 11h
Bit
Name
7-6
Reserved
R/W Default
-
0
Description
Reserved.
This bit is voltage-protect status. Once one of the monitored voltages
0
V_EXC_VP
R/W
C
(3VCC, VIN5, VIN6) over its related over-voltage limits or under its
0
related under-voltage limits and if the related voltage-protect shut
down enable bit is set, this bit will be set to 1. Write a 1 to this bit will
clear it to 0. (This bit is powered by VBAT)
6.6.18 Voltage-Protect Configuration Register (Powered by VBAT) ⎯ Index 12h
Bit
Name
7-4
Reserved
R/W Default
-
-
Description
Reserved.
PSON# de-active time select in alarm mode of voltage protection.
00: PSON# tri-state 0.5 sec and then inverted of S3# when over
voltage or under voltage occurs.
01: PSON# tri-state 1 sec and then inverted of S3# when over voltage
3-2
PU_TIME
R/W
2’h1
or under voltage occurs.
10: PSON# tri-state 2 sec and then inverted of S3# when over voltage
or under voltage occurs.
11: PSON# tri-state 4 sec and then inverted of S3# when over voltage
or under voltage occurs.
VP_EN_DELAY could set the delay time to start voltage protecting
after VDD power is ok when OVP_MODE is 1. (OVP_MODE is
strapped by RTS1# pin)
1-0
VP_EN_DELAY
R/W
2’h2
00: bypass
01: 50ms
10: 100ms
11: 200ms
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6.6.19 Voltage Protection Power Good Select Register ⎯ Index 3Fh
Bit
Name
7-1
Reserved
R/W Default
0
--
Description
Reserved
0: OVP/UVP power good signal is VDD3VOK (VCC3V > 2.8V)
0
OVP_RST_SEL
R/W
0
1: OVP/UVP power good signal is PWROK.
OVP/UVP function wont’ start detecting until power good.
6.6.20 Voltage reading and limit⎯ Index 20h- 37h
Address
Attribute
Default Value
Description
20h
R
--
3VCC reading. The unit of reading is 8mV.
21h
R
--
VIN1 (Vcore) reading. The unit of reading is 8mV.
22h
R
--
VIN2 reading. The unit of reading is 8mV.
23h
R
--
VIN3 reading. The unit of reading is 8mV.
24h
R
--
VIN4 reading. The unit of reading is 8mV.
25h
R
--
VIN5 reading. The unit of reading is 8mV.
26h
R
--
VIN6 reading. The unit of reading is 8mV.
27h
R
--
VSB3V reading. The unit of reading is 8mV.
28h
R
--
VBAT reading. The unit of reading is 8mV.
29h
R
FF
Reserved
2Dh
RO
--
FAN1 present fan duty reading
2Eh
RO
--
FAN2 present fan duty reading
2Fh
RO
--
FAN3 present fan duty reading
30h
R/W
7A
31h
R/W
D7
32~35h
R
FF
36h
R/W
C9
37h
R/W
C8
38h
R/W
75
39h
R/W
85
3Fh
W
00
3VCC under-voltage limit (V0_UVV_LIMIT). The unit is 9mv (This
byte is powered by VBAT)
3VCC over-voltage limit (V0_OVV_LIMIT). The unit is 9mv. (This byte
is powered by VBAT.)
Reserved
VIN5 over-voltage limit (V5_OVV_LIMIT). The unit is 9mv. (This byte
is powered by VBAT.)
VIN6 over-voltage limit (V6_OVV_LIMIT). The unit is 9mv. (This byte
is powered by VBAT.)
VIN5 under-voltage limit (V5_UVV_LIMIT). The unit is 9mv (This byte
is powered by VBAT)
VIN6 under-voltage limit (V6_UVV_LIMIT). The unit is 9mv (This byte
is powered by VBAT)
Write bit 0 to “1” to select OVP start monitor after PWROK ready.
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PECI 3.0 Command and Register
6.6.21 PECI Configuration Register ⎯ Index 40h
Bit
Name
R/W Default
Description
RDIAMSR_CMD_E
When PECI temperature monitoring is enabled, set this bit 1 will
R/W
0
7
N
generate a RdIAMSR() command before a GetTemp() command.
If RDIAMSR_CMD_EN is not set to 1, the temperature data is not
6 C3_UPDATE_EN R/W
0
allowed to be updated when the completion code of RdIAMSR() is
0x82.
5-4
Reserved
R
Reserved
Set this bit 1 to enable updateing positive value of temperature if the
3
C3_PTEMP_EN R/W
0
completion code of RdIAMSR() is 0x82.
Set this bit 1 to enable updating positive value of temperature if the
2
C0_PTEMP_EN R/W
0
completion code of RdIAMSR() is not 0x82 and the bit 8 of
completion code is not 1 either.
Set this bit 1 to enable updating temperature value 0x0000 if the
1
C3_ALL0_EN
R/W
0
completion code of RdIAMSR() is 0x82.
Set this bit 1 to enable updating temperature value 0x0000 if the
0
C0_ALL0_EN
R/W
0
completion code of RdIAMSR() is not 0x82 and the bit 8 of
completion code is not 1 either.
6.6.22 PECI Master Control Register ⎯ Index 41h
Bit
Name
PECI_CMD_STAR
7
T
6-5
Reserved
R/W
Default
W
-
R
-
Description
Write 1 to this bit to start a PECI command when using as a PECI
master. (PECI_PENDING must be set to 1)
Reserved
4
PECI_PENDING
R/W
0
Set this bit 1 to stop monitoring PECI temperature.
3
Reserved
R
-
2-0
PECI_CMD
R/W
3’h0
Reserved
PECI command to be used by PECI master.
000: PING()
001: GetDIB()
010: GetTemp()
011: RdIAMSR()
100: RdPkgConfig()
101: WrPkgConfig()
others: Reserved
6.6.23 PECI Master Status Register ⎯ Index 42h
Bit
Name
7-3
Reserved
2
ABORT_FCS
1
PECI_FCS_ERR
0
PECI_FINISH
R/W Default
R
R/W
C
R/W
C
R/W
C
-
Description
Reserved
This bit is the Abort FCS status of PECI master commands. Write
this bit 1 or read this byte will clear this bit to 0.
This bit is the FCS error status of PECI master commands. Write this
bit 1 or read this byte will clear this bit to 0.
This bit is the Command Finish status of PECI master commands.
Write this bit 1 or read this byte will clear this bit to 0.
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6.6.24 PECI Master DATA0 Register ⎯ Index 43h
Bit
Name
7-0
PECI_DATA0
R/W Default
R/W
0
Description
For RdIAMSR(), RdPkgConfig() and WrPkgConfig() command, this
byte represents “Host ID[7:1] & Retry[0]”. Please refer to PECI
interface specification for more detail.
6.6.25 PECI Master DATA1 Register ⎯ Index 44h
Bit
Name
7-0
PECI_DATA1
R/W Default
R/W
0
Description
For RdIAMSR() , this byte represents “Processor ID”.
For RdPkgConfig() and WrPkgConfig() , this byte represents “Index”.
Please refer to PECI interface specification for more detail.
6.6.26 PECI Master DATA2 Register ⎯ Index 45h
Bit
Name
7-0
PECI_DATA2
R/W Default
R/W
0
Description
For RdIAMSR(), this byte is the least significant byte of “MSR
Address”.
For RdPkgConfig() and WrPkgConfig(), this byte is the least
significant byte of “Parameter”.
Please refer to PECI interface specification for more detail.
6.6.27 PECI Master DATA3 Register ⎯ Index 46h
Bit
Name
7-0
PECI_DATA3
R/W Default
R/W
0
Description
For RdIAMSR(), this byte is the most significant byte of “MSR
Address”.
For RdPkgConfig() and WrPkgConfig(), this byte is the most
significant byte of “Parameter”.
Please refer to PECI interface specification for more detail.
6.6.28 PECI Master DATA4 Register ⎯ Index 47h
Bit
Name
7-0
PECI_DATA4
R/W Default
R/W
0
Description
For GetDIB() , this byte represents “Device Info”
For GetTemp(), this byte represents the least significant byte of
temperature.
For RdIAMSR() and RdPkgConfig() , this byte is “Completion Code”.
For WrPkgConfig(), this byte represents “DATA[7:0]”
6.6.29 PECI Master DATA5 Register ⎯ Index 48h
Bit
Name
7-0
PECI_DATA5
R/W Default
R/W
0
Description
For GetDIB() , this byte represents “Revision Number”
For GetTemp(), this byte represents the most significant byte of
temperature.
For RdIAMSR() and RdPkgConfig() , this byte represents
“DATA[7:0]”
For WrPkgConfig(), this byte represents “DATA[15:8]”
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6.6.30 PECI Master DATA6 Register ⎯ Index 49h
Bit
Name
7-0
PECI_DATA6
R/W Default
R/W
0
Description
RdPkgConfig() ,
For RdIAMSR() and
this byte
“DATA[15:8]”.
For WrPkgConfig(), this byte represents “DATA[23:16]”
represents
6.6.31 PECI Master DATA7 Register ⎯ Index 4Ah
Bit
Name
7-0
PECI_DATA7
R/W Default
R/W
0
Description
For RdIAMSR() and RdPkgConfig() , this byte
“DATA[23:16]”.
For WrPkgConfig(), this byte represents “DATA[31:24]”
represents
6.6.32 PECI Master DATA8 Register ⎯ Index 4Bh
Bit
Name
7-0
PECI_DATA8
R/W Default
R/W
0
Description
RdPkgConfig() ,
For RdIAMSR() and
this byte
“DATA[31:24]”.
For WrPkgConfig(), this byte represents “AW FCS”
represents
6.6.33 PECI Master DATA9 Register ⎯ Index 4Ch
Bit
Name
7-0
PECI_DATA9
R/W Default
R/W
0
Description
For RdIAMSR(), this byte represents “DATA[39:32]”.
For WrPkgConfig(), this byte represents “Completion Code”
6.6.34 PECI Master DATA10 Register ⎯ Index 4Dh
Bit
Name
7-0
PECI_DATA10
R/W Default
R/W
0
Description
For RdIAMSR(), this byte represents “DATA[47:40]”.
6.6.35 PECI Master DATA11 Register ⎯ Index 4Eh
Bit
Name
7-0
PECI_DATA11
R/W Default
R/W
0
Description
For RdIAMSR(), this byte represents “DATA[55:48]”.
6.6.36 PECI Master DATA12 Register ⎯ Index 4Fh
Bit
Name
7-0
PECI_DATA12
R/W Default
R/W
0
Description
For RdIAMSR(), this byte represents “DATA[63:56]”.
Temperature Setting
6.6.37 Temperature PME# Enable Register ⎯ Index 60h
Bit
Name
R/W Default
7
EN_ T3_OVT_PME R/W
0
6
EN_ T2_OVT_PME R/W
0
Description
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds
OVT limit setting.
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds
OVT setting.
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5
4
EN_ T1_OVT_PME R/W
R/W
0
3
EN_ T3_EXC_PME R/W
0
2
EN_ T2_EXC_PME R/W
0
1
EN_ T1_EXC_PME R/W
0
0
Reserved
0
Reserved
R/W
0
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds
OVT setting.
Reserved
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds
high limit setting.
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds
high limit setting.
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds
high limit setting.
Reserved
6.6.38 Temperature Interrupt Status Register ⎯ Index 61h
Bit
Name
R/W Default
Description
This bit gets 1 to indicate TEMP3 temperature sensor has exceeded
7
T3_OVT_STS
R/W
0
OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this
bit, and write 0 to ignore.
This bit gets 1 to indicate TEMP2 temperature sensor has exceeded
6
T2_OVT _STS
R/W
0
OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this
bit, write 0 to ignore.
This bit gets 1 to indicate TEMP1 temperature sensor has exceeded
5
T1_OVT _STS
R/W
0
OVT limit or below the “OVT limit –hysteresis”. Write 1 to clear this
bit, write 0 to ignore.
4
Reserved
R/W
0
Reserved
This bit gets 1 to indicate TEMP3 temperature sensor has exceeded
3
T3_EXC _STS
R/W
0
high limit or below the “high limit –hysteresis”. Write 1 to clear this
bit, write 0 to ignore.
This bit gets 1 to indicate TEMP2 temperature sensor has exceeded
2
T2_EXC _STS
R/W
0
high limit or below the “high limit –hysteresis” limit. Write 1 to clear
this bit, write 0 to ignore.
This bit gets 1 to indicate TEMP1 temperature sensor has exceeded
1
T1_EXC _STS
R/W
0
high limit or below the “high limit –hysteresis” limit. Write 1 to clear
this bit, write 0 to ignore.
0
Reserved
R/W
0
Reserved
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6.6.39 Temperature Real Time Status Register ⎯ Index 62h
Bit
Name
R/W Default
7
T3_OVT
R/W
0
6
T2_OVT
R/W
0
5
T1_OVT
R/W
0
4
Reserved
R/W
0
3
T3_EXC
R/W
0
2
T2_EXC
R/W
0
1
T1_EXC
R/W
0
0
Reserved
R/W
0
Description
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3
is below the “OVT limit –hysteresis” temperature.
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2
is below the “OVT limit –hysteresis” temperature.
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1
is below the “OVT limit –hysteresis” temperature.
Reserved
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3
is below the “high limit –hysteresis” temperature.
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2
is below the “high limit –hysteresis” temperature.
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1
is below the “high limit –hysteresis” temperature.
Reserved
6.6.40 Temperature BEEP Enable Register ⎯ Index 63h
Bit
7
6
5
4
3
2
1
0
Name
EN_T3_
OVT_BEEP
EN_ T2_
OVT_BEEP
EN_ T1_
OVT_BEEP
Reserved
EN_
T3_EXC_BEEP
EN_
T2_EXC_BEEP
EN_
T1_EXC_BEEP
Reserved
R/W Default
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Description
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds
OVT limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds
OVT limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds
OVT limit setting.
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds
high limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds
high limit setting.
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds
high limit setting.
Reserved
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6.6.41 T1 OVT and High Limit Temperature Select Register ⎯ Index 64h
Bit
Name
7-6
Reserved
R/W Default
R/W
0
Description
Reserved
Select the source temperature for T1 OVT Limit.
0: Select T1 to be compared to Temperature 1 OVT Limit.
1: Select CPU temperature from PECI to be compared to
5-4
OVT_TEMP_SEL R/W
0
Temperature 1 OVT Limit.
2: Select CPU temperature from AMD TSI or Intel PCH SMBus to be
compared to Temperature 1 OVT Limit.
3: Select the MAX temperature from Intel PCH SMBus to be
compared to Temperature 1 OVT Limit.
3-2
Reserved
R/W
0
Reserved
Select the source temperature for T1 High Limit.
0: Select T1 to be compared to Temperature 1 High Limit.
1: Select CPU temperature from PECI to be compared to
1-0 HIGH_ TEMP_SEL R/W
0
Temperature 1 High Limit.
2: Select CPU temperature from AMD TSI or Intel PCH SMBus to be
compared to Temperature 1 High Limit.
3: Select the MAX temperature from Intel PCH SMBus to be
compared to Temperature 1 High Limit.
6.6.42 OVT and Alert Output Enable Register 1 ⎯ Index 66h
Bit
Name
R/W Default
Description
7
EN_T3_ALERT
R
0
6
EN_T2_ALERT
R
0
5
EN_T1_ALERT
R
0
4
Reserved
R
0
Reserved.
3
EN_T3_OVT
R/W
0
Enable over temperature (OVT) mechanism of temperature3.
2
EN_T2_OVT
R/W
0
Enable over temperature (OVT) mechanism of temperature2.
1
EN_T1_OVT
R/W
1
Enable over temperature (OVT) mechanism of temperature1.
0
Reserved
R
0h
Reserved.
Enable temperature 3 alert event (asserted when temperature over
high limit)
Enable temperature 2 alert event (asserted when temperature over
high limit)
Enable temperature 1 alert event (asserted when temperature over
high limit)
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6.6.43 Reserved ⎯Index 67~69h
Bit
Name
7-0
Reserved
R/W Default
-
-
Description
Reserved
6.6.44 Temperature Sensor Type Register ⎯ Index 6Bh
Bit
Name
R/W Default
7-4
Reserved
RO
0
3
T3_MODE
R/W
1
2
T2_MODE
R/W
1
1
T1_MODE
R/W
1
0
Reserved
R
0
Description
Reserved
0: TEMP3 is connected to a thermistor
1: TEMP3 is connected to a BJT.(default)
0: TEMP2 is connected to a thermistor.
1: TEMP2 is connected to a BJT. (default)
0: TEMP1 is connected to a thermistor
1: TEMP1 is connected to a BJT.(default)
Reserved
6.6.45 TEMP1 Limit Hystersis Select Register ⎯ Index 6Ch
Bit
Name
R/W Default
7-4
TEMP1_HYS
R/W
4h
3-0
Reserved
R
0h
Description
Limit hysteresis. (0~15 degree C)
Temperature and below the (boundary – hysteresis ).
Reserved
6.6.46 TEMP2 and TEMP3 Limit Hystersis Select Register ⎯ Index 6Dh
Bit
Name
R/W Default
7-4
TEMP3_HYS
R/W
2h
3-0
TEMP2_HYS
R/W
4h
Description
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
6.6.47 DIODE OPEN Status Register ⎯ Index 6Fh
Bit
Name
R/W Default
Description
7-6
Reserved
R
-
5
PECI_OPEN
R
-
4
TSI_OPEN
R
-
3
T3_DIODE_OPEN
R
-
“1” indicates external diode 3 is open
2
T2_DIODE_OPEN
R
-
“1” indicates external diode 2 is open or short
Reserved
When PECI interface is enabled, “1” indicates an error code (0x0080
or 0x0081) is received from PECI slave.
When TSI interface is enabled, “1” indicates the error of not receiving
NACK bit or a timeout occurred.
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T1_DIODE_OPEN
R
-
“1” indicates external diode 1 is open or short
0
Reserved
R
-
Reserved
6.6.48 Temperature ⎯ Index 70h- 8Dh
Address
Attribute
Default Value
Description
70h
Reserved
FFh
Reserved
71h
Reserved
FFh
Reserved
72h
R
--
73h
R
--
74h
R
--
75h
R
--
76h
R
--
77-79h
R
--
7Ah
R
--
7Bh
R
--
7Ch
R
--
Temperature 1 reading. The unit of reading is 1ºC.At the moment
of reading this register.
Reserved
Temperature 2 reading. The unit of reading is 1ºC.At the moment
of reading this register.
Reserved
Temperature 3 reading. The unit of reading is 1ºC.At the moment
of reading this register.
Reserved
The data of CPU temperature from digital interface after IIR filter.
(Available if Intel IBX or AMD TSI interface is enabled)
The raw data of PCH temperature from digital interface. (Only
available if Intel IBX interface is enabled)
The raw data of MCH read from digital interface. (Only available if
Intel IBX interface is enabled)
The raw data of maximum temperature between CPU/PCH/MCH
7Dh
R
--
from digital interface. (Only available if Intel IBX interface is
enabled)
The data of CPU temperature from digital interface after IIR filter.
7Eh
R
--
7Fh
Reserved
FFh
Reserved
80h
Reserved
FFh
Reserved
81h
Reserved
FFh
Reserved
82h
R/W
64h
Temperature sensor 1 OVT limit. The unit is 1ºC.
83h
R/W
55h
Temperature sensor 1 high limit. The unit is 1ºC.
84h
R/W
64h
Temperature sensor 2 OVT limit. The unit is 1ºC.
85h
R/W
55h
Temperature sensor 2 high limit. The unit is 1ºC.
86h
R/W
55h
Temperature sensor 3 OVT limit. The unit is 1ºC.
(Only available if PECI interface is enabled)
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87h
R/W
46h
Temperature sensor 3 high limit. The unit is 1ºC.
88-8Bh
R
--
Reserved
8C~8Dh
R
FFH
Reserved
6.6.49 Temperature Filter Select Register ⎯Index 8Eh
Bit
Name
R/W Default
Description
The queue time for second filter to quickly update values.
00: 8 times.
7-6
IIR-QUEUR3
R/W
1h
01: 12 times.
10: 16 times. (default)
11: 24 times.
The queue time for second filter to quickly update values.
00: 8 times.
5-4
IIR-QUEUR2
R/W
1h
01: 12 times.
10: 16 times. (default)
11: 24 times.
The queue time for second filter to quickly update values.
00: 8 timers.
3-2
IIR-QUEUR1
R/W
1h
01: 12 times.
10: 16 times. (default)
11: 24 times.
The queue time for second filter to quickly update values. (for CPU
temperature from PECI or TSI interface)
1-0
IIR-QUEUR_DIG
R/W
1h
00: 8 timers.
01: 12 times.
10: 16 times. (default)
11: 24 times.
Fan Control Setting
6.6.50 FAN PME# Enable Register ⎯ Index 90h
Bit
Name
7-3
Reserved
R/W Default
R
0
Description
Reserved
A one enables the corresponding interrupt status bit for PME#
2
EN_FAN3_PME
R/W
0
interrupt
Set this bit 1 to enable PME# function for Fan3.
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A one enables the corresponding interrupt status bit for PME#
1
EN_FAN2_PME
R/W
0
interrupt.
Set this bit 1 to enable PME# function for Fan2.
A one enables the corresponding interrupt status bit for PME#
0
EN_FAN1_PME
R/W
0
interrupt.
Set this bit 1 to enable PME# function for Fan1.
6.6.51 FAN Interrupt Status Register ⎯ Index 91h
Bit
Name
7-3
Reserved
2
R/W Default
R
0
FAN3_STS
R/W
--
1
FAN2_STS
R/W
--
0
FAN1_STS
R/W
--
Description
Reserved
This bit is set when the fan3 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit is set when the fan2 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit is set when the fan1 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
6.6.52 FAN Real Time Status Register ⎯ Index 92h
Bit
Name
7-3
Reserved
R/W Default
--
0
Description
Reserved
This bit set to high mean that fan3 count can’t meet expect count over
2
FAN3_EXC
R
--
than SMI time(CR9F) or when duty not zero but fan stop over then 3
sec.
This bit set to high mean that fan2 count can’t meet expect count over
1
FAN2_EXC
R
--
than SMI time(CR9F) or when duty not zero but fan stop over then 3
sec.
This bit set to high mean that fan1 count can’t meet expect count over
0
FAN1_EXC
R
--
than SMI time(CR9F) or when duty not zero but fan stop over then 3
sec.
6.6.53 FAN BEEP# Enable Register ⎯ Index 93h
Bit
7
6
Name
FULL_WITH_
T3_EN
FULL_WITH_
T2_EN
R/W Default
Description
R/W
0
Set one will enable FAN to force full speed when T3 over high limit.
R/W
0
Set one will enable FAN to force full speed when T2 over high limit.
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5
FULL_WITH_
T1_EN
R/W
0
Set one will enable FAN to force full speed when T1 over high limit.
4
Reserved
-
-
Reserved
3
Reserved
-
-
Reserved.
2
EN_FAN3_ BEEP R/W
0
A one enables the corresponding interrupt status bit for BEEP.
1
EN_FAN2_ BEEP R/W
0
A one enables the corresponding interrupt status bit for BEEP.
0
EN_FAN1_ BEEP R/W
0
A one enables the corresponding interrupt status bit for BEEP.
6.6.54 FAN Type Select Register ⎯ Index 94h
FAN_PROG_SEL = 0
Bit
Name
7-6
Reserved
R/W Default
-
-
Description
Reserved.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s
power terminal.
5-4
FAN3_TYPE
R/W 2’b 0S
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
Bit 0 is power on trap by FANCTRL3
0: FANCTRL3 is pull up by external resistor.
1: FANCTRL3 is pull down by internal 100K resistor.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s
power terminal.
3-2
FAN2_TYPE
R/W 2’b 0S
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
Bit 0 is power on trap by FANCTRL2
0: FANCTRL2 is pull up by external resistor.
1: FANCTRL2 is pull down by internal 100K resistor.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s
power terminal.
1-0
FAN1_TYPE
R/W 2’b 0S
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
Bit 0 is power on trap by FANCTRL1
0: FANCTRL1 is pull up by external resistor.
1: FANCTRL1is pull down by internal 100K resistor.
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S: Register default values are decided by trapping.
FAN_PROG_SEL = 1
Bit
Name
R/W Default
Description
This register is used to set the base temperature for FAN1
temperature adjustment.
The FAN1 temperature is calculated according to the equation:
7-0
FAN1_BASE
_TEMP
Tfan1 = Tnow + (Ta – Tb)*Ct
R/W
0
Where Tnow is selected by FAN1_TEMP_SEL_DIG and
FAN1_TEMP_SEL.
Tb is this register, Ta is selected by TFAN1_ADJ_SEL and Ct is
selected by TFAN1_ADJ_UP_RATE/TFAN1_ADJ_DN_RATE.
To access this register, FAN_PROG_SEL(CR9F[7]) must set to “1”.
6.6.55 FAN1 Temperature Adjust Rate Register ⎯ Index 95h (FAN_PROG_SEL = 1)
Bit
Name
7
Reserved
R/W Default
-
-
Description
Reserved
This selects the weighting of the difference between Ta and Tb if Ta is
higher than Tb.
3’h1: 1 (Ct = 1)
6-4
TFAN1_ADJ_UP
3’h0
_RATE
3’h2: 1/2 (Ct= 1/2)
3’h3: 1/4 (Ct = 1/4)
3’h4: 1/8 (Ct = 1/8)
otherwise: 0
To access this byte, FAN_PROG_SEL must set to “1”.
3
Reserved
-
-
Reserved
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This selects the weighting of the difference between Ta and Tb if Ta is
lower than Tb.
3’h1: 1 (Ct = 1)
2-0
TFAN1_ADJ_DN
_RATE
R/W
3’h0
3’h2: 1/2 (Ct= 1/2)
3’h3: 1/4 (Ct = 1/4)
3’h4: 1/8 (Ct = 1/8)
otherwise: 0
To access this byte, FAN_PROG_SEL must set to “1”.
6.6.56 FAN mode Select Register ⎯ Index 96h
FAN_PROG_SEL = 0
Bit
Name
7-6
Reserved
R/W Default
-
-
Description
Reserved
00: Auto fan speed control. Fan speed will follow different temperature
by different RPM defined in 0xC6-0xCE.
01: Auto fan speed control. Fan speed will follow different temperature
by different duty cycle defined in 0xC6-0xCE.
5-4
FAN3_MODE
R/W
01
10: Manual mode fan control. User can write expected RPM count to
0xC2-0xC3, and F71869A will adjust duty cycle (PWM fan type) or
voltage (linear fan type) to control fan speed automatically.
11: Manual mode fan control. User can write expected duty cycle
(PWM fan type) or voltage (linear fan type) to 0xC3, and F71869A will
output this desired duty or voltage to control fan speed.
00: Auto fan speed control. Fan speed will follow different temperature
by different RPM defined in 0xB6-0xBE.
01: Auto fan speed control. Fan speed will follow different temperature
by different duty cycle (voltage) defined in 0xB6-0xBE.
3-2
FAN2_MODE
R/W
01
10: Manual mode fan control. User can write expected RPM count to
0xB2-0xB3, and F71869A will adjust duty cycle (PWM fan type) or
voltage (linear fan type) to control fan speed automatically.
11: Manual mode fan control, user can write expected duty cycle
(PWM fan type) or voltage (linear fan type) to 0xB3, and F71869A will
output this desired duty or voltage to control fan speed.
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00: Auto fan speed control. Fan speed will follow different temperature
by different RPM defined in 0xA6-0xAE.
01: Auto fan speed control. Fan speed will follow different temperature
by different duty cycle defined in 0xA6-0xAE.
1-0
FAN1_MODE
R/W
01
10: Manual mode fan control, user can write expected RPM count to
0xA2-0xA3, and F71869A will auto control duty cycle (PWM fan type)
or voltage (linear fan type) to control fan speed automatically.
11: Manual mode fan control, user can write expected duty cycle
(PWM fan type) or voltage (linear fan type) to 0xA3, and F71869A will
output this desired duty or voltage to control fan speed.
FAN_PROG_SEL = 1
Bit
Name
7-3
Reserved
R/W Default
-
-
Description
Reserved
This selects which temperature to be used as Ta for Fan1 temperature
adjustment.
000: PECI (CR7Eh)
001: T1 (CR72h)
010: T2 (CR74h)
2-0
TFAN1_ADJ_SEL
R/W
0h
011: T3 (CR76h)
100: Digital T1 (CR7Ah)
101: Digital T1 (CR7Bh)
110: Digital T2 (CR7Ch)
111: Digital T3 (CR7Dh)
otherwise: Ta will be 0.
To access this register FAN_PROG_SEL must set to “1”.
6.6.57 Auto FAN1 and FAN2 Boundary Hystersis Select Register ⎯ Index 98h
Bit
Name
R/W Default
Description
Boundary hysteresis. (0~15 degree C)
7-4
FAN2_HYS
R/W
4h
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
Boundary hysteresis. (0~15 degree C)
3-0
FAN1_HYS
R/W
4h
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
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6.6.58 Auto FAN3 Boundary Hystersis Select Register ⎯ Index 99h
Bit
Name
7-4
Reserved
R/W Default
-
-
Description
Reserved.
Boundary hysteresis. (0~15 degree C)
3-0
FAN3_HYS
R/W
2h
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
6.6.59 Fan3 Control Register ⎯ Index 9Ah
Bit
Name
7
Reserved
R/W Default
-
-
Description
Reserved.
This bit and FAN3_PWM_FREQ_SEL are used to select FAN3 PWM
frequency. NEW_FREQ_SEL3 = { FREQ_SEL_ADD3,
FAN3_PWM_FREQ_SEL}
6
FREQ_SEL_ADD3 R/W
0
00: 23.5 KHz
01: 220 Hz
10: 11.75 KHz
11: 5.875 KHz
This bit and FAN2_PWM_FREQ_SEL are used to select FAN2 PWM
frequency. NEW_FREQ_SEL2 = { FREQ_SEL_ADD2,
FAN2_PWM_FREQ_SEL}
5
FREQ_SEL_ADD2 R/W
0
00: 23.5 KHz
01: 220 Hz
10: 11.75 KHz
11: 5.875 KHz
This bit and FAN1_PWM_FREQ_SEL are used to select FAN1 PWM
frequency. NEW_FREQ_SEL1 = { FREQ_SEL_ADD1,
FAN1_PWM_FREQ_SEL}
4
FREQ_SEL_ADD1 R/W
0
00: 23.5 KHz
01: 220 Hz
10: 11.75 KHz
11: 5.875 KHz
3-2
Reserved
R/W
0
Reserved (Keep the value of these two bits “0”)
1
Reserved
R/W
1
Reserved (Keep the value of this bit “1”)
0
FAN3_EXT_EN
R/W
0
Set this bit 1 to enable the function that FAN3 output duty could be
adjusted by GPIO53/GPIO54.
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6.6.60 Auto Fan Up Speed Update Rate Select Register⎯ Index 9Bh
FAN_PROG_SEL = 0
Bit
Name
7-6
Reserved
R/W Default
-
-
Description
Reserved.
Fan3 duty update rate:
00: 2Hz
5-4
FAN3_UP_RATE
R/W
01
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan2 duty update rate:
00: 2Hz
3-2
FAN2_UP_RATE
R/W
01
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan1 duty update rate:
00: 2Hz
1-0
FAN1_UP_RATE
R/W
01
01: 5Hz (default)
10: 10Hz
11: 20Hz
FAN_PROG_SEL = 1
Bit
Name
R/W Default
7
UP_DN_RATE_EN
R/W
0
6
DIRECT_LOAD_EN
R/W
0
Description
0: Fan down rate disable
1: Fan down rate enable
0: Direct load disable
1: Direct load enable for manual duty mode
Fan3 duty update rate:
00: 2Hz
5-4
FAN3_DN_RATE
R/W
01
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan2 duty update rate:
00: 2Hz
3-2
FAN2_DN_RATE
R/W
01
01: 5Hz (default)
10: 10Hz
11: 20Hz
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Fan1 duty update rate:
00: 2Hz
1-0
FAN1_DN_RATE
R/W
01
01: 5Hz (default)
10: 10Hz
11: 20Hz
6.6.61 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Ch
Bit
Name
R/W Default
Description
When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this
7-4
FAN2_STOP
_DUTY
R/W
5h
(value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this
(value x 4).
When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to
3-0
FAN1_STOP
_DUTY
R/W
5h
this (value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this
(value x 4).
6.6.62 FAN3 START UP DUTY-CYCLE/VOLTAGE ⎯ Index 9Dh
Bit
Name
7-4
Reserved
R/W Default
-
-
Description
Reserved.
When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to
3-0
FAN3_STOP_
DUTY
R/W
5h
this (value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this
(value x 4).
6.6.63 FAN PROGRAMMABLE DUTY-CYCLE/VOLTAGE LOADED AFTER POWER-ON ⎯ Index 9Eh
Bit
Name
R/W Default
7-0 PROG_DUTY_VAL R/W
66h
Description
This byte will be immediately loaded as Fan duty value after VDD is
powered on if it has been programmed before shut down.
6.6.64 Fan Fault Time Register ⎯ Index 9Fh
Bit
7
6
Name
R/W Default
FAN_PROG_SEL R/W
FAN_MNT_SEL
R/W
Description
0
Set this bit to “1” will enable accessing registers of other bank.
0
Set this bit to monitor a slower fan.
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5
Reserved
-
-
Reserved
0: The Fan Duty is 100% and will be loaded immediately after VDD is
powered on if CR9E is not been programmed before shut down. (pull
down by external resistor)
4
FULL_DUTY_SEL R/W
-
1: The Fan Duty is 40% and will be loaded immediately after VDD is
powered on if CR9E is not been programmed before shut down. (pull
up by internal 47K resistor).
This register is power on trap by DTR1#.
This register determines the time of fan fault. The condition to cause
fan fault event is:
When PWM_Duty reaches FFh, if the fan speed count can’t reach the
fan expect count in time.
3-0
F_FAULT_TIME
R/W
Ah
The unit of this register is 1 second. The default value is 11 seconds.
(Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
Another condition to cause fan fault event is fan stop and the PWM
duty is greater than the minimum duty programmed by the register
index 9C-9Dh.
6.6.65 FAN1 Index A0h~AFh
Address
Attribute
Default Value
Description
FAN1 count reading (MSB). At the moment of reading this register,
A0h
RO
8’h0f
the LSB will be latched. This will prevent from data updating when
reading. To read the fan count correctly, read MSB first and followed
read the LSB.
A1h
RO
8’hff
FAN1 count reading (LSB).
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (MSB), in auto fan mode (CR96
A2h
R/W
8’h00
bit1Î0) this register is auto updated by hardware.
Duty mode(CR96 bit0=1):
This byte is reserved byte.
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (LSB) or expect PWM duty, in auto
A3h
R/W
8’h01
fan mode this register is auto updated by hardware and read only.
Duty mode(CR96 bit0=1):
The Value programming in this byte is duty value. In auto fan mode
(CR96 bit1Î0) this register is updated by hardware.
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Ex: 5Î 5*100/255 %
255 Î 100%
FAN1 full speed count reading (MSB). At the moment of reading this
A4h
R/W
8’h03
register, the LSB will be latched. This will prevent from data
updating when reading. To read the fan count correctly, read MSB
first and followed read the LSB.
A5h
R/W
8’hff
FAN1 full speed count reading (LSB).
6.6.66 VT1 BOUNDARY 1 TEMPERATURE – Index A6h
Bit
Name
R/W Default
Description
The first boundary temperature for VT1 in temperature mode.
When VT1 temperature exceeds this boundary, expected FAN1 value
7-0
BOUND1TMP1
R/W
3Ch will be loaded from segment 1 register (index AAh).
(60oC) When VT1 temperature is under this boundary – hysteresis, expected
FAN1 value will be loaded from segment 2 register (index ABh).
This byte is a 2’s complement value ranged from -128’C ~ 127’C.
6.6.67 VT1 BOUNDARY 2 TEMPERATURE – Index A7
Bit
7-0
Name
BOUND2TMP1
R/W Defaul
t
Description
The 2nd BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expected
32 value will load from segment 2 register (index ABh).
R/W
(50ºC) When VT1 temperature is below this boundary – hysteresis, FAN1
expected value will load from segment 3 register (index ACh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC.
6.6.68 VT1 BOUNDARY 3 TEMPERATURE – Index A8h
Bit
7-0
Name
BOUND3TMP1
R/W Defaul
t
Description
The 3rd BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expected
28h value will load from segment 3 register (index ACh).
R/W
(40ºC) When VT1 temperature is below this boundary – hysteresis, FAN1
expected value will load from segment 4 register (index ADh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC.
6.6.69 VT1 BOUNDARY 4 TEMPERATURE – Index A9
Bit
Name
R/W Defaul
t
Description
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7-0
BOUND4TMP1
The 4th BOUNDARY temperature for VT1 in temperature mode.
When VT1 temperature is exceed this boundary, FAN1 expected
1Eh value will load from segment 4 register (index ADh).
R/W
(30ºC) When VT1 temperature is below this boundary – hysteresis, FAN1
expected value will load from segment 5 register (index AEh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC.
6.6.70 FAN1 SEGMENT 1 SPEED COUNT – Index AAh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the FAN1_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
7-0
SEC1SPEED1
Ex:
FFh
100%:full speed: User must set this register to 0.
R/W
(100%)
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is ( (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.71 FAN1 SEGMENT 2 SPEED COUNT – Index ABh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the FAN1_MODE(CR96)
7-0
SEC2SPEED1
R/W
2’b00: The value that set in this byte is the relative expect fan speed
D9h
% of the full speed in this temperature section.
(85%)
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.72 FAN1 SEGMENT 3 SPEED COUNT Register – Index ACh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the
FAN1_MODE(CR96)
7-0
SEC3SPEED1
R/W
B2h
(70%)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.73 FAN1 SEGMENT 4 SPEED COUNT Register – Index ADh
Bit
Name
R/W Default
Description
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The meaning of this register is depending on the
FAN1_MODE(CR96)
7-0
2’b00: The value that set in this byte is the relative expect fan speed
99h
(60%)
SEC4SPEED1
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.74 FAN1 SEGMENT 5 SPEED COUNT Register – Index AEh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the
FAN1_MODE(CR96)
7-0
SEC5PEED1
R/W
80h
(50%)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.75 FAN1 Temperature Mapping Select – Index AFh
Bit
7
6
5
Name
FAN1_TEMP
_SEL_DIG
FAN1_PWM
_FREQ_SEL
FAN1_UP_T_EN
R/W Default
R/W
0
Description
This bit companies with FAN1_TEMP_SEL select the temperature
source for controlling FAN1.
Set this bit to select FAN2 PWM output frequency.
R/W
0
0: 23.5 kHz
1: 220 Hz
R/W
0
Set 1 to force FAN1 to full speed if any temperature over its high limit.
INTERPOLATION_ R/W
1
Set 1 will enable the interpolation of the fan expect table.
FAN1_
4
EN
This register controls the FAN1 duty movement when temperature over
highest boundary.
3
FAN1_JUMP
_HIGH_EN
0: The FAN1 duty will increases with the slope selected by
R/W
1
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC1SPEED1
register.
This bit only activates in duty mode.
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This register controls the FAN1 duty movement when temperature
under (highest boundary – hysteresis).
FAN1_JUMP
2
_LOW_EN
0: The FAN1 duty will decreases with the slope selected by
R/W
1
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC2SPEED1
register.
This bit only activates in duty mode.
This registers company with FAN1_TEMP_SEL_DIG select the
temperature source for controlling FAN1. The following value is
comprised by {FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL}
000: fan1 follows PECI temperature (CR7Eh)
001: fan1 follows temperature 1 (CR72h).
1-0
FAN1_TEMP_SEL
R/W
01
010: fan1 follows temperature 2 (CR74h).
011: fan1 follows temperature 3 (CR76h).
100: fan1 follows IBX/TSI CPU temperature (CR7Ah)
101: fan1 follows IBX PCH temperature (CR7Bh).
110: fan1 follows IBX MCH temperature (CR7Ch).
111: fan1 follows IBX maximum temperature (CR7Dh).
Others are reserved.
6.6.76 FAN2 Index B0h~BFh
Address
Attribute
Default Value
Description
FAN2 count reading (MSB). At the moment of reading this register,
B0h
RO
8’h0f
the LSB will be latched. This will prevent from data updating when
reading. To read the fan count correctly, read MSB first and followed
read the LSB.
B1h
RO
8’hff
FAN2 count reading (LSB).
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (MSB), in auto fan mode(CR96
B2h
R/W
8’h00
bit3Î0) this register is auto updated by hardware.
Duty mode(CR96 bit2=1):
This byte is reserved byte.
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (LSB) or expect PWM duty , in auto
B3h
R/W
8’h01
fan mode this register is auto updated by hardware and read only.
Duty mode(CR96 bit2=1):
The Value programming in this byte is duty value. In auto fan
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mode(CR96 bit3Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN2 full speed count reading (MSB). At the moment of reading this
B4h
R/W
8’h03
register, the LSB will be latched. This will prevent from data
updating when reading. To read the fan count correctly, read MSB
first and followed read the LSB.
B5h
R/W
8’hff
FAN2 full speed count reading (LSB).
6.6.77 VT2 BOUNDARY 1 TEMPERATURE – Index B6h
Bit
Name
R/W Default
Description
The first boundary temperature for VT2 in temperature mode.
When VT2 temperature exceeds this boundary, FAN2 expect value
7-0
BOUND1TMP2
R/W
3Ch will load from segment 1 register (index Bah).
(60oC) When VT2 temperature is under this boundary – hysteresis, FAN2
expect value will load from segment 2 register (index BAh).
This byte is a 2’s complement value ranging from -128’C ~ 127’C.
6.6.78 VT2 BOUNDARY 2 TEMPERATURE – Index B7
Bit
Name
7-0
BOUND2TMP2
R/W Default
R/W
Description
The 2nd BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expected
32
value will load from segment 2 register (index BBh).
(50ºC) When VT2 temperature is below this boundary – hysteresis, FAN2
expected value will load from segment 3 register (index BCh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC.
6.6.79 VT2 BOUNDARY 3 TEMPERATURE – Index B8h
Bit
Name
7-0
BOUND3TMP2
R/W Default
R/W
Description
The 3rd BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expected
28h value will load from segment 3 register (index BCh).
(40ºC) When VT2 temperature is below this boundary – hysteresis, FAN2
expected value will load from segment 4 register (index BDh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC.
6.6.80 VT2 BOUNDARY 4 TEMPERATURE – Index B9
Bit
Name
R/W Default
Description
99
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7-0
BOUND4TMP2
R/W
The 4th BOUNDARY temperature for VT2 in temperature mode.
When VT2 temperature is exceed this boundary, FAN2 expected
1Eh value will load from segment 4 register (index BDh).
(30ºC) When VT2 temperature is below this boundary – hysteresis, FAN2
expected value will load from segment 5 register (index BEh).
This byte is a 2’s complement value ranging from -128ºC ~ 127ºC.
6.6.81 FAN2 SEGMENT 1 SPEED COUNT – Index BAh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
7-0
SEC1SPEED2
Ex:
FFh
100%:full speed: User must set this register to 0.
R/W
(100%)
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.82 FAN2 SEGMENT 2 SPEED COUNT – Index BBh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the FAN2_MODE(CR96)
7-0
SEC2SPEED2
R/W
2’b00: The value that set in this byte is the relative expect fan speed
D9h
% of the full speed in this temperature section.
(85%)
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.83 FAN2 SEGMENT 3 SPEED COUNT Register – Index BCh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the
FAN2_MODE(CR96)
7-0
SEC3SPEED2
R/W
B2h
(70%)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.84 FAN2 SEGMENT 4 SPEED COUNT Register – Index BDh
Bit
Name
R/W Default
Description
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The meaning of this register is depending on the
FAN2_MODE(CR96)
7-0
SEC4SPEED2
R/W
99h
(60%)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.85 FAN2 SEGMENT 5 SPEED COUNT Register – Index BEh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the
FAN2_MODE(CR96)
7-0
SEC5PEED2
R/W
80h
(50%)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.86 FAN2 Temperature Mapping Select – Index BFh
Bit
7
6
5
4
Name
FAN2_TEMP_
SEL_DIG
FAN2_PWM_
FREQ_SEL
FAN2_UP_T_EN
FAN2_
INTERPOLATION_EN
R/W Default
R/W
0
Description
This bit companies with FAN2_TEMP_SEL to select the temperature
source for controlling FAN2.
Set this bit to select FAN2 PWM output frequency.
R/W
0
0: 23.5 kHz
1: 220 Hz
R/W
0
Set 1 to force FAN2 to full speed if any temperature over its high limit.
R/W
1
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN2 duty movement when temperature
over highest boundary.
3
FAN2_JUMP_
HIGH_EN
0: The FAN2 duty will increases with the slope selected by
R/W
1
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC1SPEED2
register.
This bit only activates in duty mode.
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This register controls the FAN2 duty movement when temperature
under (highest boundary – hysteresis).
FAN2_JUMP_
2
LOW_EN
0: The FAN2 duty will decreases with the slope selected by
R/W
1
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC2SPEED2
register.
This bit only activates in duty mode.
This registers companying with FAN2_TEMP_SEL_DIG select the
temperature source for controlling FAN2. The following value is
comprised by {FAN2_TEMP_SEL_DIG, FAN2_TEMP_SEL}
000: fan2 follows PECI temperature (CR7Eh)
001: fan2 follows temperature 1 (CR72h).
1-0
FAN2_TEMP_SEL
R/W
10
010: fan2 follows temperature 2 (CR74h).
011: fan2 follows temperature 3 (CR76h).
100: fan2 follows IBEX/TSI CPU temperature (CR7Ah)
101: fan2 follows IBEX PCH temperature (CR7Bh).
110: fan2 follows IBEX MCH temperature (CR7Ch).
111: fan2 follows IBEX maximum temperature (CR7Dh).
Otherwise: reserved.
6.6.87 FAN3 Index C0h- CFh
Address
Attribute
Default Value
Description
FAN3 count reading (MSB). At the moment of reading this register,
C0h
RO
8’h0F
the LSB will be latched. This will prevent from data updating when
reading. To read the fan count correctly, read MSB first and followed
read the LSB.
C1h
RO
8’hff
FAN3 count reading (LSB).
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (MSB), in auto fan mode(CR96
C2h
R/W
8’h00
bit5Î0) this register is auto updated by hardware.
Duty mode(CR96 bit4=1):
This byte is reserved byte.
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (LSB) or expect PWM duty , in auto
C3h
R/W
8’h01
fan mode this register is auto updated by hardware and read only.
Duty mode(CR96 bit4=1):
The Value programming in this byte is duty value. In auto fan
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mode(CR96 bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
FAN3 full speed count reading (MSB). At the moment of reading this
C4h
R/W
8’h03
register, the LSB will be latched. This will prevent from data
updating when reading. To read the fan count correctly, read MSB
first and followed read the LSB.
C5h
R/W
8’hff
FAN3 full speed count reading (LSB).
6.6.88 VT3 BOUNDARY 1 TEMPERATURE – Index C6h
Bit
Name
R/W Default
Description
The first boundary temperature for VT3 in temperature mode.
When VT3 temperature exceeds this boundary, FAN3 expect value
7-0
BOUND1TMP3
R/W
3Ch will load from segment 1 register (index CA)h.
(60oC) When VT3 temperature is under this boundary – hysteresis, FAN3
expect value will load from segment 2 register (index CAh).
This byte is a 2’s complement value ranging from -128’C ~ 127’C.
6.6.89 VT3 BOUNDARY 2 TEMPERATURE – Index C7
Bit
Name
7-0
BOUND2TMP3
R/W Default
R/W
Description
The 2nd BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expected
32
value will load from segment 2 register (index CBh).
(50oC) When VT3 temperature is below this boundary – hysteresis, FAN3
expected value will load from segment 3 register (index CCh).
This byte is a 2’s complement value ranging from -128 oC ~ 127 oC.
6.6.90 VT3 BOUNDARY 3 TEMPERATURE – Index C8h
Bit
Name
7-0
BOUND3TMP3
R/W Default
R/W
Description
The 3rd BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expected
28h value will load from segment 3 register (index CCh).
(40oC) When VT3 temperature is below this boundary – hysteresis, FAN3
expected value will load from segment 4 register (index CDh).
This byte is a 2’s complement value ranging from -128 oC ~ 127 oC.
6.6.91 VT3 BOUNDARY 4 TEMPERATURE – Index C9
Bit
Name
7-0
BOUND4TMP3
R/W Default
R/W
Description
The 4th BOUNDARY temperature for VT3 in temperature mode.
When VT3 temperature is exceed this boundary, FAN3 expected
1Eh value will load from segment 4 register (index CDh).
(30oC) When VT3 temperature is below this boundary – hysteresis, FAN3
expected value will load from segment 5 register (index CEh).
This byte is a 2’s complement value ranging from -128 oC ~ 127 oC.
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6.6.92 FAN3 SEGMENT 1 SPEED COUNT – Index CAh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
7-0
SEC1SPEED3
Ex:
FFh
100%:full speed: User must set this register to 0.
R/W
(100%)
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.93 FAN3 SEGMENT 2 SPEED COUNT – Index CBh
Bit
Name
R/W Default
Description
The meaning of this register is depending on the FAN3_MODE(CR96)
7-0
SEC2SPEED3
R/W
2’b00: The value that set in this byte is the relative expect fan speed
D9h
% of the full speed in this temperature section.
(85%)
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.94 FAN3 SEGMENT 3 SPEED COUNT
Bit
Name
7-0
SEC3SPEED3
R/W Default
R/W
B2h
(70%)
Description
The meaning of this register is depending on the
FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.95 FAN3 SEGMENT 4 SPEED COUNT
Bit
Name
7-0
SEC4SPEED3
R/W Default
R/W
99h
(60%)
Name
– Index CDh
Description
The meaning of this register is depending on the
FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.96 FAN3 SEGMENT 5 SPEED COUNT
Bit
– Index CCh
– Index CEh
R/W Default
Description
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7-0
SEC5SPEED3
R/W
80h
(50%)
The meaning of this register is depending on the
FAN3_MODE(CR96)
2’b00: The value that set in this byte is the relative expect fan speed
% of the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM
duty-cycle in this temperature section.
6.6.97 FAN3 Temperature Mapping Select – Index CFh
Bit
7
6
5
4
Name
FAN3_TEMP_
SEL_DIG
FAN3_PWM_
FREQ_SEL
FAN3_UP_T_EN
FAN3_
INTERPOLATION_EN
R/W Default
R/W
0
Description
This bit companies with FAN3_TEMP_SEL select the temperature
source for controlling FAN3.
Set this bit to select FAN3 PWM output frequency.
R/W
0
0: 23.5 kHz
1: 220 Hz
R/W
0
Set 1 to force FAN3 to full speed if any temperature over its high limit.
R/W
1
Set 1 will enable the interpolation of the fan expect table.
This register controls the FAN3 duty movement when temperature
over highest boundary.
3
FAN3_JUMP_
HIGH_EN
0: The FAN3 duty will increases with the slope selected by
R/W
1
FAN3_RATE_SEL register.
1: The FAN3 duty will directly jumps to the value of SEC1SPEED3
register.
This bit only activates in duty mode.
This register controls the FAN3 duty movement when temperature
under (highest boundary – hysteresis).
2
FAN3_JUMP_
LOW_EN
0: The FAN3 duty will decreases with the slope selected by
R/W
1
FAN3_RATE_SEL register.
1: The FAN3 duty will directly jumps to the value of SEC2SPEED3
register.
This bit only activates in duty mode.
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This registers companying with FAN3_TEMP_SEL_DIG select the
temperature source for controlling FAN3. The following value is
comprised by {FAN3_TEMP_SEL_DIG, FAN3_TEMP_SEL}
000: fan3 follows PECI temperature (CR7Eh)
001: fan3 follows temperature 1 (CR72h).
1-0
FAN3_TEMP_SEL
R/W
11
010: fan3 follows temperature 2 (CR74h).
011: fan3 follows temperature 3 (CR76h).
100: fan3 follows IBEX/TSI CPU temperature (CR7Ah)
101: fan3 follows IBEX PCH temperature (CR7Bh).
110: fan3 follows IBEX MCH temperature (CR7Ch).
111: fan3 follows IBEX maximum temperature (CR7Dh).
Otherwise: reserved.
6.6.98 TSI Temperature 0 – Index E0h
Bit
Name
R/W Default
Description
This is the AMD TSI reading if AMD TSI enable.
TSI_TEMP0
R/W
-
And will be highest temperature among CPU, MCH and PCH if Intel
temperature interface enable. The range is 0~255’C. To access this
byte, MCH_BANK_SEL must set to “0”.
This byte is used as multi-purpose:
1. The received data of receive protocol.
7-0
2. The first received byte of read word protocol.
SMB_DATA0
R/W
8’h00
3. The 10th received byte of read block protocol.
4. The sent data for send byte protocol and write byte protocol.
5. The first send byte for write word protocol.
6. The first send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.99 TSI Temperature 1 – Index E1h
Bit
Name
R/W Default
Description
This is the high byte of Intel temperature interface PCH reading. The
7-0
TSI_TEMP1
R
-
range is 0~255’C.
To access this byte, MCH_BANK_SEL should be set to “0”.
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This byte is used as multi-purpose:
1. The second received byte of read word protocol.
SMB_DATA1
R/W
8’h00
2. The 11th received byte of read block protocol.
3. The second send byte for write word protocol.
4. The second send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.100
Bit
TSI Temperature 2 Low Byte – Index E2h
Name
R/W Default
Description
This is the low byte of Intel temperature interface CPU reading. The
reading is the fraction part of CPU temperature. Bit 0 indicates the
TSI_TEMP2_LO
R
-
7-0
error status.
0: No error.
1: Error code.
To access this byte, MCH_BANK_SEL should be set to “0”.
This is the 12th byte of the block read protocol.
SMB_DATA2
R/W
8’h00 This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.101
Bit
TSI Temperature 2 High Byte – Index E3h
Name
R/W Default
Description
This is the high byte of Intel temperature interface CPU reading. The
TSI_TEMP2_HI
R
-
reading is the decimal part of CPU temperature.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 13th byte of the block read protocol.
SMB_DATA3
R/W
8’h00 This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.102
Bit
TSI Temperature 3 – Index E4h
Name
R/W Default
Description
This is the high byte of Intel temperature interface MCH reading. The
TSI_TEMP3
R
-
range is 0~255’C.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 14th byte of the block read protocol.
SMB_DATA4
R/W
8’h00 This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
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6.6.103
Bit
TSI Temperature 4 – Index E5h
Name
R/W Default
Description
This is the high byte of Intel temperature interface DIMM0 reading.
TSI_TEMP4
R
-
The range is 0~255’C.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 15th byte of the block read protocol.
SMB_DATA5
R/W
8’h00 This byte is also used as the 6th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.104
Bit
TSI Temperature 5 – Index E6h
Name
R/W Default
Description
This is the high byte of Intel temperature interface DIMM1 reading.
TSI_TEMP5
R
-
The range is 0~255’C.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 16th byte of the block read protocol.
SMB_DATA6
R/W
8’h00 This byte is also used as the 7th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.105
Bit
TSI Temperature 6 – Index E7h
Name
R/W Default
Description
This is the high byte of Intel temperature interface DIMM2 reading.
TSI_TEMP6
R
-
The range is 0~255’C.
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 17th byte of the block read protocol.
SMB_DATA7
R/W
8’h00 This byte is also used as the 8th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.106
Bit
TSI Temperature 7 – Index E8h
Name
R/W Default
Description
This is the high byte of Intel temperature interface DIMM3 reading.
TSI_TEMP7
R
-
The range is 0~255’C. The above 9 bytes could also be used as the
read data of block read protocol if the TSI is disable or pending.
7-0
This is the 18th byte of the block read protocol.
SMB_DATA8
R/W
8’h00 This byte is also used as the 9th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.107
Bit
SMB Data Buffer 9 – Index E9h
Name
R/W Default
Description
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th
This is the 18 byte of the block read protocol.
7-0
SMB_DATA9
R/W
FFh
This byte is also used as the 9th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
6.6.108
Block Write Count Register – Index ECh
Bit
Name
7
MCH_BANK_SEL
R/W
0
6
Reserved
-
0
5-0
BLOCK_WR_CNT
R/W
0
6.6.109
Bit
R/W Default
Description
This bit is used to select the register in index E0h to E9h.
Set “0” to read the temperature bank and “1” to access the data bank.
Reserved
Use the register to specify the byte count of block write protocol.
Support up to 10 bytes.
SMB Command Byte/TSI Command Byte – Index EDh
Name
R/W Default
Description
There are actual two bytes for this index. TSI_CMD_PROG select
which byte to be programmed:
0: SMB_CMD, which is the command code for write byte/word, read
7-0
SMB_CMD/TSI_CMD R/W
0/1
byte/word, block write/read and process call protocol.
1: TSI_CMD, which is the command code for Intel temperature
interface block read protocol and the data byte for AMD TSI send byte
protocol.
6.6.110
Bit
SMB Status – Index EEh
Name
R/W Default
Description
Set 1 to pending auto TSI accessing. (In AMD model, auto accessing
7
TSI_PENDING
R/W
0
will issue a send-byte followed a receive-byte; In Intel model, auto
accessing will issue a block read).
To use the SCL/ SDA as a SMBus master, set this bit to “1” first.
6
TSI_CMD_PROG
R/W
0
5
PROC_KILL
R/W
0
4
FAIL_STS
R
0
3
SMB_ABT_ERR
R
0
2
SMB_TO_ERR
R
0
Set 1 to program TSI_CMD.
Kill the current SMBus transfer and return the state machine to idle. It
will set an fail status if the current transfer is not completed.
This is set when PROC_KI LL kill an un-completed transfer. It will be
auto cleared by next SMBus transfer.
This is the arbitration lost status if a SMBus command is issued. Auto
cleared by next SMBus command.
This is the timeout status if a SMBus command is issued. Auto
cleared by next SMBus command.
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1
SMB_NAC_ERR
R
0
0
SMB_READY
R
1
6.6.111
This is the NACK error status if a SMBus command is issued. Auto
cleared by next SMBus command.
0: a SMBus transfer is in process.
1: Ready for next SMBus command.
SMB Protocol Select – Index EFh
Bit
Name
R/W Default
7
SMB_START
W
0
6-4
Reserved
-
-
Description
Write “1” to trigger a SMBus transfer with the protocol specified by
SMB_PROTOCOL.
Reserved.
Select what protocol if a SMBus transfer is triggered.
0001b: send byte.
0010b: write byte.
0011b: write word.
0100b: Reserved.
0101b: block write.
3-0
SMB_PROTOCOL
R/W
0
0111b: quick command (write).
1001b: receive byte.
1010b: read byte.
1011b: read word.
1101b: block read.
1111b: Reserved
Otherwise: reserved.
6.7
KBC Registers (CR05)
6.7.1 KBC Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
KBC_EN
R/W
1
Description
Reserved
0: disable KBC.
1: enable KBC.
6.7.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
00h
Description
The MSB of KBC command port address. The address of data port is
command port address + 4;
6.7.3 Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Default
Description
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7-0
BASE_ADDR_LO R/W
60h
The LSB of KBC command port address. The address of data port is
command port address + 4.
6.7.4 KBC IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELKIRQ
R/W
1h
Description
Reserved.
Select the IRQ channel for keyboard interrupt.
6.7.5 Mouse IRQ Channel Select Register ⎯ Index 72h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELMIRQ
R/W
Ch
Description
Reserved.
Select the IRQ channel for PS/2 mouse interrupt.
6.7.6 Auto Swap Register ⎯ Index FEh (Powered by VBAT)
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
KB_MO_SWAP
R/W
0
0: Keyboard/mouse does not swap.
1: Keyboard/mouse swap.
Users could also program this bit manually.
Set “1” to enable auto response to KBC command. It will return 0xFA, 0xAA
PSEUDO_8408_EN R/W
3
0
for 0xFF command and 0xFA for other commands. This bit is used for GPIO
scan code function without PS/2 keyboard.
2-0
Reserved
-
1h
Reserved
6.7.7 User Wakeup Code Register ⎯ Index FFh (Powered by VBAT)
Bit
9-0
6.8
Name
USER_WAKEUP_
CODE
R/W Default
R/W
29h
Description
User defined wakeup code.
GPIO Registers (CR06)
6.8.1 GPIO Device Enable Register ⎯ Index 30h
Bit
Name
R/W Default
7-1
Reserved
-
-
0
GPIO_EN
R/W
0
Description
Reserved
0: disable GPIO I/O Port.
1: enable GPIO I/O Port.
6.8.2 Base Address High Register ⎯ Index 60h
Bit
Name
R/W Default
Description
111
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BASE_ADDR_HI
6.8.3
Bit
7-0
R/W
The MSB of GPIO index/data port address. The index port is
BASE_ADDR[15:2] + 5 and the data port is BASE_ADDR[15:2] + 6.
Base Address Low Register ⎯ Index 61h
Name
R/W Default
BASE_ADDR_LO R/W
6.8.4
00h
00h
Description
The LSB of GPIO index/data port address. The index port is
BASE_ADDR[15:2] + 5 and the data port is BASE_ADDR[15:2] + 6.
GPIRQ Channel Select Register ⎯ Index 70h
Bit
Name
7-4
Reserved
-
-
Reserved.
3-0
SELGPIRQ
R/W
0h
Select the IRQ channel for GPIO interrupt.
6.8.5
R/W Default
Description
GPIO0 Output Enable Register ⎯ Index F0h
Bit
Name
R/W Default
Description
7-6
Reserved
-
-
Reserved.
5
GPIO05_OE
R/W
0
0: GPIO05 is in input mode.
1: GPIO05 is in output mode.
4
GPIO04_OE
R/W
0
0: GPIO04 is in input mode.
1: GPIO04 is in output mode.
3
GPIO03_OE
R/W
0
0: GPIO03 is in input mode.
1: GPIO03 is in output mode.
2
GPIO02_OE
R/W
0
0: GPIO02 is in input mode.
1: GPIO02 is in output mode.
1
GPIO01_OE
R/W
0
0: GPIO01 is in input mode.
1: GPIO01 is in output mode.
0
Reserved
R/W
0
Reserved
6.8.6
GPIO0 Output Data Register ⎯ Index F1h
Bit
Name
R/W Default
Description
7-6
Reserved
-
-
Reserved.
5
GPIO05_VAL
R/W
1
0: GPIO05 outputs 0 when in output mode.
1: GPIO05 outputs 1 when in output mode.
4
GPIO04_VAL
R/W
1
0: GPIO04 outputs 0 when in output mode.
1: GPIO04 outputs 1 when in output mode.
3
GPIO03_VAL
R/W
1
0: GPIO03 outputs 0 when in output mode.
1: GPIO03 outputs 1 when in output mode.
2
GPIO02_VAL
R/W
1
0: GPIO02 outputs 0 when in output mode.
1: GPIO02 outputs 1 when in output mode.
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GPIO01_VAL
R/W
1
0: GPIO01 outputs 0 when in output mode.
1: GPIO01 outputs 1 when in output mode.
0
Reserved
R/W
1
Reserved
6.8.7
GPIO Pin Status Register ⎯ Index F2h
Bit
Name
7-6
Reserved
-
-
Reserved.
5
GPIO05_IN
R
-
The pin status of S3_Gate#/GPIO05/WDTRST#
4
GPIO04_IN
R
-
The pin status of S3P5_Gate#/SLOTOCC#/GPIO04
3
GPIO03_IN
R
-
The pin status of CIRRX#/GPIO03
2
GPIO02_IN
R
-
The pin status of CIRTX#/GPIO02
1
GPIO01_IN
R
-
The pin status of CIRWB#/GPIO01
0
Reserved
R
-
Reserved
6.8.8
GPIO Drive Enable Register ⎯ Index F3h
Bit
Name
7
Reserved
R/W Default
Description
R/W Default
-
Description
-
Reserved.
5
GPIO05_DRV_EN R/W
0
0: GPIO05 is open drain in output mode.
1: GPIO05 is push pull in output mode.
4
GPIO04_DRV_EN R/W
0
0: GPIO04 is open drain in output mode.
1: GPIO04 is push pull in output mode.
3
GPIO03_DRV_EN R/W
0
0: GPIO03 is open drain in output mode.
1: GPIO03 is push pull in output mode.
2
GPIO02_DRV_EN R/W
0
0: GPIO02 is open drain in output mode.
1: GPIO02 is push pull in output mode.
1
GPIO01_DRV_EN R/W
0
0: GPIO01 is open drain in output mode.
1: GPIO01 is push pull in output mode.
0
Reserved
0
Reserved
R/W
6.8.9
GPIO1 Output Enable Register ⎯ Index E0h
Bit
Name
R/W Default
Description
7
GPIO17_OE
R/W
0
0: GPIO17 is in input mode.
1: GPIO17 is in output mode.
6
GPIO16_OE
R/W
0
0: GPIO16 is in input mode.
1: GPIO16 is in output mode.
5
GPIO15_OE
R/W
0
0: GPIO15 is in input mode.
1: GPIO15 is in output mode.
4
GPIO14_OE
R/W
0
0: GPIO14 is in input mode.
1: GPIO14 is in output mode.
3
GPIO13_OE
R/W
0
0: GPIO13 is in input mode.
1: GPIO13 is in output mode.
2
GPIO12_OE
R/W
0
0: GPIO12 is in input mode.
1: GPIO12 is in output mode.
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GPIO11_OE
R/W
0
0: GPIO11 is in input mode.
1: GPIO11 is in output mode.
0
GPIO10_OE
R/W
0
0: GPIO10 is in input mode.
1: GPIO10 is in output mode.
6.8.10 GPIO1 Output Data Register ⎯ Index E1h
Bit
Name
R/W Default
Description
7
GPIO17_VAL
R/W
1
0: GPIO17 outputs 0 when in output mode.
1: GPIO17 outputs1 when in output mode.
6
GPIO16_VAL
R/W
1
0: GPIO16 outputs 0 when in output mode.
1: GPIO16 outputs1 when in output mode.
5
GPIO15_VAL
R/W
1
0: GPIO15 outputs 0 when in output mode.
1: GPIO15 outputs 1 when in output mode.
4
GPIO14_VAL
R/W
1
0: GPIO14 outputs 0 when in output mode.
1: GPIO14 outputs 1 when in output mode.
3
GPIO13_VAL
R/W
1
0: GPIO13 outputs 0 when in output mode.
1: GPIO13 outputs 1 when in output mode.
2
GPIO12_VAL
R/W
1
0: GPIO12 outputs 0 when in output mode.
1: GPIO12 outputs 1 when in output mode.
1
GPIO11_VAL
R/W
1
0: GPIO11 outputs 0 when in output mode.
1: GPIO11 outputs 1 when in output mode.
0
GPIO10_VAL
R/W
1
0: GPIO10 outputs 0 when in output mode.
1: GPIO10 outputs 1 when in output mode.
6.8.11 GPIO1 Pin Status Register ⎯ Index E2h
Bit
Name
7
GPIO17_IN
R/W Default Description
R
-
The pin status of CPU_PWGD/GPIO17.
6
GPIO16_IN
R
-
The pin status of LED_VCC/GPIO16.
5
GPIO15_IN
R
-
The pin status of LED_VSB/ALERT#/GPIO15.
4
GPIO14_IN
R
-
The pin status of WDTRST#/GPIO14.
3
GPIO13_IN
R
-
The pin status of BEEP/GPIO13.
2
GPIO12_IN
R
-
The pin status of RSTCON#/GPIO12.
1
GPIO11_IN
R
-
The pin status of PCI_RST5#/GPIO11.
0
GPIO10_IN
R
-
The pin status of PCI_RST4#/GPIO10.
6.8.12 GPIO1 Drive Enable Register ⎯ Index E3h
Bit
Name
R/W Default
Description
7
GPIO17_DRV_EN R/W
0
0: GPIO17 is open drain in output mode.
1: GPIO17 is push pull in output mode.
6
GPIO16_DRV_EN R/W
0
0: GPIO16 is open drain in output mode.
1: GPIO16 is push pull in output mode.
5
GPIO15_DRV_EN R/W
0
0: GPIO15 is open drain in output mode.
1: GPIO15 is push pull in output mode.
4
GPIO14_DRV_EN R/W
0
0: GPIO14 is open drain in output mode.
1: GPIO14 is push pull in output mode.
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GPIO13_DRV_EN R/W
0
0: GPIO13 is open drain in output mode.
1: GPIO13 is push pull in output mode.
2
GPIO12_DRV_EN R/W
0
0: GPIO12 is open drain in output mode.
1: GPIO12 is push pull in output mode.
1
GPIO11_DRV_EN R/W
0
0: GPIO11 is open drain in output mode.
1: GPIO11 is push pull in output mode.
0
GPIO10_DRV_EN R/W
0
0: GPIO10 is open drain in output mode.
1: GPIO10 is push pull in output mode.
6.8.13 GPIO1 PME Enable Register ⎯ Index E4h
Bit
Name
R/W Default
Description
7
GPIO17_PME_EN R/W
0
When GPIO17_EVENT_STS is 1 and GPIO17_PME_EN is set to 1, a
GPIO PME event will be generated.
6
GPIO16_PME_EN R/W
0
When GPIO16_EVENT_STS is 1 and GPIO16_PME_EN is set to 1, a
GPIO PME event will be generated.
5
GPIO15_PME_EN R/W
0
When GPIO15_EVENT_STS is 1 and GPIO15_PME_EN is set to 1, a
GPIO PME event will be generated.
4
GPIO14_PME_EN R/W
0
When GPIO14_EVENT_STS is 1 and GPIO14_PME_EN is set to 1, a
GPIO PME event will be generated.
3
GPIO13_PME_EN R/W
0
When GPIO13_EVENT_STS is 1 and GPIO13_PME_EN is set to 1, a
GPIO PME event will be generated.
2
GPIO12_PME_EN R/W
0
When GPIO12_EVENT_STS is 1 and GPIO12_PME_EN is set to 1, a
GPIO PME event will be generated.
1
GPIO11_PME_EN R/W
0
When GPIO11_EVENT_STS is 1 and GPIO11_PME_EN is set to 1, a
GPIO PME event will be generated.
0
GPIO10_PME_EN R/W
0
When GPIO10_EVENT_STS is 1 and GPIO10_PME_EN is set to 1, a
GPIO PME event will be generated.
6.8.14 GPIO1 Input Detection Select Register ⎯ Index E5h
Bit
7
6
5
4
Name
R/W Default
GPIO17_DET_SEL R/W
GPIO16_DET_SEL R/W
GPIO15_DET_SEL R/W
GPIO14_DET_SEL R/W
Description
0
When GPIO17 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO16 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO15 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO14 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
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2
1
0
GPIO13_DET_SEL R/W
GPIO12_DET_SEL R/W
GPIO11_DET_SEL R/W
GPIO10_DET_SEL R/W
0
When GPIO13 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO12 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO11 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO10 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
6.8.15 GPIO1 Event Status Register ⎯ Index E6h
Bit
Name
R/W Default
Description
7
GPIO17_
EVENT_STS
R/W
0
When GPIO17 is in input mode and a GPIO17 input is detected
according to CRE5[7], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
6
GPIO16_
EVENT_STS
R/W
0
When GPIO16 is in input mode and a GPIO16 input is detected
according to CRE5[6], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
5
GPIO15_
EVENT_STS
R/W
0
When GPIO15 is in input mode and a GPIO15 input is detected
according to CRE5[5], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
4
GPIO14_
EVENT_STS
R/W
0
When GPIO14 is in input mode and a GPIO14 input is detected
according to CRE5[4], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
3
GPIO13_
EVENT_STS
R/W
0
When GPIO13 is in input mode and a GPIO13 input is detected
according to CRE5[3], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
2
GPIO12_
EVENT_STS
R/W
0
When GPIO12 is in input mode and a GPIO12 input is detected
according to CRE5[2], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
1
GPIO11_
EVENT_STS
R/W
0
When GPIO11 is in input mode and a GPIO11 input is detected
according to CRE5[1], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
0
GPIO10_
EVENT_STS
R/W
0
When GPIO10 is in input mode and a GPIO10 input is detected
according to CRE5[0], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
6.8.16 GPIO2 Output Enable Register ⎯ Index D0h
Bit
Name
7
GPIO27_OE
R/W Default
R/W
0
Description
0: GPIO27 is in input mode.
1: GPIO27 is in output mode.
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GPIO26_OE
R/W
0
0: GPIO26 is in input mode.
1: GPIO25 is in output mode.
5
GPIO25_OE
R/W
0
0: GPIO25 is in input mode.
1: GPIO25 is in output mode.
4
GPIO24_OE
R/W
0
0: GPIO24 is in input mode.
1: GPIO24 is in output mode.
3
GPIO23_OE
R/W
0
0: GPIO23 is in input mode.
1: GPIO23 is in output mode.
2
GPIO22_OE
R/W
0
0: GPIO22 is in input mode.
1: GPIO22 is in output mode.
1
GPIO21_OE
R/W
0
0: GPIO21 is in input mode.
1: GPIO21 is in output mode.
0
GPIO20_OE
R/W
0
0: GPIO20 is in input mode.
1: GPIO20 is in output mode.
6.8.17 GPIO2 Output Data Register ⎯ Index D1h
Bit
Name
R/W Default
Description
7
GPIO27_VAL
R/W
1
0: GPIO27 outputs 0 when in output mode.
1: GPIO27 outputs 1 when in output mode.
6
GPIO26_VAL
R/W
1
0: GPIO26 outputs 0 when in output mode.
1: GPIO26 outputs 1 when in output mode.
5
GPIO25_VAL
R/W
1
0: GPIO25 outputs 0 when in output mode.
1: GPIO25 outputs 1 when in output mode.
4
GPIO24_VAL
R/W
1
0: GPIO24 outputs 0 when in output mode.
1: GPIO24 outputs 1 when in output mode.
3
GPIO23_VAL
R/W
1
0: GPIO23 outputs 0 when in output mode.
1: GPIO23 outputs 1 when in output mode.
2
GPIO22_VAL
R/W
1
0: GPIO22 outputs 0 when in output mode.
1: GPIO22 outputs 1 when in output mode.
1
GPIO21_VAL
R/W
1
0: GPIO21 outputs 0 when in output mode.
1: GPIO21 outputs 1 when in output mode.
0
GPIO20_VAL
R/W
1
0: GPIO20 outputs 0 when in output mode.
1: GPIO20 outputs 1 when in output mode.
6.8.18 GPIO2 Pin Status Register ⎯ Index D2h
Bit
Name
R/W Default
Description
7
GPIO27_IN
R
-
The pin status of SIN2/GPIO27.
6
GPIO26_IN
R
-
The pin status of SOUT2/GPIO26.
5
GPIO25_IN
R
-
The pin status of DSR2#/GPIO25.
4
GPIO24_IN
R
-
The pin status of RTS2#/GPIO24.
3
GPIO23_IN
R
-
The pin status of DTR2#/GPIO23.
2
GPIO22_IN
R
-
The pin status of CTS2#/GPIO22.
1
GPIO21_IN
R
-
The pin status of RI2#/GPIO21.
0
GPIO20_IN
R
-
The pin status of DCD2#/GPIO20.
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6.8.19 GPIO2 Drive Enable Register ⎯ Index D3h
Bit
Name
R/W Default
Description
7
GPIO27_DRV_EN R/W
0
0: GPIO27 is open drain in output mode.
1: GPIO27 is push pull in output mode.
6
GPIO26_DRV_EN R/W
0
0: GPIO26 is open drain in output mode.
1: GPIO26 is push pull in output mode.
5
GPIO25_DRV_EN R/W
0
0: GPIO25 is open drain in output mode.
1: GPIO25 is push pull in output mode.
4
GPIO24_DRV_EN R/W
0
0: GPIO24 is open drain in output mode.
1: GPIO24 is push pull in output mode.
3
GPIO23_DRV_EN R/W
0
0: GPIO23 is open drain in output mode.
1: GPIO23 is push pull in output mode.
2
GPIO22_DRV_EN R/W
0
0: GPIO22 is open drain in output mode.
1: GPIO22 is push pull in output mode.
1
GPIO21_DRV_EN R/W
0
0: GPIO21 is open drain in output mode.
1: GPIO21 is push pull in output mode.
0
GPIO20_DRV_EN R/W
0
0: GPIO20 is open drain in output mode.
1: GPIO20 is push pull in output mode.
6.8.20 GPIO3 Output Enable Register ⎯ Index C0h
Bit
Name
R/W Default
Description
7
GPIO37_OE
R/W
0
0: GPIO37 is in input mode.
1: GPIO37 is in output mode. (Open-drain).
6
GPIO36_OE
R/W
0
0: GPIO36 is in input mode.
1: GPIO35 is in output mode. (Open-drain).
5
GPIO35_OE
R/W
0
0: GPIO35 is in input mode.
1: GPIO35 is in output mode. (Open-drain).
4
GPIO34_OE
R/W
0
0: GPIO34 is in input mode.
1: GPIO34 is in output mode. (Open-drain).
3
GPIO33_OE
R/W
0
0: GPIO33 is in input mode.
1: GPIO33 is in output mode. (Open-drain).
2
GPIO32_OE
R/W
0
0: GPIO32 is in input mode.
1: GPIO32 is in output mode. (Open-drain).
1
GPIO31_OE
R/W
0
0: GPIO31 is in input mode.
1: GPIO31 is in output mode. (Open-drain).
0
GPIO30_OE
R/W
0
0: GPIO30 is in input mode.
1: GPIO30 is in output mode. (Open-drain).
6.8.21 GPIO3 Output Data Register ⎯ Index C1h
Bit
Name
R/W Default
Description
7
GPIO37_VAL
R/W
1
0: GPIO37 outputs 0 when in output mode.
1: GPIO37 outputs 1 when in output mode.
6
GPIO36_VAL
R/W
1
0: GPIO36 outputs 0 when in output mode.
1: GPIO36 outputs 1 when in output mode.
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GPIO35_VAL
R/W
1
0: GPIO35 outputs 0 when in output mode.
1: GPIO35 outputs 1 when in output mode.
4
GPIO34_VAL
R/W
1
0: GPIO34 outputs 0 when in output mode.
1: GPIO34 outputs 1 when in output mode.
3
GPIO33_VAL
R/W
1
0: GPIO33 outputs 0 when in output mode.
1: GPIO33 outputs 1 when in output mode.
2
GPIO32_VAL
R/W
1
0: GPIO32 outputs 0 when in output mode.
1: GPIO32 outputs 1 when in output mode.
1
GPIO31_VAL
R/W
1
0: GPIO31 outputs 0 when in output mode.
1: GPIO31 outputs 1 when in output mode.
0
GPIO30_VAL
R/W
1
0: GPIO30 outputs 0 when in output mode.
1: GPIO30 outputs 1 when in output mode.
6.8.22 GPIO3 Pin Status Register ⎯ Index C2h
Bit
Name
R/W Default
Description
7
GPIO37_IN
R
-
The pin status of WGATE#/GPIO37.
6
GPIO36_IN
R
-
The pin status of HDSEL#/GPIO36.
5
GPIO35_IN
R
-
The pin status of STEP#/GPIO35.
4
GPIO34_IN
R
-
The pin status of DIR#/GPIO34.
3
GPIO33_IN
R
-
The pin status of WDATA#/GPIO3.
2
GPIO32_IN
R
-
The pin status of DRVA#/GPIO32.
1
GPIO31_IN
R
-
The pin status of MOA#/GPIO31.
0
GPIO30_IN
R
-
The pin status of DENSEL#/GPIO30.
6.8.23 GPIO4 Output Enable Register ⎯ Index B0h
Bit
Name
R/W Default Description
7
GPIO47_OE
R/W
0
0: GPIO47 is in input mode.
1: GPIO47 is in output mode.
6
GPIO46_OE
R/W
0
0: GPIO46 is in input mode.
1: GPIO46 is in output mode.
5
GPIO45_OE
R/W
0
0: GPIO45 is in input mode.
1: GPIO45 is in output mode.
4
GPIO44_OE
R/W
0
0: GPIO44 is in input mode.
1: GPIO44 is in output mode.
3
GPIO43_OE
R/W
0
0: GPIO43 is in input mode.
1: GPIO43 is in output mode.
2
GPIO42_OE
R/W
0
0: GPIO42 is in input mode.
1: GPIO42 is in output mode.
1
GPIO41_OE
R/W
0
0: GPIO41 is in input mode.
1: GPIO41 is in output mode.
0
GPIO40_OE
R/W
0
0: GPIO40 is in input mode.
1: GPIO40 is in output mode.
6.8.24 GPIO4 Output Data Register ⎯ Index B1h
Bit
Name
R/W Default
Description
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GPIO47_VAL
R/W
1
0: GPIO47 outputs 0 when in output mode.
1: GPIO47 outputs 1 when in output mode.
6
GPIO46_VAL
R/W
1
0: GPIO46 outputs 0 when in output mode.
1: GPIO46 outputs 1 when in output mode.
5
GPIO45_VAL
R/W
1
0: GPIO45 outputs 0 when in output mode.
1: GPIO45 outputs 1 when in output mode.
4
GPIO44_VAL
R/W
1
0: GPIO44 outputs 0 when in output mode.
1: GPIO44 outputs 1 when in output mode.
3
GPIO43_VAL
R/W
1
0: GPIO43 outputs 0 when in output mode.
1: GPIO43 outputs 1 when in output mode.
2
GPIO42_VAL
R/W
1
0: GPIO42 outputs 0 when in output mode.
1: GPIO42 outputs 1 when in output mode.
1
GPIO41_VAL
R/W
1
0: GPIO41 outputs 0 when in output mode.
1: GPIO41 outputs 1 when in output mode.
0
GPIO40_VAL
R/W
1
0: GPIO40 outputs 0 when in output mode.
1: GPIO40 outputs 1 when in output mode.
6.8.25 GPIO4 Pin Status Register ⎯ Index B2h
Bit
Name
R/W Default
Description
7
GPIO47_IN
R
-
The pin status of PS_ON#/GPIO47.
6
GPIO46_IN
R
-
The pin status of PSOUT#/GPIO46
5
GPIO45_IN
R
-
The pin status of PSIN#/GPIO45
4
GPIO44_IN
R
-
The pin status of ATXPG_IN/GPIO44
3
GPIO43_IN
R
-
The pin status of IRRX/GPIO43.
2
GPIO42_IN
R
-
The pin status of IRTX/GPIO42.
1
GPIO41_IN
R
-
The pin status of FANCTL3/GPIO41.
0
GPIO40_IN
R
-
The pin status of FANIN3/GPIO40.
6.8.26 GPIO4 Drive Enable Register ⎯ Index B3h
Bit
Name
R/W Default
Description
7
GPIO47_DRV_EN R/W
0
0: GPIO47 is open drain in output mode.
1: GPIO47 is push pull in output mode.
6
GPIO46_DRV_EN R/W
0
0: GPIO46 is open drain in output mode.
1: GPIO46 is push pull in output mode.
5
GPIO45_DRV_EN R/W
0
0: GPIO45 is open drain in output mode.
1: GPIO45 is push pull in output mode.
4
GPIO44_DRV_EN R/W
0
0: GPIO44 is open drain in output mode.
1: GPIO44 is push pull in output mode.
3
GPIO43_DRV_EN R/W
0
0: GPIO43 is open drain in output mode.
1: GPIO43 is push pull in output mode.
2
GPIO42_DRV_EN R/W
0
0: GPIO42 is open drain in output mode.
1: GPIO42 is push pull in output mode.
1
GPIO41_DRV_EN R/W
0
0: GPIO41 is open drain in output mode.
1: GPIO41 is push pull in output mode.
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GPIO40_DRV_EN R/W
0
0: GPIO40 is open drain in output mode.
1: GPIO40 is push pull in output mode.
6.8.27 GPIO4 PME Enable Register ⎯ Index B4h
Bit
Name
7-4
Reserved
R/W Default
-
Description
-
Reserved
3
GPIO43_PME_EN R/W
0
When GPIO43_EVENT_STS is 1 and GPIO43_PME_EN is set to 1, a
GPIO PME event will be generated.
2
GPIO42_PME_EN R/W
0
When GPIO42_EVENT_STS is 1 and GPIO42_PME_EN is set to 1, a
GPIO PME event will be generated.
1
GPIO41_PME_EN R/W
0
When GPIO41_EVENT_STS is 1 and GPIO41_PME_EN is set to 1, a
GPIO PME event will be generated.
0
GPIO40_PME_EN R/W
0
When GPIO40_EVENT_STS is 1 and GPIO40_PME_EN is set to 1, a
GPIO PME event will be generated.
6.8.28 GPIO4 Input Detection Select Register ⎯ Index B5h
Bit
Name
7-4
Reserved
3
2
1
0
R/W Default
-
GPIO43_DET_SEL R/W
GPIO42_DET_SEL R/W
GPIO41_DET_SEL R/W
GPIO40_DET_SEL R/W
Description
-
Reserved
0
When GPIO43 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO42 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO41 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO40 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
6.8.29 GPIO4 Event Status Register ⎯ Index B6h
Bit
Name
R/W Default
Description
7-4
Reserved
-
-
Reserved
3
GPIO43_
EVENT_STS
R/W
-
When GPIO43 is in input mode and a GPIO43 input is detected
according to CRB5[3], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
2
GPIO42_
EVENT_STS
R/W
-
When GPIO42 is in input mode and a GPIO42 input is detected
according to CRB5[2], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
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GPIO41_
EVENT_STS
R/W
-
When GPIO41 is in input mode and a GPIO41 input is detected
according to CRB5[1], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
0
GPIO40_
EVENT_STS
R/W
-
When GPIO40 is in input mode and a GPIO40 input is detected
according to CRB5[0], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
6.8.30 GPIO5 Output Enable Register ⎯ Index A0h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
GPIO54_OE
R/W
0
0: GPIO54 is in input mode.
1: GPIO54 is in output mode.
3
GPIO53_OE
R/W
0
0: GPIO53 is in input mode.
1: GPIO53 is in output mode.
2
GPIO52_OE
R/W
0
0: GPIO52 is in input mode.
1: GPIO52 is in output mode.
1
GPIO51_OE
R/W
0
0: GPIO51 is in input mode.
1: GPIO51 is in output mode.
0
GPIO50_OE
R/W
0
0: GPIO50 is in input mode.
1: GPIO50 is in output mode.
6.8.31 GPIO5 Output Data Register ⎯ Index A1h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
GPIO54_VAL
R/W
1
0: GPIO54 outputs 0 when in output mode.
1: GPIO54 outputs 1 when in output mode.
3
GPIO53_VAL
R/W
1
0: GPIO53 outputs 0 when in output mode.
1: GPIO53 outputs 1 when in output mode.
2
GPIO52_VAL
R/W
1
0: GPIO52 outputs 0 when in output mode.
1: GPIO52 outputs 1 when in output mode.
1
GPIO51_VAL
R/W
1
0: GPIO51 outputs 0 when in output mode.
1: GPIO51 outputs 1 when in output mode.
0
GPIO50_VAL
R/W
1
0: GPIO50 outputs 0 when in output mode.
1: GPIO50 outputs 1 when in output mode.
6.8.32 GPIO5 Pin Status Register ⎯ Index A2h
Bit
Name
R/W Default
Description
7-5
Reserved
-
-
Reserved.
4
GPIO54_IN
R
-
The pin status of DSKCHG#/GPIO54.
3
GPIO53_IN
R
-
The pin status of WPT#/GPIO53.
2
GPIO52_IN
R
-
The pin status of INDEX#/GPIO52.
1
GPIO51_IN
R
-
The pin status of TRK0#/GPIO51.
0
GPIO50_IN
R
-
The pin status of RDDATA#/GPIO50.
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6.8.33 GPIO5 PME Enable Register ⎯ Index A4h
Bit
Name
R/W Default
Description
7
GPIO37_PME_EN R/W
0
When GPIO37_EVENT_STS is 1 and GPIO37_PME_EN is set to 1, a
GPIO PME event will be generated.
6
GPIO36_PME_EN R/W
0
When GPIO37_EVENT_STS is 1 and GPIO37_PME_EN is set to 1, a
GPIO PME event will be generated.
5
GPIO35_PME_EN R/W
0
When GPIO37_EVENT_STS is 1 and GPIO37_PME_EN is set to 1, a
GPIO PME event will be generated.
4
GPIO54_PME_EN R/W
0
When GPIO54_EVENT_STS is 1 and GPIO54_PME_EN is set to 1, a
GPIO PME event will be generated.
3
GPIO53_PME_EN R/W
0
When GPIO53_EVENT_STS is 1 and GPIO53_PME_EN is set to 1, a
GPIO PME event will be generated.
2
GPIO52_PME_EN R/W
0
When GPIO52_EVENT_STS is 1 and GPIO52_PME_EN is set to 1, a
GPIO PME event will be generated.
1
GPIO51_PME_EN R/W
0
When GPIO51_EVENT_STS is 1 and GPIO51_PME_EN is set to 1, a
GPIO PME event will be generated.
0
GPIO50_PME_EN R/W
0
When GPIO50_EVENT_STS is 1 and GPIO50_PME_EN is set to 1, a
GPIO PME event will be generated.
6.8.34 GPIO5 Input Detection Select Register ⎯ Index A5h
Bit
7
6
5
4
3
2
Name
R/W Default
GPIO37_DET_SEL R/W
GPIO36_DET_SEL R/W
GPIO35_DET_SEL R/W
GPIO54_DET_SEL R/W
GPIO53_DET_SEL R/W
GPIO52_DET_SEL R/W
Description
0
When GPIO37 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO36 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO35 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO54 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO53 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO52 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
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0
GPIO51_DET_SEL R/W
GPIO50_DET_SEL R/W
0
When GPIO51 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
0
When GPIO50 is in input mode, set this bit to select which input event
should be detected.
0: rising edge
1: falling edge
6.8.35 GPIO5 Event Status Register ⎯ Index A6h
Bit
Name
R/W Default
Description
7
GPIO37_
EVENT_STS
R/W
-
When GPIO37 is in input mode and a GPIO37 input is detected
according to CRA5[7], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
6
GPIO36_
EVENT_STS
R/W
-
When GPIO36 is in input mode and a GPIO36 input is detected
according to CRA5[6], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
5
GPIO35_
EVENT_STS
R/W
-
When GPIO35 is in input mode and a GPIO35 input is detected
according to CRA5[5], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
4
GPIO54_
EVENT_STS
R/W
-
When GPIO54 is in input mode and a GPIO54 input is detected
according to CRA5[4], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
3
GPIO53_
EVENT_STS
R/W
-
When GPIO53 is in input mode and a GPIO53 input is detected
according to CRA5[3], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
2
GPIO52_
EVENT_STS
R/W
-
When GPIO52 is in input mode and a GPIO52 input is detected
according to CRB5[2], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
1
GPIO51_
EVENT_STS
R/W
-
When GPIO51 is in input mode and a GPIO51 input is detected
according to CRB5[1], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
0
GPIO50_
EVENT_STS
R/W
-
When GPIO50 is in input mode and a GPIO50 input is detected
according to CRB5[0], this bit will be set to 1. Write a 1 to this bit will
clear it to 0.
6.8.36 GPIO5 KBC Emulation Control Register 1⎯ Index A9h
Bit
7-6
5-4
Name
DELAY_TIME
REP_TIME
R/W Default
R/W
R/W
Description
00
The delay time for repeat make code.
00: 500ms ~ 750ms.
01: 750ms ~ 1000ms.
10: 1000ms ~ 1250ms.
11: 1250ms ~ 1500ms.
00
The make code repeat time select.
00: 50ms.
01: 100ms.
10: 250ms.
11: 500ms.
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2-0
EVENT_EN_SEL
R/W
MAKE_CODE_SE
R/W
L
0
000
0: Index 0xAF is GPIO5 event enable register.
1: Index 0xAF is GPIO3 event enable register.
Make code select. Select which make code to be accessed.
000: GPIO50 make code.
001: GPIO51 make code.
010: GPIO52 make code.
011: GPIO53 make code.
100: GPIO54 make code.
101: GPIO35 make code.
110: GPIO36 make code.
111: GPIO37 make code.
This changes the content of GP_MAKE_CODE register (CRAB).
6.8.37 GPIO5 KBC Make Code Register ⎯ Index ABh
Bit
Name
R/W Default
7-0 GP_MAKE_CODE R/W
00h
Description
This byte is the make code for GPIO5 KBC emulation. The break
code will be GP_MAKE_CODE + 0x80.
6.8.38 GPIO5 KBC Prefix Code Register ⎯ Index ACh
Bit
Name
7-0
GP_PRE_CODE
R/W Default
R/W
E0h
Description
This byte is the prefix code for GPIO5 KBC emulation if
PRE_CODE_EN is set.
6.8.39 GPIO5 KBC Emulation Status Register 1⎯ Index ADh
Bit
Name
R/W Default
Description
7
GP37_BRK_STS
R/W
0
Break code status of GPIO37. It will be set if GPIO37 is released
(rising edge). Write “1” to clear this bit.
6
GP36_BRK_STS
R/W
0
Break code status of GPIO36. It will be set if GPIO36 is released
(rising edge). Write “1” to clear this bit.
5
GP35_BRK_STS
R/W
0
Break code status of GPIO35. It will be set if GPIO35 is released
(rising edge). Write “1” to clear this bit.
4
GP54_BRK_STS
R/W
0
Break code status of GPIO54. It will be set if GPIO54 is released
(rising edge). Write “1” to clear this bit.
3
GP53_BRK_STS
R/W
0
Break code status of GPIO53. It will be set if GPIO53 is released
(rising edge). Write “1” to clear this bit.
2
GP52_BRK_STS
R/W
0
Break code status of GPIO52. It will be set if GPIO52 is released
(rising edge). Write “1” to clear this bit.
1
GP51_BRK_STS
R/W
0
Break code status of GPIO51. It will be set if GPIO51 is released
(rising edge). Write “1” to clear this bit.
0
GP50_BRK_STS
R/W
0
Break code status of GPIO50. It will be set if GPIO50 is released
(rising edge). Write “1” to clear this bit.
6.8.40 GPIO5 KBC Emulation Status Register 2⎯ Index AEh
Bit
7
Name
R/W Default
GP37_MAKE_STS R/W
0
Description
Make code status of GPIO37. It will be set if GPIO37 is pressed
(falling edge). Write “1” to clear this bit.
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GP36_MAKE_STS R/W
0
Make code status of GPIO36. It will be set if GPIO36 is pressed
(falling edge). Write “1” to clear this bit.
5
GP35_MAKE_STS R/W
0
Make code status of GPIO35. It will be set if GPIO35 is pressed
(falling edge). Write “1” to clear this bit.
4
GP54_MAKE_STS R/W
0
Make code status of GPIO54. It will be set if GPIO54 is pressed
(falling edge). Write “1” to clear this bit.
3
GP53_MAKE_STS R/W
0
Make code status of GPIO53. It will be set if GPIO53 is pressed
(falling edge). Write “1” to clear this bit.
2
GP52_MAKE_STS R/W
0
Make code status of GPIO52. It will be set if GPIO52 is pressed
(falling edge). Write “1” to clear this bit.
1
GP51_MAKE_STS R/W
0
Make code status of GPIO51. It will be set if GPIO51 is pressed
(falling edge). Write “1” to clear this bit.
0
GP50_MAKE_STS R/W
0
Make code status of GPIO50. It will be set if GPIO50 is pressed
(falling edge). Write “1” to clear this bit.
6.8.41 GPIO5 KBC Emulation Control Register 2⎯ Index AFh
Bit
Name
7
GP_KBC_EN
R/W Default
R/W
Description
0
0: Disable KBC emulation function.
1: Enable KBC emulation function.
This bit is only available when EVENT_EN_SEL is “0”
6
PRE_CODE_EN
R/W
0
0: One byte is sent when GPIO5 event occurs.
1: Two bytes are sent when GPIO5 event occurs. The prefix code is
defined by GP_PRE_CODE.
This bit is only available when EVENT_EN_SEL is “0”
5
Reserved
-
-
Reserved.
0
0: Disable GPIO54 event detection.
1: Enable GPIO54 event detection.
This bit is only available when EVENT_EN_SEL is “0”
4
GP54_EVENT_EN R/W
3
GP53_EVENT_EN R/W
0
0: Disable GPIO53 event detection.
1: Enable GPIO53 event detection.
This bit is only available when EVENT_EN_SEL is “0”
2
GP52_EVENT_EN/
R/W
GP37_EVENT_EN
0
When EVENT_EN_SEL is “1”, the register is GP37_EVENT_EN.
0: Disable GPIO52/GPIO37 event detection.
1: Enable GPIO52/GPIO37 event detection.
1
GP51_EVENT_EN/
R/W
GP36_EVENT_EN
0
When EVENT_EN_SEL is “1”, the register is GP36_EVENT_EN.
0: Disable GPIO51/GPIO36 event detection.
1: Enable GPIO51/GPIO37 event detection.
0
GP50_EVENT_EN/
R/W
GP35_EVENT_EN
0
When EVENT_EN_SEL is “1”, the register is GP35_EVENT_EN.
0: Disable GPIO50/GPIO35 event detection.
1: Enable GPIO50/GPIO35 event detection.
6.8.42 GPIO6 Output Enable Register ⎯ Index 90h
Bit
Name
R/W Default
Description
7
GPIO67_OE
R/W
0
0: GPIO67 is in input mode.
1: GPIO67 is in output mode.
6
GPIO66_OE
R/W
0
0: GPIO66 is in input mode.
1: GPIO66 is in output mode.
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GPIO65_OE
R/W
0
0: GPIO65 is in input mode.
1: GPIO65 is in output mode.
4
GPIO64_OE
R/W
0
0: GPIO64 is in input mode.
1: GPIO64 is in output mode.
3
GPIO63_OE
R/W
0
0: GPIO63 is in input mode.
1: GPIO63 is in output mode.
2
GPIO62_OE
R/W
0
0: GPIO62 is in input mode.
1: GPIO62 is in output mode.
1
GPIO61_OE
R/W
0
0: GPIO61 is in input mode.
1: GPIO61 is in output mode.
0
GPIO60_OE
R/W
0
0: GPIO60 is in input mode.
1: GPIO60 is in output mode.
6.8.43 GPIO6 Output Data Register ⎯ Index 91h
Bit
Name
R/W Default
Description
7
GPIO67_VAL
R/W
1
0: GPIO67 outputs 0 when in output mode.
1: GPIO67 outputs 1 when in output mode.
6
GPIO66_VAL
R/W
1
0: GPIO66 outputs 0 when in output mode.
1: GPIO66 outputs 1 when in output mode.
5
GPIO65_VAL
R/W
1
0: GPIO65 outputs 0 when in output mode.
1: GPIO65 outputs 1 when in output mode.
4
GPIO64_VAL
R/W
1
0: GPIO64 outputs 0 when in output mode.
1: GPIO64 outputs 1 when in output mode.
3
GPIO63_VAL
R/W
1
0: GPIO63 outputs 0 when in output mode.
1: GPIO63 outputs 1 when in output mode.
2
GPIO62_VAL
R/W
1
0: GPIO62 outputs 0 when in output mode.
1: GPIO62 outputs 1 when in output mode.
1
GPIO61_VAL
R/W
1
0: GPIO61 outputs 0 when in output mode.
1: GPIO61 outputs 1 when in output mode.
0
GPIO60_VAL
R/W
1
0: GPIO60 outputs 0 when in output mode.
1: GPIO60 outputs 1 when in output mode.
6.8.44 GPIO6 Pin Status Register ⎯ Index 92h
Bit
Name
R/W Default
Description
7
GPIO67_IN
R
-
The pin status of STB#/GPIO67.
6
GPIO66_IN
R
-
The pin status of AFD#/GPIO66.
5
GPIO65_IN
R
-
The pin status of ERR#/GPIO65.
4
GPIO64_IN
R
-
The pin status of INIT#/GPIO64.
3
GPIO63_IN
R
-
The pin status of ACK#/GPIO63.
2
GPIO62_IN
R
-
The pin status of BUSY/GPIO62.
1
GPIO61_IN
R
-
The pin status of PE/GPIO61.
0
GPIO60_IN
R
-
The pin status of SLCT/GPIO60.
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6.8.45 GPIO6 Drive Enable Register ⎯ Index 93h
Bit
Name
R/W Default
Description
7
GPIO67_DRV_EN R/W
0
0: GPIO67 is open drain in output mode.
1: GPIO67 is push pull in output mode.
6
GPIO66_DRV_EN R/W
0
0: GPIO66 is open drain in output mode.
1: GPIO66 is push pull in output mode.
5
GPIO65_DRV_EN R/W
0
0: GPIO65 is open drain in output mode.
1: GPIO65 is push pull in output mode.
4
GPIO64_DRV_EN R/W
0
0: GPIO64 is open drain in output mode.
1: GPIO64 is push pull in output mode.
3
GPIO63_DRV_EN R/W
0
0: GPIO63 is open drain in output mode.
1: GPIO63 is push pull in output mode.
2
GPIO62_DRV_EN R/W
0
0: GPIO62 is open drain in output mode.
1: GPIO62 is push pull in output mode.
1
GPIO61_DRV_EN R/W
0
0: GPIO61 is open drain in output mode.
1: GPIO61 is push pull in output mode.
0
GPIO60_DRV_EN R/W
0
0: GPIO60 is open drain in output mode.
1: GPIO60 is push pull in output mode.
6.8.46 GPIO7 Output Enable Register ⎯ Index 80h
Bit
Name
R/W Default
Description
7
GPIO77_OE
R/W
0
0: GPIO77 is in input mode.
1: GPIO77 is in output mode.
6
GPIO76_OE
R/W
0
0: GPIO76 is in input mode.
1: GPIO76 is in output mode.
5
GPIO75_OE
R/W
0
0: GPIO75 is in input mode.
1: GPIO75 is in output mode.
4
GPIO74_OE
R/W
0
0: GPIO74 is in input mode.
1: GPIO74 is in output mode.
3
GPIO73_OE
R/W
0
0: GPIO73 is in input mode.
1: GPIO73 is in output mode.
2
GPIO72_OE
R/W
0
0: GPIO72 is in input mode.
1: GPIO72 is in output mode.
1
GPIO71_OE
R/W
0
0: GPIO71 is in input mode.
1: GPIO71 is in output mode.
0
GPIO70_OE
R/W
0
0: GPIO70 is in input mode.
1: GPIO70 is in output mode.
6.8.47 GPIO7 Output Data Register ⎯ Index 81h
Bit
Name
R/W Default
Description
7
GPIO77_VAL
R/W
1
0: GPIO77 outputs 0 when in output mode.
1: GPIO77 outputs 1 when in output mode.
6
GPIO76_VAL
R/W
1
0: GPIO76 outputs 0 when in output mode.
1: GPIO76 outputs 1 when in output mode.
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GPIO75_VAL
R/W
1
0: GPIO75 outputs 0 when in output mode.
1: GPIO75 outputs 1 when in output mode.
4
GPIO74_VAL
R/W
1
0: GPIO74 outputs 0 when in output mode.
1: GPIO74 outputs 1 when in output mode.
3
GPIO73_VAL
R/W
1
0: GPIO73 outputs 0 when in output mode.
1: GPIO73 outputs 1 when in output mode.
2
GPIO72_VAL
R/W
1
0: GPIO72 outputs 0 when in output mode.
1: GPIO72 outputs 1 when in output mode.
1
GPIO71_VAL
R/W
1
0: GPIO71 outputs 0 when in output mode.
1: GPIO71 outputs 1 when in output mode.
0
GPIO70_VAL
R/W
1
0: GPIO70 outputs 0 when in output mode.
1: GPIO70 outputs 1 when in output mode.
6.8.48 GPIO7 Pin Status Register ⎯ Index 82h
Bit
Name
R/W Default
Description
7
GPIO77_IN
R
-
The pin status of PD7/GPIO77.
6
GPIO76_IN
R
-
The pin status of PD6/GPIO76.
5
GPIO75_IN
R
-
The pin status of PD5/GPIO75.
4
GPIO74_IN
R
-
The pin status of PD4/GPIO74.
3
GPIO73_IN
R
-
The pin status of PD3/GPIO73.
2
GPIO72_IN
R
-
The pin status of PD2/GPIO72.
1
GPIO71_IN
R
-
The pin status of PD1/GPIO71.
0
GPIO70_IN
R
-
The pin status of PD0/GPIO70.
6.8.49 GPIO7 Drive Enable Register ⎯ Index 83h
Bit
Name
R/W Default
Description
7
GPIO77_DRV_EN R/W
0
0: GPIO77 is open drain in output mode.
1: GPIO77 is push pull in output mode.
6
GPIO76_DRV_EN R/W
0
0: GPIO76 is open drain in output mode.
1: GPIO76 is push pull in output mode.
5
GPIO75_DRV_EN R/W
0
0: GPIO75 is open drain in output mode.
1: GPIO75 is push pull in output mode.
4
GPIO74_DRV_EN R/W
0
0: GPIO74 is open drain in output mode.
1: GPIO74 is push pull in output mode.
3
GPIO73_DRV_EN R/W
0
0: GPIO73 is open drain in output mode.
1: GPIO73 is push pull in output mode.
2
GPIO72_DRV_EN R/W
0
0: GPIO72 is open drain in output mode.
1: GPIO72 is push pull in output mode.
1
GPIO71_DRV_EN R/W
0
0: GPIO71 is open drain in output mode.
1: GPIO71 is push pull in output mode.
0
GPIO70_DRV_EN R/W
0
0: GPIO70 is open drain in output mode.
1: GPIO70 is push pull in output mode.
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6.9
Watch Dog Timer Registers (CR07)
6.9.1 WDT Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
0
Reserved
0
WDT_EN
R/W
0
0: disable watch dog timer
1: enable watch dog timer
6.9.2 Base Address High Register ⎯ Index 60h
Bit
Name
7-0
BASE_ADDR_HI
R/W Default
R/W
00h
Description
The MSB of WDT base address.
6.9.3 Base Address Low Register ⎯ Index 61h
Bit
7-0
Name
R/W Default
BASE_ADDR_LO R/W
00h
Description
The LSB of WDT base address.
6.9.4 Configuration Register ⎯ Index F0h (Offset 00h)
(* Cleared by Slotocc# and watch dog timeout)
Bit
Name
R/W Default Description
This bit is decided by RTS1# power-on trapping.
7
WDOUT_EN
R/W
-
If this bit is set to 1 and watchdog timeout event occurs, WDTRST#
output is enabled.
6-1
Reserved
-
-
0
WD_RST_EN
R/W
1
6.9.5
Reserved
0: Disable WDT to reset the VID register marked with *.
1: Enable WDT to reset the VID register marked with *.
Serial Key Data Register 1 ⎯ Index F2h (Offset 02h)
Bit
Name
7
Reserved
-
-
Reserved
6
KEY_OK
R
1
This bit is 1 represents that the serial key is entered correctly.
5-0
Reserved
-
-
Reserved
6.9.6
Bit
R/W Default
Description
Serial Key Data Register 2 ⎯ Index F3h (Offset 03h)
Name
R/W Default
Description
Write serial data to this register correctly, the KEY_OK bit will be set to
7-0
KEY_DATA
R/W
F3h
1. Hence, users are able to write key protected registers. The
sequence to enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When
KEY_OK is set, write this register 0x35 will clear KEY_OK.
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6.9.7
Reserved ⎯ Index F4h (Offset 04h)
Bit
Name
7-0
Reserved
6.9.8
Bit
R/W Default
-
-
Description
Reserved
Watchdog Timer Configuration Register 1⎯ Index F5h (Offset 05h)
Name
R/W Default
Description
Select the WDT clock source.
0: The clock source is from CLKIN. (powered by VDD and is
7
WDT_CLK_SEL
R
0
accurate)\
1: The clock source is from internal 500KHz (powered by VSB3V and
20% tolerance).
6
WDTMOUT_STS R/W
0
5
WD_EN
R/W
-
4
WD_PULSE
R/W
0
3
WD_UNIT
R/W
0
2
WD_HACTIVE
R/W
0
If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to
this bit will clear it to 0.
This bit is decided by RTS1# power-on trapping.
If this bit is set to 1, the counting of watchdog time is enabled.
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this
bit.
Select output polarity of RSTOUT# (1: high active, 0: low active) by
setting this bit.
Select output pulse width of RSTOUT#
1:0
6.9.9
WD_PSWIDTH
R/W
0
0: 750 us
1: 18 ms
2: 93 ms
3: 3.75 sec
Watchdog Timer Configuration Register 2 ⎯ Index F6h (Offset 06h)
Bit
Name
7:0
WD_TIME
R/W Default
R/W
0A
Description
Time of watchdog timer
6.9.10 WDT PME Register ⎯ Index F7h (Offset 07h)
Bit
Name
R/W Default
7
WDT_PME
R
0
6
WDT_PME_EN
R/W
0
Description
WDT PME real time status.
0: Disable WDT PME.
1: Enable WDT PME.
0: No WDT PME occurred.
6
WDT_PME_ST
R/W
0
1: WDT PME occurred.
The WDT PME is occurred one unit before WDT timeout.
4-1
Reserved
R
0
Reserved
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0
R/W
CPU_CHANGE
C
This bit will be set at SLOTOCC# rising edge. Internal 1us de-bounce
-
circuit is implemented. Write “1” to this bit will clear the status.(This bit
is powered by VBAT.)
6.10 CIR Registers (CR08)
Configuration Registers
6.10.1 CIR Enable Register ⎯ Index 30h
Bit
Name
R/W Default
Description
7-1
Reserved
-
0
Reserved
0
CIR_EN
R/W
0
0: disable CIR
1: enable CIR
6.10.2 Base Address High Register ⎯ Index 60h
Bit
Name
R/W
Default
7-0
BASE_ADDR_HI
R/W
00h
Description
The MSB of CIR base address.
6.10.3 Base Address Low Register ⎯ Index 61h
Bit
7-0
Name
R/W Default
BASE_ADDR_LO R/W
00h
Description
The LSB of CIR base address.
6.10.4 CIRIRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Default
7-4
Reserved
-
-
3-0
SELCIRIRQ
R/W
0h
Description
Reserved.
Select the IRQ channel for CIR interrupt.
Device Registers
6.10.5 CIR Status Register ⎯ Index 00h
Bit
Name
R/W Default
Description
7
CIR_IRQ_EN
R/W
0
CIR IRQ function enable
6-4
Reserved
R
0
Reserved
3
TX_FINISH
R/W
0
CIR transmittion finish status. Write 1 clear.
2
TX_UNDERRUN
R/W
0
CIR transmitttion underrun status. Write 1 clear.
1
RX_TIMEOUT
R/W
0
CIR receiver timeout status. Write 1 clear.
0
RX_RECEIVE
R/W
0
CIR receiver receives data status. Write 1 clear.
6.10.6 CIR RX Data Register ⎯ Index 01h
Bit
Name
R/W Default
Description
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7-0
RX_DATA
R
-
CIR received data is read from here.
6.10.7 CIR TX Control Register ⎯ Index 02h
Bit
Name
R/W Default
Description
7
TX_START
R/W
0
6
TX_END
R/W
0
Set 1 to start CIR TX transmittion and will be auto cleared if transmittion is
finished.
Set 1 to indicate that all TX data has been written to CIR TX FIFO.
5-0
Reserved
-
-
Reserved
6.10.8 CIR TX Data Register ⎯ Index 03h
Bit
Name
7-0
TX_DATA
R/W Default
R/W
-
Description
The transmittion data should be written to TX_DATA.
6.10.9 CIR Control Register ⎯ Index 04h
Bit
Name
7-0
CIR_CMD
R/W Default
R/W
0
Description
Host writes command to CIR.
6.11 PME, ACPI, and ERP Power Saving Registers (CR0A)
6.11.1 Device Enable Register ⎯ Index 30h
Bit
Name
7-1
Reserved
R/W Default
-
-
Reserved
Description
0
PME_EN
R/W
0
0: disable PME.
1: enable PME.
6.11.2 ERP Enable Register ⎯ Index E0h
Bit
Name
7
EUP_EN
R/W
0
0 : disable ERP function
1: enable ERP function
6
S3_BACK
R/W
0
This bit will set “1” when system is back from S3 state.
5-2
Reserved
-
-
Reserved
1
RING_PME_EN
R/W
0
RING1 PME event enable.
0: disable RING1 PME event.
1: enable RING1 PME event, when RING1 falling edge detect
RING_PSOUT_EN R/W
0
RING1 PSOUT event enable.
0: disable RING1 PSOUT event.
1: enable RING1 PSOUT event, when RING1 falling edge detect
0
R/W Default
Description
6.11.3 ERP control register ⎯ Index E1h
Bit
Name
R/W Default
Description
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11
Write these two bits to select Boot Mode for Always Off/ Always On/
Keep Last State.
00:Always Off
11:Support Always On and Keep Last State
10:Reserved
01:Reserved
5
S3_
R/W
ERP_CTRL1#_DIS
0
If clear to “0” ERP_CTRL1# will output Low when S3 state. Else If set
to “1” ERP_CTRL1# will output High when S3 state.
4
S3 _
R/W
ERP_CTRL0#_DIS
0
If clear to “0” ERP_CTRL0# will output Low when S3 state. Else If set
to “1” ERP_CTRL0# will output High when S3 state.
3
S5 _
R/W
ERP_CTRL1#_DIS
1
If clear to “0” ERP_CTRL1# will output Low when S5 state. Else If set
to “1” ERP_CTRL1# will output High when S5 state.
2
S5 _
R/W
ERP_CTRL0#_DIS
1
If clear to “0” ERP_CTRL0# will output Low when S5 state. Else If set
to “1” ERP_CTRL0# will output High when S5 state.
1
AC_
R/W
ERP_CTRL1#_DIS
0
If clear to “0” ERP_CTRL1# will output Low when after AC lost. Else
If set to “1” ERP_CTRL1# will output High when after AC lost.
0
AC_
R/W
ERP_CTRL0#_DIS
0
If clear to “0” ERP_CTRL0# will output Low when after AC lost. Else
If set to “1” ERP_CTRL0# will output High when after AC lost.
7-6
Boot_Mode
6.11.4 ERP control register ⎯ Index E2h
Bit
Name
R/W Default
Description
7
AC_LOST
R
-
This bit is AC lost status and writes 1 to this bit will clear it.
6
Reserved
R/W
0
Reserved
5
VSB_CTRL_EN[1] R/W
1’b0
0: Disable ERP_CTRL1# assert RSMRST low
1: Enable ERP_CTRL1# assert RSMRST low
4
VSB_CTRL_EN[0] R/W
1’b0
0: Disable ERP_CTRL0# assert RSMRST low
1: Enable ERP_CTRL0# assert RSMRST low
3-2
1
0
Reserved
R/W
0
Reserved
RSMRST_DET_5V
R/W
_N
0
Device detects VSB5V power ok (4.4V) and VSB3V_IN become high,
and after ~50ms de-bounce time RSMRST will become high. But when
user set this bit to 1. RSMRST will not check VSB5V power ok.
-
Reserved
Reserved
R
6.11.5 ERP PSIN deb-register ⎯ Index E3h
Bit
Name
7-0
PS_DEB_TIME
R/W Default
R/W
Description
0x13 PS_IN pin input de-bounce time default is ~20mSec
6.11.6 ERP RSMRST deb-register ⎯ Index E4h
Bit
7-0
Name
R/W Default
RSMRST_DEB_TI
R/W
ME
0x09
Description
RSMRST internal de-bounce time default is ~10mSec
6.11.7 ERP PSOUT deb-register ⎯ Index E5h
Bit
Name
R/W Default
7-0 PS_OUT_PULSE_W R/W
0xC7
Description
PS_OUT_OUT output Pulse width default is ~200mSec low pulse
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6.11.8 ERP PSON deb-register ⎯ Index E6h
Bit
Name
R/W Default
7-0 PS_ON_DEB_TIME R/W
0x09
Description
PSON_IN pin input de-bounce time default is 10mSec
6.11.9 ERP S5 Delay Register ⎯ Index E7h
Bit
Name
7-0
S5_DEL_TIME
R/W Default
R/W
Description
0x63 S5 to deep S5 state delay time. The unit of this byte is 64 ms
6.11.10 Wakeup Enable register ⎯ Index E8h
Bit
Name
R/W Default
Description
7
RI2_WAKEUP_EN
R/W
0
Set this bit to enable RI2# event to wakeup system.
6
CIR_WAKEUP_EN
R/W
0
Set this bit to enable CIR event to wakeup system.
5
RI1_WAKEUP_EN
R/W
0
Set this bit to enable RI1# event to wakeup system.
4
RING_WAKEUP_EN
R/W
1
Set this bit to enable EVENT_IN0# event to wakeup system.
3
GP_WAKEUP_EN
R/W
0
Set this bit to enable GPIO event to wakeup system.
2 TMOUT_WAKEUP_EN R/W
0
Set this bit to enable Timeout event to wakeup system.
1
MO_WAKEUP_EN
R/W
0
Set this bit to enable Mouse event to wakeup system.
0
KB_WAKEUP_EN
R/W
0
Set this bit to enable Keyboard event to wakeup system.
6.11.11 ERP S3 Delay Register ⎯ Index E9h
Bit
Name
7-0
S3_DEL_TIME
R/W Default
R/W
Description
0x0F S3 to deep S3 state delay time. The unit of this byte is 64ms.
6.11.12 ERP Mode Select register ⎯ Index ECh
Bit
Name
7-6
ERP_MODE
5
4-0
R/W Default
Description
R/W
0
00: Fintek G3’ mode.
01: Intel DSW + Fintek G3` mode.
10: Reserved.
11: Intel DSW mode.
DPWROK_CTRL_ R/W
EN
0
Set “1” to enable DPWROK reset by ERP_CTRL1#.
-
Reserved
Reserved
R
6.11.13 ERP WDT Control register ⎯ Index EDh
Bit
Name
7-6 ERP_WD_TIME[11
:10]
R/W Default
Description
R
-
Time of ERP watchdog timer.
Write index EEh will load watchdog time.
5
Reserved
R
-
Reserved
4
ERP_WDTMOUT
R
-
Time of ERP watchdog timer.
Write index EEh will load watchdog time.
3-2 ERP_WD_TIME[9:
8]
R
-
Reserved
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1
WD_UNIT
R/W
0
ERP WDT unit. It is the time unit of ERP_WD_TIME.
0: 1sec.
1: 60 sec.
0
WD_EN
R/W
0
Set “1” to enable ERP WDT. Auto clear if timeout occurs.
6.11.14 ERP WDT Timer ⎯ Index EEh
Bit
Name
7-0
ERP_WD_TIME
R/W Default
R/W
0
Description
Time of ERP watchdog timer.
6.11.15 PME Event Enable Register 1⎯ Index F0h
Bit
Name
R/W Default
Description
7
WDT_PME_EN
R/W
0
WDT PME event enable.
0: disable WDT PME event.
1: enable WDT PME event.
6
MO_PME_EN
R/W
0
Mouse PME event enable.
0: disable mouse PME event.
1: enable mouse PME event.
5
KB_PME_EN
R/W
0
Keyboard PME event enable.
0: disable keyboard PME event.
1: enable keyboard PME event.
4
HM_PME_EN
R/W
0
Hardware monitor PME event enable.
0: disable hardware monitor PME event.
1: enable hardware monitor PME event.
3
PRT_PME_EN
R/W
0
Parallel port PME event enable.
0: disable parallel port PME event.
1: enable parallel port PME event.
2
UR2_PME_EN
R/W
0
UART 2 PME event enable.
0: disable UART 2 PME event.
1: enable UART 2 PME event.
1
UR1_PME_EN
R/W
0
UART 1 PME event enable.
0: disable UART 1 PME event.
1: enable UART 1 PME event.
0
FDC_PME_EN
R/W
0
FDC PME event enable.
0: disable FDC PME event.
1: enable FDC PME event.
6.11.16 PME Event Status Register ⎯ Index F1h
Bit
7
6
Name
WDT_PME_ST
MO_PME_ST
R/W Default
R/W
R/W
Description
-
WDT PME event status.
0: WDT has no PME event.
1: WDT has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
Mouse PME event status.
0: Mouse has no PME event.
1: Mouse has a PME event to assert. Write 1 to clear to be ready for
next PME event.
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5
4
3
2
1
0
KB_PME_ST
HM_PME_ST
PRT_PME_ST
UR2_PME_ST
UR1_PME_ST
FDC_PME_ST
R/W
R/W
R/W
R/W
R/W
R/W
-
Keyboard PME event status.
0: Keyboard has no PME event.
1: Keyboard has a PME event to assert. Write 1 to clear to be ready
for next PME event.
-
Hardware monitor PME event status.
0: Hardware monitor has no PME event.
1: Hardware monitor has a PME event to assert. Write 1 to clear to be
ready for next PME event.
-
Parallel port PME event status.
0: Parallel port has no PME event.
1: Parallel port has a PME event to assert. Write 1 to clear to be ready
for next PME event.
-
UART 2 PME event status.
0: UART 2 has no PME event.
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
UART 1 PME event status.
0: UART 1 has no PME event.
1: UART 1 has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
FDC PME event status.
0: FDC has no PME event.
1: FDC has a PME event to assert. Write 1 to clear to be ready for
next PME event.
6.11.17 PME Event Enable Register 2 ⎯ Index F2h
Bit
Name
7-5
Reserved
R/W Default
-
Description
-
Reserved
4
CIR_PME_EN
R/W
0
CIR PME event enable.
0: disable CIR PME event.
1: enable CIR PME event.
3
Reserved
-
-
Reserved
2
RI2_PME_EN
R/W
0
RI2# PME event enable.
0: disable RI2# PME event.
1: enable RI2# PME event.
1
RI1_PME_EN
R/W
0
RI1# PME event enable.
0: disable RI1# PME event.
1: enable RI1# PME event.
0
GPIO PME event enable.
0: disable GPIO PME event.
1: enable GPIO PME event.
0
GP_PME_EN
R/W
6.11.18 PME Event Status Register ⎯ Index F3h
Bit
Name
7-5
Reserved
R/W Default
-
-
Description
Reserved
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4
3
2
1
0
CIR_PME_ST
ERP_PME_ST
RI2_PME_ST
RI1_PME_ST
GP_PME_ST
R/W
R/W
R/W
R/W
R/W
-
CIR PME event status.
0: CIR has no PME event.
1: CIR has a PME event to assert. Write 1 to clear to be ready for next
PME event.
-
ERP PME event status.
0: ERP has no PME event.
1: ERP has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
RI2# PME event status.
0: RI2# has no PME event.
1: RI2# has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
RI1# PME event status.
0: RI1# has no PME event.
1: RI1# has a PME event to assert. Write 1 to clear to be ready for
next PME event.
-
GPIO PME event status.
0: GPIO has no PME event.
1: GPIO has a PME event to assert. Write 1 to clear to be ready for
next PME event.
6.11.19 Keep Last State Select Register ⎯ Index F4h
Bit
Name
7
Reserved
R/W Default Description
-
-
-
6
EN_CIRWAKEUP R/W
0
Set one to enable CIR wakeup event asserted via PSOUT#.
5
EN_GPWAKEUP
R/W
0
Set one to enable GPIO wakeup event asserted via PSOUT#.
4
EN_KBWAKEUP
R/W
0
Set one to enable keyboard wakeup event asserted via PSOUT#.
3
EN_MOWAKEUP R/W
0
Set one to enable mouse wakeup event asserted via PSOUT#.
The ACPI Control the PSON_N to always on or always off or keep last
state
00 : Keep last state
10 : Always on
01 : Bypass mode.
11: Always off
2-1
0
PWRCTRL
R/W
11
VSB_PWR_LOSS R/W
0
When VSB 3V comes, it will set to 1, and write 1 to clear it
6.11.20 VDDOK Delay Register ⎯ Index F5h (powered by VBAT)
Bit
Name
R/W Default
Description
7-6
PWROK_DELAY
R/W
0
The additional PWROK delay. The unit is 100 ms.
00: no delay
01: 1X
10: 2X
11: 4X
5
RSTCON_EN
R/W
0
0: RSTCON# will assert via PWROK.
1: RSTCON# will assert via PCIRST4# and PCIRST5#.
138
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4-3
VDD_DELAY
R/W
11
The PWROK delay timing from VDD3VOK by followed setting. The
unit is 100 ms.
00 : 1X
01 : 2X
10 : 3X
11 : 4X
2
VINDB_EN
R/W
1
Enable the ATXPWGD de-bounce.
1
PCIRST_DB_EN
R/W
0
Enable the LRESET_N de-bounce.
0
Reserved
R/W
0
Reserved
6.11.21 PCIRST Control Register ⎯ Index F6h
Bit
Name
R/W Default
Description
7
S3_SEL
R/W
0
Select the KBC S3 state.
0: Enter S3 state when internal VDD3VOK signal de-asserted.
1: Enter S3 state when S3# is low or the TS3 register is set to 1.
6
PSON_DEL_EN
R/W
0
0: PSON# is the inverted of S3# signal.
1: PSON# will sink low only if the time after the last turn-off elapse at
least 4 seconds.
5
Reserved
-
-
Reserved
4
PCIRST5_GATE
R/W
1
Write “0” to this bit will force PCIRST5# to sink low.
3
PCIRST4_GATE
R/W
1
Write “0” to this bit will force PCIRST4# to sink low.
2
PCIRST3_GATE
R/W
1
Write “0” to this bit will force PCIRST3# to sink low.
1
PCIRST2_GATE
R/W
1
Write “0” to this bit will force PCIRST2# to sink low.
0
PCIRST1_GATE
R/W
1
Write “0” to this bit will force PCIRST1# to sink low.
6.11.22 Power Sequence Control Register ⎯ Index F7h (powered by VBAT)
Bit
Name
7
VDIMM_S3_ON
R/W
1
0: TIMING_1 will low during S3 state.
1: TIMING_1 will be tri-state during S3 state.
6
VDDA_S3_ON
R/W
0
0: TIMING_2 will low during S3 state.
1: TIMING_2 will be tri-state during S3 state.
5
VCORE_S3_ON
R/W
0
0: TIMING_3 will low during S3 state.
1: TIMING_3 will be tri-state during S3 state.
4
VLDT_S3_ON
R/W
0
0: TIMING_4 will low during S3 state.
1: TIMING_4 will be tri-state during S3 state.
WDT_PWROK_EN R/W
0
Set “1” to enable WDTRST# assert from PWROK pin.
3
R/W Default
Description
2
S0P5_Gate#_TRI
R/W
1
0: S0P5_Gate# will sink low in S5 state.
1: S0P5_Gate# will be tri-state in S5 state.
1
PWR_
S3P5_Gate#_TRI
R/W
1
0: S3P5_Gate# will sink low in S5 state.
1: S3P5_Gate# will be tri-state in S5 state.
0
Reserved
R/W
0
Reserved
6.11.23 LED VCC Mode Select Register ⎯ Index F8h
Bit
Name
R/W Default
Description
139
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7
6
5-4
3-2
1-0
LED_INV_DIS
LED_VCC_DS3
R/W
R/W
LED_VCC_S5_MO
R/W
DE
LED_VCC_S3_MO
R/W
DE
LED_VCC_S0_MO
R/W
DE
0
0: Default Invert signal
1: Invert disable
0
0: Disable LED_VCC deep S3 mode.
1: Enable LED_VCC deep S3 mode. LED_VCC will output 0.25Hz
clock with 75% duty when enter deep S3 state.
0
Select LED_VCC mode in S5 state. The mode is controlled by
{LED_VCC_S5_ADD, LED_VCC_S5_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
0
Select LED_VCC mode in S3 state. The mode is controlled by
{LED_VCC_S3_ADD, LED_VCC_S3_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
0
Select LED_VCC mode in S0 state. The mode is controlled by
{LED_VCC_S0_ADD, LED_VCC_S0_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
6.11.24 LED VSB Mode Select Register ⎯ Index F9h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved
6
LED_VSB_DS3
R/W
0
0: Disable LED_VSB deep S3 mode.
1: Enable LED_VSB deep S3 mode. LED_VSB will output 0.25Hz
clock with 25% duty when enter deep S3 state.
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5-4
3-2
1-0
LED_VSB_S5_MO
R/W
DE
LED_VSB_S3_MO
R/W
DE
LED_VSB_S0_MO
R/W
DE
0
Select LED_VSB mode in S5 state. The mode is controlled by
{LED_VSB_S5_ADD, LED_VSB_S5_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.
111: 0.25Hz clock with 25% duty.
0
Select LED_VSB mode in S3 state. The mode is controlled by
{LED_VSB_S3_ADD, LED_VSB_S3_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.
111: 0.25Hz clock with 25% duty.
0
Select LED_VSB mode in S0 state. The mode is controlled by
{LED_VSB_S0_ADD, LED_VSB_S0_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.
111: 0.25Hz clock with 25% duty.
6.11.25 LED Additional Mode Select Register ⎯ Index FAh
Bit
Name
7
Reserved
6
R/W Default
-
LED_VSB_S5_AD
R/W
D
Description
-
Reserved
0
Select LED_VSB mode in S5 state. The mode is controlled by
{LED_VSB_S5_ADD, LED_VSB_S5_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
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5
4
3
2
1
LED_VSB_S3_AD
R/W
D
LED_VSB_S0_AD
D
R/W
Reserved
-
LED_VCC_S5_AD
D
R/W
LED_VCC_S3_AD
D
R/W
0
Select LED_VSB mode in S3 state. The mode is controlled by
{LED_VSB_S3_ADD, LED_VSB_S3_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
0
Select LED_VSB mode in S0 state. The mode is controlled by
{LED_VSB_S0_ADD, LED_VSB_S0_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
-
Reserved
0
Select LED_VCC mode in S5 state. The mode is controlled by
{LED_VCC_S5_ADD, LED_VCC_S5_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
0
Select LED_VCC mode in S3 state. The mode is controlled by
{LED_VCC_S3_ADD, LED_VCC_S3_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
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0
LED_VCC_S0_AD
R/W
D
0
Select LED_VCC mode in S0 state. The mode is controlled by
{LED_VCC_S0_ADD, LED_VCC_S0_MODE}
000: Sink low.
001: Tri-state.
010: 0.5Hz clock.
011: 1Hz clock.
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 75% duty.
111: 0.25Hz clock with 75% duty.
6.11.26 Intel DSW Delay Select Register ⎯ Index FCh
Bit
Name
R/W
Default
7-4
Reserved
R/W
-
3-0
DSW_DELAY
R/W
7h
Description
Reserved
This is the delay time for SUS_ACK# and SUS_WARN#. Time unit is 0.5s.
6.11.27 RI De-bounce Select Register ⎯ Index FEh
Bit
Name
7
WR_TRIM_EN
R/W
0
After entry key is enabled, write “1” to enable trim operation.
6
WR_KEY_EN
R/W
0
Enable CRFD for entry data.
5
Reserved
-
-
Reserved
4
CIR_VDD_S3
R/W
0
Write “1” to emulate a S3 state for CIR.
3-2
Reserved
-
-
Reserved
0
Select RI de-bounce time.
00: reserved.
01: 200us.
10: 2ms.
11: 20ms.
1-0
RI_DB_SEL
R/W Default
R/W
Description
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7. Electrical Characteristics
7.1
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
-0.5 to 5.5
V
-0.5 to VDD+0.5
V
0 to +70
°C
-55 to 150
°C
Power Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may dversely
affect the life and reliability of the device.
7.2
DC Characteristics
(Ta = 0° C to 70° C, 3VCC = 3.3V ± 10%, VSS = 0V)
PARAMETER
Operating Voltage
Battery Voltage
Operating Current
SYM.
VDD
VBAT
ICC
Idle State Current
ISTY
Battery Current
IBAT
MIN.
3.0
2.4
TYP.
3.3
3.3
10
MAX.
3.6
3.6
UNIT
V
V
mA
CONDITIONS
3VCC=3.3V VBAT=3.3V
5
uA
3VCC=3.3V VBAT=3.3V
4
uA
3VCC=3.3V VBAT=3.3V
PARAMETER
SYM. MIN. TYP.
MAX.
UNIT
CONDITIONS
I/O12st,5v-TTL level bi-directional pin with schmitt trigger, output with12 mA sink capability, 5V
tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+12
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/O16t,u47k-TTL level bi-directional pin with 16 mA source-sink capability, internal pull-up 47k ohms
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+16
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OOD12t-TTL level bi-directional pin, Output pin with 12mA source-sink capability, and can
programming to open-drain function.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-12
-9
mA
VOL = 0.4 V
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OOD12t,5v-TTL level bi-directional pin, Output pin with 12mA source-sink capability, and can
programming to open-drain function, 5v tolerance.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
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Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-12
-9
mA
VOL = 0.4 V
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OOD8st,5v-TTL level bi-directional pin and schmitt triggrt, Open-drain output with 8mA source-sink
capability, 5v tolerance.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-8
-9
mA
VOL = 0.4 V
Output High Current
IOH
+9
+8
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OOD12st,5v-TTL level bi-directional pin and schmitt triggrt, Open-drain output with 12mA source-sink
capability, 5v tolerance.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-12
-9
mA
VOL = 0.4 V
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OOD24st,5v-TTL level bi-directional pin and schmitt triggrt, Open-drain output with 24mA source-sink
capability, 5v tolerance.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-24
-9
mA
VOL = 0.4 V
Output High Current
IOH
+9
+24
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
INst - TTL level input pin with schmitt trigger
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
INt,5v - TTL level input pin with 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
INst,5v - TTL level input pin with schmitt trigger, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
INst-u47k - TTL level input pin with schmitt trigger, internal pull-up 47k ohms
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
Input Low Voltage
Input High Voltage
Input High Leakage
Input Low Leakage
INst,lv - TTL level input pin with schmitt trigger, low level.
VIL
0.8
V
VIH
2.0
V
ILIH
+1
μA
ILIL
-1
μA
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OD12-Open-drain output with12 mA sink capability.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD12,5v-Open-drain output with12 mA sink capability, 5V tolerance.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD14,5v-Open-drain output with14 mA sink capability, 5V tolerance.
Output Low Current
IOL
-14
mA
VOL = 0.4V
OD24,5v-Open-drain output with24 mA sink capability, 5V tolerance.
Output Low Current
IOL
-24
mA
VOL = 0.4V
OD12,u10k,5v-Open-drain output with 12 mA sink capability, pull-up 10k ohms, 5V tolerance.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD16,u10k,5v-Open-drain output with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
Output Low Current
IOL
-16
mA
VOL = 0.4V
O8t,u47,5v- TTL level Output pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
Output High Current
IOH
+6
+8
mA
VOH = 2.4V
O12- Output pin with 12 mA source-sink capability.
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
O16- Output pin with 16 mA source-sink capability.
Output High Current
IOH
+16
mA
VOH = 2.4V
O18- Output pin with 18 mA source-sink capability.
Output High Current
IOH
+18
mA
VOH = 2.4V
O20- Output pin with 20 mA source-sink capability.
Output High Current
IOH
+20
mA
VOH = 2.4V
O30- Output pin with 30 mA source-sink capability.
Output High Current
IOH
+26
+30
mA
VOH = 2.4V
O12-5v- Output pin with 12 mA source-sink capability, 5V tolerance.
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
ILv/OD8-s1 - Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 8mA drive and 1mA sink
capability.
Input Low Voltage
VIL
0.6
V
Input High Voltage
VIH
0.9
V
Output High Current
IOH
+8
mA
VOH = 1.0V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0 V
I/OD12st,5v-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink
capability, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+12
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
ILv /OD12st,5v-Low level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink
capability, 5V tolerance.
Input Low Voltage
VIL
0.6
V
Input High Voltage
VIH
0.9
V
Output Low Current
IOL
+12
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
I/OD14st,5v-TTL level bi-directional pin with schmitt trigger, Open-drain output with 16 mA sink
capability, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+14
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
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I/OD16st,5v-TTL level bi-directional pin with schmitt trigger, Open-drain output with 16 mA sink
capability, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+16
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
μA
VIN = VDD
Input Low Leakage
ILIL
-1
μA
VIN = 0V
8. Ordering Information
Part Number
Package Type
Production Flow
F71869AD
128-LQFP (Green Package)
Commercial, 0°C to +70°C
9. Top Marking Specification
Fintek
F71869AD
XXXXXXX
XXXXXX.X
Fintek Logo
1st Line: Device Name Æ F71869AD, where D means the package type (128-LQFP)
2nd Line: Assembly Plant Code (x) + Assembled Year Code (x) + Week Code (xx) + Fintek Internal Code
(xx) + IC Version (x) where A means version A, B means version B, …
3rd Line: Wafer Fab Code (XXXX…XX)
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10. Package Dimensions (128-LQFP)
128 LQFP (14*14)
Feature Integration Technology Inc.
Headquarters
3F-7, No 36, Tai Yuan St.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
TEL : 886-3-5600168
FAX : 886-3-5600166
www: http://www.fintek.com.tw
Taipei Office
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 866-2-8227-8027
FAX : 866-2-8227-8037
Please note that all datasheet and specifications are subject to change without notice. All
the trade marks of products and companies mentioned in this datasheet belong to their
respective owner
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11. Application Circuit
(GND close to IC)
RSMRST#
VBAT
ATXPG_IN
VSB3V VCC3V
C58
S4#
PCIRST3#
PCIRST2#
PCIRST1#
I_3VSB
ATXPG_IN
R1
4.7k
0.1U
VCC5V
R4
R6
R2
R3
R7
R5
4.7k
2
COPEN#
DD3+
D2+
D1+
VREF
VIN6
VIN5
VDIMM(VIN4)
VDDA(VIN3)
PWOK
PSON#
S3#
PSOUT#
PSIN#
PME#
1
S3
1K
1K
1K
1K
1K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
WPT#
INDEX#
TRK0#
RDATA#
DSKCHG#
RSMRST#
PWOK
MCLK
MDAT
KCLK
KDAT
RSMRST# and PWOK pull-up
OVT#
CPU_PWGD
LED_VCC
J1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
DENSEL#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
INDEX#
MOA#
DRVA#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
F71869_10
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WDTRST#
STRAP_TIMING
LED_VSB
WDTRST#
S0P5_Gate#
RSTCON#
IBX_DAT
IBX_CLK
PECI
CIRLED#
S3_Gate#
S3P5_Gate#
SUS_WARN#/TIMING_1
SUS_ACK#/TIMING_2
5VA
STRAP_TIMING
CIRRX#
CIRTX
CIRWB#
SLP_SUS#/TIMING_4
DPWROK/TIMING_3
STRAP_TIMING
DTR1#
SOUT1#
FANCTL1
FANCTL2
FANCTL3
SOUT2
R9
1K
R10
1K
R11
1K
R12
1K
R14 X_R128 X_R129
1K
1K
1K
POWER-ON TRIP
R115
10R
CTRL1#
C6
CTRL0#
EVEN_IN#
0.1U
GA20
KBRST#
CLK_24/48M
PCICLK
VCC3V
LAD3
LAD2
LAD1
LAD0
1
GA20
KBRST#
CLK_24/48M
RTS1#
R8
1K
PIN
Function
NET Name
26
FANCTL3
FANCTL3
PWM FAN
HI
LINEAR FAN
24
FANCTL2
FANCTL2
PWM FAN
LINEAR FAN
22
FANCTL1
FANCTL1
PWM FAN
121
DTR1#
FAN40_100
LO
124
SOUT1#
Config 4E/2E
52
TIMING/GPIO
LINEAR FAN
FAN SPEED DUTY:40%
FAN SPEED DUTY:100%
4E
2E
TIMING/GPIO
TIMING
GPIO
80 PORT
COM2
5
SOUT2
STRAP_DPORT
122
RTS1#
STRAP_PROTECT
Disable UVP
Enable UVP
VSB3V
LFRAME#
SERIRQ
LDRQ#
LRESET#
IRRX
IRTX
FANCTL3
FANIN3
FANCTL2
FANIN2
FANCTL1
FANIN1
C4
0.1U 0.1UF 0.1U
C5
0.1U
R16
4.7k
S3_Gate#
S3P5_Gate#
S3_Gate# & S3P5_Gate# Pull-up
(Place capacitor close to IC)
VBAT D12
D13
DIODEVBAT
DIODE
I_3VSB
Title
Feature Integration Technology Inc.
Size
B
Date:
149
R15
4.7k
1
C3
1
1
C2
2
0.1U
2
C1
2
NC/0R
1
R140
I_3VSB
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
RDATA#
TRK0#
INDEX#
WPT#
DSKCHG#
2
DIODE3VA
1
VCC3VVCC3VVCC3VVSB3V VBAT
D11
2
DTR2#
RTS2#
DSR2#
VCC3V
SOUT2
SIN2
F71869A
GPIO15/LED_VSB/ALERT#
WDTRST#/GPIO14
S0P5_Gate#/GPIO13/BEEP
GPIO12/RSTCON#
GPIO11/PCI_RST5#/SDA
GPIO10/PCI_RST4#/SCL
PECI/SDA
CIR_LED#/SCL
S3_Gate#/GPIO05/WDTRST#
S3P5_Gate#/SLOTOCC#/GPIO04
SUS_WARN#/TIMING_1
SUS_ACK#/TIMING_2
STRAP_TIMING
CIRRX#/GPIO03
CIRTX/GPIO02
CIRWB#/GPIO01
GND
SLP_SUS#/TIMING_4
DPWROK/TIMING_3
5VSB
ERP_CTRL1#
ERP_CTRL0#
EVENT_IN0#
GA20
KBRST#
CLKIN
PCICLK
3VCC
LAD3
LAD2
LAD1
LAD0
2
VIN3(VDDA)
VIN4(VDIMM)
VIN5
VIN6
VREF
D1+(CPU)
D2+
D3+
AGND(D-)
COPEN#
VBAT
RSMRST#
PWOK
PS_ON#/GPIO47
S3#
PSOUT#/GPIO46
PSIN#/GPIO45
PME#
ATXPG_IN/GPIO44
S5#
PCIRST3#
PCIRST2#
PCIRST1#
GND
MCLK
MDATA
KCLK
KDATA
I_VSB3V
OVT#
CPU_PWGD/GPIO17
GPIO16/LED_VCC
VIN2(VLDT)
VIN1(VCORE)
3VSB
SLCT/GPIO60
PE/GPIO61
BUSY /GPIO62
ACK#/GPIO63
SLIN#
INIT#/GPIO64
ERR#/GPIO65
AFD#/GPIO66
STB#/GPIO67
PD0/GPIO70
PD1/GPIO71
PD2/GPIO72
PD3/GPIO73
PD4/GPIO74
PD5/GPIO75
PD6/GPIO76
PD7/GPIO77
GND
DCD1#
RI1#
CTS1#
DTR1#/FAN40_100
RTS1#/STRAP_PROTECT
DSR1#
SOUT1/STRAP4E_2E
SIN1
DCD2#/SEGG/GPIO20
RI2#/SEGF/GPIO21
CTS2#/SEGA/GPIO22
GPIO23/DTR2#/SEGD
GPIO24/RTS2#/SEGC
GPIO25/DSR2#/L#
3VCC
GPIO26/SOUT2/SEGB/STRAP_DPORT
GPIO27/SIN2/SEGE
GPIO30/DENSEL#
GPIO31/MOA#
GPIO32/DRVA#
GPIO33/WDATA#
GPIO34/DIR#
GPIO35/STEP#
GPIO36/HDSEL#
GPIO37/WGATE#
GPIO50/RDATA#
GPIO51/TRK0#
GPIO52/INDEX#
GPIO53/WPT#
GPIO54/DSKCHG#
GND
FANIN1
FANCTL1
FANIN2
FANCTL2
GPIO40/FANIN3
GPIO41/FANCTL3
GPIO42/IRTX
GPIO43/IRRX
LRESET#
LDRQ#
SERIRQ
LFRAM#
DCD1#
RI1#
CTS1#
DTR1#
RTS1#
DSR1#
SOUT1
SIN1
DCD2#
RI2#
CTS2#
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
FLOPPY CONN.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VLDT(VIN2)
VCORE(VIN1)
VSB3V
SLCT
PE
BUSY
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
HEADER 17X2
<Part Ref erence>
Document Number
F71869ED&FDD
Thursday , February 10, 2011
Rev
2.0
Sheet
1
of
8
Oct., 2011
V0.19P
F71869A
RN1
RN2
RN3
D1
1
VCC5V
VCC5V
1N5819
FOR LEKAGE TO POWER
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
RI1#
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RN4
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R
R22
2.7K
RN5
1
3
5
7
STB#
AFD#
INIT#
SLIN#
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
33-8P4R
RN6
PD0
PD1
PD2
PD3
2
4
6
8
33-8P4R
RN7
1
3
5
7
PD4
PD5
PD6
PD7
2
4
6
8
33-8P4R
ERR#
ACK#
BUSY
PE
SLCT
C7
180pC16
C8
C9
C10
180p
180p
180p
180p
C17
C18
C19
180p
180p
180p
180p
C11
C20
C12
180p
180p
C21
180p
180p
U1
VCC
1
+12V
RY 1
RY 2
RY 3
DA1
DA2
RY 4
DA3
RY 5
2
3
4
5
6
7
8
9
RA1
RA2
RA3
DY 1
DY 2
RA4
DY 3
RA9
GND
10
-12V
VCC3V
+12V
GND
RIN1
DTRN1
CTSN1
SOUTN1
RTSN1
SINN1
DSRN1
DCDN1
RIN1
CTSN1
DSRN1
RTSN1
DTRN1
SINN1
SOUTN1
DCDN1
5
9
4
8
3
7
2
6
1
P1
R17
4.7K
UART DB9
-12V
J2
UART
VCC5V
RI2#
CTS2#
DSR2#
RTS2#
DTR2#
SIN2
SOUT2
DCD2#
20
19
18
17
16
15
14
13
12
11
C15
180p
C23 180p
180p
R19
4.7K
R20
4.7K
R21
4.7K
DCD1#
RI1#
CTS1#
DSR1#
SIN1
If you do not use the UART port 1,
please pull-up these pin to VCC3V.
1 PORT INTERFACE
U2
VCC
+12V
RY 1
RY 2
RY 3
DA1
DA2
RY 4
DA3
RY 5
RA1
RA2
RA3
DY 1
DY 2
RA4
DY 3
RA9
GND
-12V
1
2
3
4
5
6
7
8
9
10
+12V
GND
RIN2
DTRN2
CTSN2
SOUTN2
RTSN2
SINN2
DSRN2
DCDN2
RIN2
CTSN2
DSRN2
RTSN2
DTRN2
SINN2
SOUTN2
DCDN2
5
9
4
8
3
7
2
6
1
P2
R23
4.7K
UART DB9
-12V
C13
C22
R18
4.7K
VCC3V
DB25
(FEMALE)
C14
19
18
17
16
15
14
13
12
11
2
4
6
8
1
3
5
7
20
UART
2
R24
4.7K
R25
4.7K
R26
4.7K
R27
4.7K
DCD2#
RI2#
CTS2#
DSR2#
SIN2
If you do not use the UART port 2,
please pull-up these pin to VCC3V.
PORT INTERFACE
180p
RING-IN Wake-up is
supported by F71869A
PARALLEL PORT INTERFACE
VSB5V
J3
1
2
3
If you do not use the KBC,
please pull-up these pin to VSB5V.
F1
CON3
VCC5V
R28
4.7K
R29
4.7K
F2
M-DIN_6-R JS1
FUSE
1
2
3
6
5
4
R30
4.7K
R31
4.7K
L1
MDAT
KDAT
FB
L3
MCLK
M-DIN_6-R JS2
FUSE
1
2
3
FB
IRTX
FB
IRRX
1
2
3
4
5
C24
FB
C25
C26
C27
C28
C29
C30
100P
100P
0.1U
100P
100P
0.1U
PS2 MOUSE INTERFACE
JP1
L2
L4
KCLK
VCC5V/3V
6
5
4
HEADER 5
0.1U
Title
PS2 KEYBOARD INTERFACE
150
IR INTERFACE
Size
B
Date:
Feature Integration Technology Inc.
Document Number
Printer &UART
Thursday , February 10, 2011
Rev
2.0
Oct., 2011
V0.19P
Sheet
2
of
8
F71869A
R32
1K
VBAT
VCORE(VIN1)
C31
100p
VCORE
D+
D1+
R33
C32
3300P
from CPU
D-
DVLDT(1.5V)
R131
10K
2M
C35
1000P
D2+
R132 10K
C33
R36
VDDA
3300P
Q1
PNP
3906
for
SYSTEM
Q13
PNP
3906
for
SYSTEM
CASE OPEN CIRCUIT
D-
10K
VDDA(VIN3)
SW1
1
2
COPEN#
VLDT(VIN2)
C34
100p
DIODE SENSING CIRCUIT
100p
VDIMM(VIN4)
C37
100p
5VSB( for Intel)
R40
R42
R44
3300P
8.6K
VIN5
C38
100p
R45
20K
VIN6
C39
100p
R47
R41
4.7K
DIODE SENSING CIRCUIT
VREF
R43
RT1
10K 1%
VREF
10K 1%
THERMISTOR
R46
RT2
10K 1%
VSB5V
(for system)
VSB3V
10K 1%
T
RT3
R114 10K 1%
THERMISTOR
D3+
(for system)
R48
330
R49
4.7K
THERMISTOR SENSING CIRCUIT
VREF
D2
LED
(for system)
10K 1%
THERMISTOR
D2+
P_LED
Q2
NPN
LED_VCC
2.9K
The best voltage input level is about 1V.
R39
330
D-
D1+
+12V
VSB5V
VSB3V
10K
20K
5VCC
C59
T
VDIMM
D3+
10K
10K
T
R37
R38
SUS_LED
Q3
NPN
LED_VSB
D3
LED
must scale the voltage under 2.048V to VIN
THERMISTOR SENSING CIRCUIT
If use force mode voltage protect, the
voltage must to scale become1.5V to VIN.
VOLTAGE SENSING.
LED
Temperature Sensing
VCC3V
R50
4.7K
OVT#
Title
OVT# PULL-UP
Feature Integration Technology Inc.
151
Size
B
Date:
Document Number
Hardware Monitor
Friday , July 02, 2010
Oct., 2011
V0.19P
3
of
Sheet
Rev
2.0
8
F71869A
12V
+12V
8
R51
4.7K
VCC5V
D4
1N4148
2
FANCTL1
4 HEADER
C40
4
3
2
1
+
R57 100
R53
4.7K
47U
+
R55
27K
FANIN1
C43
0.1U
JP2
D5
1N4148
1
R54
4.7K
LM358
JP3
R59 10K
R58
10K
(4 PIN FAN Control)
PMOS
Q4
4
R52
10K
FANCTL1
3
U3A
C41
47u
R56 27K
3
2
1
C42
CON3
R61
3.9K
FANIN1
0.1u R60
10K
DC FAN Control with OP 1
PWM FAN 1
SPEED CONTROL
12V
+12V
R63
4.7K
4.7K
8
R62
4.7K
D6
1N4148
R65
4.7K
FANCTL2
R69
330
C44
Q7
+
MOSFET N
2N7002 47U
5
R66
4.7K
JP4
R70
3
2
1
27K
SPEED CONTROL
FANCTL3
330
C48
Q10
+
MOSFET N
2N7002 47U
R68 27K
3
2
1
C46
CON3
FANIN2
0.1u R73
10K
DC FAN Control with OP 2
12V
8
D8
1N4148
JP6
3
2
1
3
R79
4.7K
2
FANCTL3
R82
HEADER 3
27K
+
PMOS
Q8
U4A
D9
1N4148
1
-
R80
4.7K
LM358
JP7
FANIN3
R83
10K
R85 10K
C51
0.1U
R87
3.9K
PWM FAN 3
C45
47u
R76
4.7K
Q9
PNP
R78
4.7K
R81
JP5
4.7K
4.7K
R67
4.7K
LM358
R74
3.9K
4
R77
VCC3V
D7
1N4148
7
R72 10K
C47
0.1U
PMOS
Q5
-
FANIN2
+12V
R75
+
R71
10K
HEADER 3
PWM FAN 2
6
FANCTL2
4
R64
VCC3V
Q6
PNP
U3B
SPEED CONTROL
C49
47u
R84 27K
3
2
1
C50
CON3
FANIN3
0.1u R86
10K
DC FAN Control with OP 3
FAN CONTROL FOR PWM OR DC
Title
Size
B
152
Date:
Feature Integration Technology Inc.
Document Number
FAN Control
Friday , April 09, 2010
Rev
2.0
Oct., 2011
V0.19P
Sheet
4
of
8
F71869A
VDDIO
R88
300
VCC3V
R89
300
R90
300
PECI
SIC
CIRLED#
SID
PECI
PECI_Client
R92
100K
(avoid pre-bios floating)
R91
300
IBX_DAT
IBX_CLK
SMLINK[1]
Client
Client
AMD_TSI
INTEL IBEX
Client
INTEL PECI
VSB3V
R93
4.7K
VCC3V
R94
4.7K
VCC3V
R95
4.7K
VCC3V
2.5V
R96
4.7K
TIMING_1
TIMING_2
TIMING_3
TIMING_4
R97
4.7K
CPU_PWRGD
CPU_PWRGD Pull-Up
Power Sequence Pull-up
SLP_S3#
PWROK
TIMING_1(VDIMM_EN)
TIMING_2(VDDA)
TIMING_3(VCORE_EN)
TIMING_4(VLDT_EN)
Title
Size
B
Date:
153
Feature Integration Technology Inc.
Document Number
AMDSI/PECI
Friday , April 15, 2011
Rev
2.0
Sheet
5
of
8
Oct., 2011
V0.19P
F71869A
5VA
5VA
R98
10K
MOSFET P
CTRL0#
R101 10K
R102 1K
10K
5VSB
Q11
R100 10K
R99
C52
10u
SLP_SUS#/TIMING_4
EVENT_IN
PSIN#
PSON#
C53
1u
C54
10u
SUS_ACK#/TIMING_2
FOR INTEL
R
R107
FOR AMD
R
R108
FOR INTEL
R109
FOR AMD
R
R110
FOR INTEL
R
R113
FOR AMD
R
R126
SLP_SUS#
TIMING_4
SUS_ACK#
TIMING_2
VSB3V
5VA
MOSFET P
5VUSB
Q12
R106 1K
C56
1u
CTRL1#
R105 10K
C55
10u
R104 10K
R103 10K
DPWROK/TIMING_3
PSOUT#
PME#
SUS_WARN#/TIMING_1
R
R111
FOR AMD
R
R112
TIMING_3
SUS_WARN#
TIMING_1
DSW
C57
10u
Eup Control VSB
FOR INTEL
DPWROK
Eup ACPI PULL UP
R129
0
R130
0
SUS_WARN#(CHIPSET)
SUS_WARN#
Select SUS_WARN#
V3A
5V_DUAL
to Chipset or 5V_DUAL
V3A
R128 10K
R127 10K
SUS_ACK#
DPWROK
DSW PULL UP
Title
<Title>
Size
B
154
Date:
Document Number
<Doc>
Friday , June 25, 2010
Rev
2.0
of
Oct.,6 2011
V0.19P
Sheet
8
F71869A
U8
DCD2#
CTS2#
RI2#
DSR2#
R138 100
1
2
3
4
5
SEGG
NC
SEGA
SEGF
L#
H#
SEGB
SEGC
SEGE
SEGD
10
9
8
7
6
R139 100
H#
SOUT2
RTS2#
SIN2
DTR2#
Dual Digit Display
VCC3V
D
R125
Q17
MOSFET N
G
S
DSR2#
4.7K
H#
80 PORT 1 (output by COM2 interface)
Title
Size
A
Date:
Feature Integration Technology Inc.
Document Number
<Doc>
Rev
<Rev Code>
Friday , April 09, 2010
155
Sheet
1
of
1
Oct., 2011
V0.19P
F71869A
VSB5V
VSB3V
R121
0R
VCC3V
R122
0R
C61
R118
1.8K
2
4
2
3
GP1UD260Y K
Q15
NPN3904
R117
100
Long Rang IR Receiver
choose power and capacitance by IR receiver
R123100
Q14
2N7002
1
C60 10nF
Wide band IR Receiver
J5
1
VSB3V
2
3
R124
330
1
TX1 JACK
D10
LED
2
CIRTX
R116330
R120
12K
Q16
LTR-301
1
case
1
CIRRX#
3
GND
OUT
R119
330
CIRWB#
U7
VCC
C62
0.1u
2
0.1u
C63
10u
CIRLED#
TX PORT
CIRTX
CIRLED#
CIRWB#
CIRTX
CIRLED#
CIRWB#
IR LED
Title
156
Size
A
Date:
Feature Integration Technology Inc.
Document Number
<Doc>
Friday , April 09, 2010
Rev
Oct.,
<Rev Code>
Sheet
1
of
1
2011
V0.19P