TI DIX9211PTR

DIX9211
www.ti.com
SBAS519 – SEPTEMBER 2010
216-kHz Digital Audio Interface Transceiver (DIX)
Check for Samples: DIX9211
FEATURES
1
• Integrated DIX and Signal Routing:
– Asynchronous Operation (DIR, DIT)
– Mux and Routing of PCM Data:
– I2S™, Left-Justified, Right-Justified
– Multipurpose Input/Output Pins
• Digital Audio I/F Receiver (DIR):
– 24-bit, 216-kHz Capable
– 50-ps Ultralow Jitter
– Non-PCM Detection (IEC61937, DTS-CD/LD)
– 12x S/PDIF Input Ports:
– 2x Coaxial S/PDIF Inputs
– 10x Optical S/PDIF Inputs
• Digital Audio I/F Transmitter (DIT):
– 24-Bit, 216-kHz Capable
– 24-Bit Data Length
– 48-Bit Channel Status Buffer
– Synchronous/Asynchronous Operation
• Routing Function:
– Input: 3x PCM, 1x DIR
– Output: Main Out, Aux Out, DIT
– Multi-Channel (8-Ch) PCM Routing
•
23456
•
•
•
Other Function Features:
– Power Down (Pin and Register Control)
– PCM Port Sampling Frequency Counter
– GPIO and GPO
– OSC for External Crystal (24.576 MHz)
– SPI™, I2C™ or Hardware Control Modes
Power Supply:
– 3.3 V (2.9 V to 3.6 V) for DIX, All Digital
Operating Temperature: –40°C to +85°C
Package: 48-Pin LQFP
APPLICATIONS
•
•
•
•
Home Theater and AVR Equipment
Television and Soundbars
Musical Instruments, Recording, and
Broadcast
High-Performance Soundcards
DESCRIPTION
The DIX9211 is a complete analog and digital
front-end for today's multimedia players and
recorders.
The DIX9211 integrates an S/PDIF transceiver with
up to 12 multiplexed inputs and 3x PCM inputs to
allow other audio receivers to be multiplexed along
with the analog and S/PDIF signals to a digital signal
processor (DSP).
1
2
3
4
5
6
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AC-3 is a trademark of Dolby Laboratories.
SPI is a trademark of Motorola, Inc.
I2S, I2C are trademarks of NXP Semiconductors.
TOSLINK is a trademark of Toshiba Corp.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
DIX9211
SBAS519 – SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
DIX9211
LQFP-48
PT
OPERATING
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
DIX9211
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
DIX9211PT
Tray, 250
DIX9211PTR
Tape and Reel, 1000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DIX9211
UNIT
–0.3 to +4.0
V
Supply voltage differences: VCC, VDD
±0.1
V
Ground voltage differences: AGND, DGND, GNDRX
±0.1
V
RXIN2, RXIN3, RXIN4/ASCKI0, RXIN5/ABCKI0, RXIN6/ALRCKI0,
RXIN7/ADIN0, MC/SCL, MDI/SDA, MDO/ADR, MS/ADR1, RST
–0.3 to +6.5
V
MPIO_A0-A3, MPIO_B0-B3, MPIO_C0-C3
–0.3 to +6.5
V
RXIN0, RXIN1 (For S/PDIF TTL / OPTICAL input)
–0.3 to +6.5
V
MODE
–0.3 to +4.0
V
–0.3 to (VDDRX + 0.3) < +4.0
V
–0.3 to (VDD + 0.3) < +4.0
V
Supply voltage
Digital input voltage
VCC, VDD, VDDRX
RXIN0, RXIN1 (For S/PDIF Coaxial Input Only)
Analog input voltage XTI, XTO
FILT
–0.3 to (VCC + 0.3) < +4.0
V
±10
mA
Ambient temperature under bias
–40 to +125
°C
Storage temperature
–55 to +150
°C
Junction temperature
+150
°C
Package temperature (reflow, peak)
+260
°C
Input current (any pins except supplies)
(1)
2
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SBAS519 – SEPTEMBER 2010
THERMAL INFORMATION
DIX9211
THERMAL METRIC (1)
PT PACKAGE
UNITS
48 PINS
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
0.7
qJB
Junction-to-board thermal resistance
29.6
yJT
Junction-to-top characterization parameter
18.9
yJB
Junction-to-board characterization parameter
30.0
qJCbot
Junction-to-case (bottom) thermal resistance
N/A
(1)
61.0
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
MIN
NOM
MAX
DIR analog supply voltage, VCC
2.9
3.3
3.6
V
ALL digital supply voltage, VDD
2.9
3.3
3.6
V
Coaxial amplifier supply voltage, VDDRX
2.9
3.3
3.6
V
Digital input interface level
TTL-compatible
DIR, DIT, and Routing sampling frequency
Digital input/output clock frequency
UNIT
DIR, DIT, and Routing system clock frequency
7
216
kHz
0.896
55.296
MHz
XTI input clock frequency
24.576
MHz
Digital output load capacitance
Except SCKO
20
pF
Digital output load capacitance
SCKO
10
pF
10
pF
+85
°C
MODE pin capacitance
Operating free-air temperature
–40
+25
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DIX9211
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ELECTRICAL CHARACTERISTICS: GENERAL
All specifications at TA = +25°C, and VCC = VDD = VDDRX = 3.3 V, unless otherwise noted.
DIX9211
TEST CONDITIONS (1)
PARAMETER
MIN
TYP
MAX
UNIT
DIGITAL INPUT/OUTPUT
DATA FORMAT
I2S, Left-Justified, Right-Justified
Audio data interface format
Audio data word length
16, 24
Audio data format
fS
Bits
MSB first, twos complement
Sampling frequency, DIR
7
216
kHz
Sampling frequency, DIT
7
216
kHz
Sampling frequency, Routing
7
216
kHz
2.0
5.5
VDC
0.8
VDC
VCC
VDC
0.3 VCC
VDC
VDDRX
VDC
0.3 VDDRX
VDC
INPUT LOGIC
VIH
(2) (3)
VIL
(2) (3)
VIH
(4)
VIL
(4)
VIH
(5)
VIL
(5)
IIH
(2) (4)
IIL
(2) (4)
IIH
(3)
IIL
(3)
IIH
(5)
IIL
(5)
Input logic level
0.7 VCC
Input logic level (XTI pin)
0.7 VDDRX
Input logic level (RXIN0/1 pins)
Input logic current
Input logic current (RST pin)
Input logic current (RXIN0/1
pins)
VIN = VDD or VCC
±10
mA
VIN = 0 V
±10
mA
100
mA
±10
mA
165
300
mA
–165
–300
mA
VIN = VDD
65
VIN = 0 V
VIN = VDDRX
VIN = 0 V
OUTPUT LOGIC
VOH
(6)
VOL
(6)
VOH
(7)
VOL
(7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
Output logic level
Output logic level
IOUT = –4 mA
2.8
IOUT = 4 mA
IOUT = –4 mA
IOUT = 4 mA
VDC
0.5
0.85 VCC
VDC
VDC
0.15 VCC
VDC
PLL lock-up time varies with ERROR release wait time setting (Register 23h/ERRWT). Therefore, lock-up time in this table shows the
value at ERRWT = 11 as the shortest time setting.
Pins: MPIO_A0-A3, MPIO_B0-B3, MPIOC0-C3, RXIN2-RXIN7, MC/SCL, MDI/SDA, MDO/ADR0, MS/ADR1
Pin: RST
Pin: XTI
Pins: RXIN0, RXIN1. Input impedance of RXIN0 and RXIN1 is 20 kΩ (typical). COAX amplifiers are powered on by Register
34h/RX0DIS and RX1DIS = 0. At power down by Register 34h/RX0DIS and RX1DIS= 1 (default), RXIN0 and RXIN1 are internally tied
high.
Pins: MPIO_A0-A3, MPIO_B0-B3, MPIO_C0-C3, SCKO, BCK, LRCK, DOUT, MPO0-1, ERROR/INT0, NPCM/INT1.
Pin: XTO.
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SBAS519 – SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS: GENERAL (continued)
All specifications at TA = +25°C, and VCC = VDD = VDDRX = 3.3 V, unless otherwise noted.
DIX9211
PARAMETER
TEST CONDITIONS (1)
MIN
TYP
MAX
UNIT
2.9
3.3
3.6
VDC
2.9
3.3
3.6
VDC
2.9
3.3
3.6
VDC
POWER-SUPPLY REQUIREMENTS
VCC
VDD
Voltage range
VDDRX
fS = 48 kHz / DIR, fS = 48 kHz / DIT
ICC
Supply current
4.5
fS = 192 kHz / DIR, fS = 192 kHz / DIT
Full power down, RST = low
fS = 48 kHz / DIR, fS = 48 kHz / DIT
IDD
Supply current
IDDRX (8)
Supply current
13
150
350
12
fS = 192 kHz / DIR, fS = 192 kHz / DIT
26
38
150
350
fS = 48 kHz / DIR, fS = 48 kHz / DIT
3.2
fS = 192 kHz / DIR, fS = 192 kHz / DIT
3.2
4.8
0
30
fS = 48 kHz / DIR, fS = 48 kHz / DIT
mA
mA
mA
Full power down, RST = low
Full power down, RST = low
Power dissipation
mA
7
mA
mA
mA
mA
mA
75
mW
fS = 192 kHz / DIR, fS = 192 kHz / DIT
120
mW
Full power down, RST = low
1.0
mW
TEMPERATURE RANGE
Operating temperature
(8)
–40
+85
°C
Two coaxial amplifiers are powered on by Register 34h/RX1DIS and Register 34h/RX0DIS.
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ELECTRICAL CHARACTERISTICS: Digital Audio I/F Receiver (DIR)
All specifications at TA = +25°C, and VCC = VDD = VDDRX = 3.3 V, unless otherwise noted.
DIX9211
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIR, COAXIAL INPUT AMPLIFIER (RXIN0 and RXIN1)
Input resistance
20
Input voltage
kΩ
0.2
Input hysteresis
VPP
50
Input sampling frequency
mV
7
216
kHz
28
108
kHz
216
kHz
100
ms
DIR, BIPHASE SIGNAL INPUT and PLL
Input biphase sampling
frequency range
Normal mode
Wide mode
7
Input sampling frequency
accuracy
IEC60958-3 (2003-01)
Level III (±12.5%)
Jitter tolerance
IEC60958-3 (2003-01)
IEC60958-3
PLL lock up time (1)
From biphase signal detection to error out
release (ERROR = L)
DIR, RECOVERED CLOCK and DATA
Serial audio data width
System clock frequency
16
24
Bits
128fS
0.896
27.648
MHz
256fS
1.792
55.296
MHz
512fS
3.584
55.296
MHz
Bit clock frequency
64fS
0.448
13.824
MHz
LR clock frequency
fS
7
216
kHz
System clock jitter
fS = 48 kHz, SCKO = 256fS, measured
period jitter
100
ps, rms
System clock duty cycle
50% reference
±5
±5
%
7
216
kHz
128fS
0.896
27.648
MHz
256fS
1.792
55.296
MHz
50
DIT
Output biphase sampling
frequency
Input system clock frequency
512fS
3.584
55.296
MHz
Input bit clock frequency
64fS
0.448
13.824
MHz
Input LR clock frequency
fS
7
216
kHz
OSCILLATOR CIRCUIT, XTI and XMCKO CLOCK
XTI source clock frequency
24.576
Frequency accuracy
–100
XTI input clock duty cycle
45
XMCKO frequency
XMCKO output duty cycle
MHz
100
55
24.576
50% reference
ppm
%
MHz
±5
±5
%
PCM OUTPUT PORT (SCKO, BCK, LRCK, DOUT)
System clock frequency
128fS / 256fS / 512fS
0.896
55.296
MHz
Bit clock output frequency
64fS
0.448
13.824
MHz
LR clock output frequency
fS
7
216
kHz
ROUTING
(1)
6
System clock frequency
128fS / 256fS / 512fS
0.896
55.296
MHz
Bit clock output Frequency
64fS
0.448
13.824
MHz
LR clock output frequency
fS
7
216
kHz
PLL lock-up time varies with ERROR release wait time setting (Register 23h/ERRWT). Therefore, lock-up time in this table shows the
value at ERRWT = 11 as the shortest time setting.
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SBAS519 – SEPTEMBER 2010
PIN CONFIGURATIONS
RSV2
RSV2
RSV1
RSV1
RSV2
FILT
VCC
AGND
XTO
XTI
GNDRX
RXIN0
PT PACKAGE
LQFP-48
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
MPIO_A1
4
33
RXIN2
MPIO_A2
5
32
RXIN3
MPIO_A3
6
31
RXIN4/ASCKIO
MPIO_C0
7
30
RXIN5/ABCKIO
MPIO_C1
8
29
RXIN6/ALRCKIO
MPIO_C2
9
28
RXIN7/ADIN0
MPIO_C3
10
27
MODE
MPIO_B0
11
26
MS/ADR1
MPIO_B1
12
25
MC/SCL
13
14
15
16
17
18
19
20
21
22
23
24
MDI/SDA
RST
MDO/ADR0
34
DVDD
3
DGND
MPIO_A0
SCKO
RXIN1
BCK
35
LRCK
2
DOUT
NPCM/INT1
MPO1
VDDRX
MPO0
36
MPIO_B3
1
MPIO_B2
ERROR/INT0
PIN FUNCTIONS
PIN
NAME
I/O
5-V
TOLERANT
1
ERROR/INT0
O
No
DIR Error detection output / Interrupt0 output
2
NPCM/INT1
O
No
DIR Non-PCM detection output / Interrupt1 output
3
MPIO_A0
I/O
Yes
Multipurpose I/O, Group A (1)
4
MPIO_A1
I/O
Yes
Multipurpose I/O, Group A (1)
5
MPIO_A2
I/O
Yes
Multipurpose I/O, Group A (1)
6
MPIO_A3
I/O
Yes
Multipurpose I/O, Group A (1)
7
MPIO_C0
I/O
Yes
Multipurpose I/O, Group C (1)
8
MPIO_C1
I/O
Yes
Multipurpose I/O, Group C (1)
9
MPIO_C2
I/O
Yes
Multipurpose I/O, Group C (1)
10
MPIO_C3
I/O
Yes
Multipurpose I/O, Group C (1)
11
MPIO_B0
I/O
Yes
Multipurpose I/O, Group B (1)
12
MPIO_B1
I/O
Yes
Multipurpose I/O, Group B (1)
13
MPIO_B2
I/O
Yes
Multipurpose I/O, Group B (1)
14
MPIO_B3
I/O
Yes
Multipurpose I/O, Group B (1)
15
MPO0
O
No
Multipurpose output 0
NO.
(1)
DESCRIPTION
Schmitt trigger input
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PIN FUNCTIONS (continued)
PIN
NO.
(2)
(3)
(4)
(5)
8
NAME
I/O
5-V
TOLERANT
DESCRIPTION
16
MPO1
O
No
Multipurpose output 1
17
DOUT
O
No
Main output port, serial digital audio data output
18
LRCK
O
No
Main output port, LR clock output
19
BCK
O
No
Main output port, Bit clock output
20
SCKO
O
No
Main output port, System clock output
21
DGND
–
–
Ground, for digital
22
DVDD
–
–
Power supply, 3.3 V (typ.), for digital
23
MDO/ADR0
I/O
Yes
Software control I/F, SPI data output / I2C slave address setting0 (2)
24
MDI/SDA
I/O
Yes
Software control I/F, SPI data input / I2C data input/output (2) (3)
25
MC/SCL
I
Yes
Software control I/F, SPI clock input / I2C clock input (2)
26
MS/ADR1
I
Yes
Software control I/F, SPI chip select / I2C slave address setting1 (2)
27
MODE
I
No
Control mode setting, (see the Serial Control Mode section, Control Mode Pin Setting)
28
RXIN7/ADIN0
I
Yes
Biphase signal, input 7 / AUXIN0, serial audio data input (2)
29
RXIN6/ALRCKI0
I
Yes
Biphase signal, input 6 / AUXIN0, LR clock input (2)
30
RXIN5/ABCKI0
I
Yes
Biphase signal, input 5 / AUXIN0, bit clock input (2)
31
RXIN4/ASCKI0
I
Yes
Biphase signal, input 4 / AUXIN0, system clock input (2)
32
RXIN3
I
Yes
Biphase signal, input 3 (2)
33
RXIN2
I
Yes
Biphase signal, input 2 (2)
34
RST
I
Yes
Reset Input, active low (2) (4)
35
RXIN1
I
Yes
Biphase signal, input 1, built-in coaxial amplifier
36
VDDRX
–
–
37
RXIN0
I
Yes
38
GNDRX
-
-
39
XTI
I
No
Oscillation circuit input for crystal resonator or external XTI clock source input (5)
40
XTO
O
No
Oscillation circuit output for crystal resonator
41
AGND
–
–
Ground, for PLL analog
42
VCC
–
–
Power supply, 3.3 V (typ.), for PLL analog
43
FILT
O
No
44
RSV2
–
–
Reserved; left open
45
RSV1
–
–
Reserved; connect to ground
46
RSV1
–
–
Reserved; connect to ground
47
RSV2
–
–
Reserved; left open
48
RSV2
–
–
Reserved; left open
Power supply, 3.3 V (typ.), for RXIN0 and RXIN1.
Biphase signal, input 0, built-in coaxial amplifier
Ground, for RXIN
External PLL loop filter connection terminal; must connect recommended filter
Schmitt trigger input
Open-drain configuration in I2C mode
Onboard pull-down resistor (50 kΩ, typical)
CMOS Schmitt trigger input
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BLOCK DIAGRAM
FILT
AUXIN0
AUTO
RXIN0
RXIN0
RXIN1
RXIN1
RXIN2
RXIN2
AUXIN0
RXIN3
RXIN3
AUXIN1
RXIN4/ASCKI0
RXIN4
AUXIN2
RXIN5/ABCKI0
RXIN5
RXIN6/ALRCKI0
RXIN6
RXIN7/ADIN0
RXIN7
DIR
RXIN7
SCKO
DIR
XTI
PLL
Main
Output
Port
DOUT
Lock: DIR
Unlock: XTI
Clock/Data
Recovery
BCK
LRCK
DOUT
SCKO/BCK/LRCK
AUTO
DIR
MPIO_A0
RXIN8
MPIO_A1
RXIN9
MPIO_A2
MPIO_A
Selector
MPIO_A3
XTI
Lock
Detection
DIT
AUXIN0
RXIN10
AUXIN1
RXIN11
RECOUT0
DITOUT
RECOUT1
AUXIN2
RECOUT0
RECOUT1
DITOUT
MPO0
MPO0/1
Selector
MPO1
AUTO
MPIO_C0
DIR
MPIO_C1
XTI
MPIO_C2
MPIO_C
Selector
MPIO_B0
MPIO_B1
AUXOUT
AUXIN0
AUXIN1
MPIO_C3
AUXIN1
MPIO_B
Selector
AUXIN2
MPIO_B2
MPIO_B3
XTI Clock
(SCK/BCK/
LRCK)
Divider
XTI
XTO
OSC
XMCKO
(To MPIO_A and MPO0/1)
XMCKO
Divider
Register
MC/SCL
MDI/SDA
MDO/ADR0
Secondary BCK/LRCK
Divider
Selector
2
SPI/I C
Interface
Function
Control
DIR CS
(48-Bit)
DIR PC
and PD
DIR fS
Calculator
GPIO/GPO
Data
DIR CS
(48-Bit)
DIR
Interrupt
All Port fS
Calculator
MS/ADR1
RST
MODE
Power Supply
Reset
and
Mode Set
DIR
Analog
RSV1
RSV2
VCC
AGND
DIR
Analog
VDDRX GNDRX
All
Digital
DVDD
SBCK/SLRCK
(to MPIO_A)
EXTRA DIR
FUNCTIONS
Error Detection
Non-PCM Detection
fS Calculator
Flags
DTS-CD/LD Detection
Validity Flag
User Data
Channel Status Data
BFRAME Detection
Interrupt System
ERROR/INT0
NPCM/INT1
MPIO_A
MPIO_B
MPIO_C
MPO0
MPO1
DGND
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OVERVIEW
Introduction
The DIX9211 is an analog and digital front-end device for any media player/recorder. It integrates a 216-kHz
Digital Audio Transceiver (DIX) and multiple PCM (I2S, Left-Justified, Right-Justified) interfaces. Additionally, the
device integrates a router that allows any source (DIR or PCM) to be routed to one of three outputs (2x PCM and
DIT), thus significantly reducing the number of external components required to route sources to the core DSP.
Each audio interface of the DIX9211 (that is, the DIT and DIR) can operate asynchronously at different sampling
rates, allowing an analog source to be sampled at 96 kHz and to be switched over to an S/PDIF source driving
encoded data at 48 kHz.
The DIX9211 also features a power down function that can be set via hardware pins and registers, ensuring that
the system minimizes power consumption during standby.
Digital Audio Interface Receiver (DIR)
Up to 12 single-ended S/PDIF input pins are available on the DIX9211 DIR module. Two of the 12 S/PDIF inputs
integrate coaxial amplifiers; the other inputs are designed to be directly connected to CMOS sources (up to +5
V), or standard S/PDIF optical modules.
The DIR module outputs the first 48 bits of channel status data from each frame into specific registers that can
be read via the control interface. In addition, the DIR can detect non-PCM data (such as compressed
multi-channel data) by looking at channel status bits, burst preambles and DTS-CD/LD. When the DIR detects
non-PCM audio data, its status can be configured to the NPCM pin (pin 2). Control of pin 2 (NPCM or INT1) is
set by register 2Bh.
When the DIR encounters an error (for example, when it loses a lock), an error signal can be configured and
sent to the ERROR pin (pin 1). Control of pin 1 (ERROR or Int0) is set by Register 20h. Preamble data PC and
PD (typically used to transmit format information such as Digital Theater Sound, or DTS, or AC-3™ data) can be
read from registers Register 3Ah through Register 3Dh. For more information, see the audio data standard
IEC61937.
The DIX9211 has two interrupt pins (INT0 and INT1) that are shared with other functions (NPCM and ERROR).
The interrupt pins, when configured, can be used for operations such as interrupt transmissions to the DSP (for
example, instructing the DSP where the start of the frame is, etc.). Eight different factors can drive the interrupt.
For more details, see Register 2Ch and Register 2Dh. The interrupt source can also be stored in a register to be
read by a DSP, if required.
When switching from one source to the DIR and vice-versa, additional circuitry in the DIR helps continuity
between the crystal clock source and an internal phase-locked loop (PLL). During a clock source switch, a clock
transition signal can be output that can then be used by the processor to respond accordingly (such as
temporarily muting the output).
An integrated sample rate calculator in the DIR can read and detect both the incoming data rate of the S/PDIF
input as well as the sample rate information bits that are within the channel status data.
The DIX9211 has an internal clock divider that changes its system clock (SCK) output rate in order to maintain
synchronization between the incoming clock and the receiver (based on the autodetector of the incoming data
rate). For example, if the user switches from a 96-kHz source to a 48-kHz source, the divider automatically
detects the switch and changes the clock dividing ratio to ensure that the subsequent DSP continues to receive
the same system clock.
The DIX9211 also has two output ports for the DIR output. The primary output is available from the Main Port
and/or MPIO_B; the secondary port is available through MPIO_A. The dividing ratio of BCK and LRCK for the
primary output is defined by the DIR. The dividing ratio for the second output (normally taken from MPIO_A) is
defined by Register 32h and Register 33h.
When the PLL is locked, the secondary clock source automatically selects the PLL clock (256fS). Otherwise, the
XTI clock source is selected. Register 32h should be used for dividing in the lock status (that is, the PLL source).
When unlocked, Register 33h should be used (the XTI source).
The DIX9211 has two RECOUT signals that can be routed to the MPO port. The respective sources can be
drawn from one of the 12 S/PDIF inputs, or the DIT module.
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Channel status, user data, and valid audio data from the S/PDIF stream can be found in various registers or
routed to MPIO pins. In addition, the block start signal can be routed to an I/O pin, so that any postprocessing
DSP can be informed of the start of a frame for decoding data and so forth.
The DIR module in the DIX9211 complies with these digital audio I/F standards:
• S/PDIF
• IEC60958 (formerly IEC958)
• JEITA CPR-1205 (formerly EIAJ CP-1201/340)
• AES3
• EBU Tech 3250 (also known as AES/EBU)
In addition, the DIR Module within the DIX9211 also meets and exceeds jitter tolerance specifications defined by
IEC60958-3 for sampling frequencies between 28 kHz and 216 kHz.
Digital Audio Interface Transmitter (DIT)
The DIT (S/PDIF transmitter) is a relatively simple module. The DIT integrated in the DIX9211 is able to transmit
control status and user bits in the data stream, as well as standard 24-bit audio. Channel status, user data, and
Audio Valid bits in the stream are configured on incoming MPIO pins.
The DIT complies with the following audio standards:
• S/PDIF
• IEC60958 (formerly IEC958)
• JEITA CPR-1205 (formerly EIAJ CP-1201/340)
• AES3
• EBU Tech 3250 (also known as AES/EBU)
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Auxiliary PCM Audio Input and Output (I/O)
There are up to 3x digital auxiliary (AUX) inputs and one AUX output on the DIX9211. These I/Os are multiplexed
and shared with RXIN4 through RXIN7, MPIOB, and MPIOC. Each input and output supports a four-wire digital
audio interface that is similar to the I2S protocol. Each I/O can support SCK (system clock), BCK (bit clock),
LRCK (left/right clock, or word clock) and data transmissions. The audio format supported through the Aux I/O
can be configured for I2S, 24-bit left-justified (LJ), 24-bit right-justified (RJ), and 16-bit RJ output.
The AUX inputs are designed to be driven in Clock Slave mode. The Aux Output can only operate in Master
mode. The system clock can be run from 128fS, 256fS, and 512fS.
Routing
All 3x AUXIN data and clocks, in addition to data and clocks from the DIR module, are routed to three output
ports. The Main Output Port and Aux Output Port (that can be output through MPIO_B) are both PCM outputs
capable of I2S, RJ, and LJ. The DIT output is an S/PDIF signal output.
All three outputs have individual multiplexers that can select between the AUXINs or DIR.
Control Interface
The DIX9211 can be controlled by either SPI or I2C (up to a 400-kHz I2C bus). However, on startup, the device
goes into a default routing mode. Details of this mode are discussed in the Serial Control Mode section. For
certain applications, the default configuration may be suitable, and therefore does not require external
programming.
Multipurpose I/O
The DIX9211 includes 12 MPIO (Multi-Purpose Inputs/Outputs) and two MPO (Multi-Purpose Output) pins.
These MPIO/MPO pins can be easily set to different configurations through registers to allow different routing
and provide data outputs based on the specific application.
The 12 MPIO pins are divided into three groups (A, B, and C); each group has four pins (MPIO_Ax, MPIO_Bx,
and MPIO_Cx).
For example, to access all 12 S/PDIF inputs, the MPIO_Ax pins can be configured to support S/PDIF RXIN8 and
RXIN11. However, if the application requires an additional I2S input, then the MPIO_Ax pins can be configured
for an Aux In instead of RXIN8 and RXIN11.
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DIX9211 MODULE DESCRIPTIONS
Power Supply
The DIX9211 has three power-supply pins and three ground pins. All ground pins (AGND, DGND, and GNDRX)
must be connected as closely as possible to the DIX9211. The DIX9211 DVDD and DGND pins are
power-supply pins that support all the onboard digital circuitry for the DIX9211. DVDD should be connected to a
3.3-V supply. DVDD drives the internal power-on reset circuit, making it a startup requirement.
VCC and AGND are analog power-supply power pins that support the DIR analog supply rails.
VDDRX is a dedicated power supply for the coaxial input amplifiers on pins RXIN0 and RXIN1. It should be
connected to a 3.3-V pin. The relative GND pin for this supply is GNDRX. If the coaxial amplifiers are not used
(for example, the application only uses optical inputs), then no power supply is required for the VDDRX.
Because VCC (3.3 V) is an analog supply (used as part of the power supply for the DIR PLL), care should be
taken to ensure minimum noise and ripple are present. 0.1-mF ceramic capacitors and 10-mF electrolytic
capacitors should be used to decouple each supply pin to the respective relative GND.
Power-Down Function
The DIX9211 has a power-down function that is controlled by the external RST pin or a power control register.
When the RST pin is held at GND, the DIX9211 powers down.
When the device is powered down (that is, RST = GND), all register values are cleared and reset to the
respective default values. By default, all modules are powered on except for the coaxial amplifier.
The other option for powering down the device is to use the Power Control Register (Register 40h). The Power
Control Register allows selective power down of the DIR, DIT, Coax Amp, and Oscillator circuit without resetting
other registers to the respective default modes.
The advantage of using the registers to power down individual modules of the DIX9211 is that the registers retain
the respective settings rather than resetting to default.
System Reset
The DIX9211 has two sources for reset: the internal power-on reset circuit (hereafter called POR) and the
external reset circuit. Initialization (reset) is done automatically when VDD exceeds 2.2 V (typ).
When only the onboard POR is to be used, the RST pin should be connected to VDD directly. An external pull-up
resistor should not be used, because the RST pin has an internal pull-down resistor (typ 50 kΩ). If an external
resistor is used, then the reset is not released. The reset sequence is shown in Figure 1.
VDD
0V
VDD = 3.3 V typ
VDD = 2.2 V typ
Tied to VDD or DGND
MODE
RST
tRSTL
Figure 1. Required System Reset Timing
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Table 1 shows the timing requirements to reset the device using the RST pin.
Table 1. Timing Requirements for RST Pin Device Reset
SYMBOL
tRSTL
DESCRIPTION
MIN
RST pulse width (RST pin = low)
TYP
MAX
1
UNITS
µs
The condition of each output pins during the device reset is shown in Table 2.
Table 2. Output Pin Condition During Reset
CLASSIFICATION
Main Output Port
SCKO
L
BCK
L
LRCK
L
DOUT
L
H
NPCM/INT1
L
MPIO_A0 through MPIO_A3
Hi-Z
MPIO_B0 through MPIO_B3
Hi-Z
MPIO_C0 through MPIO_C3
Hi-Z
Serial I/F
(1)
AT RST = L (1)
ERROR/INT0
Flag and Status
MPIOs and MPOs
PIN NAME
MPO0, MPO1
L
MDI/SDA
Hi-Z
MDO/ADR0
Hi-Z
Oscillation Circuit
XTO
Output
Coax Input
RXIN0, RXIN1
H
L = low, H = high, Hi-Z = high impedance.
PCM Audio Interface Format
Each of the modules in the DIX9211 (DIR, DIT, and Aux I/Os) supports these four interface formats:
• 24-bit I2S format
• 24-bits Left-Justified format
• 24-bit Right-Justified format
• 16-bit Right-Justified format
32-bit interfaces are supported for the paths from AUXIN0/1/2 to MainPort/AUXOUT.
All formats are provided twos complement, MSB first. They are selectable through SPI-/I2C-accessible registers.
The specific control registers are:
• DIR: RXFMT[2:0]
• DIT: TXFMT[1:0]
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Figure 2 illustrates these formats.
2
MSB First, 24-bit I S
Left channel
LRCK
Right channel
BCK
1
DATA IN
2
3
1
DATA OUT
1
22 23 24
MSB
LSB
2
3
22 23 24
MSB
2
3
22 23 24
2
3
22 23 24
MSB
1
LSB
LSB
MSB
LSB
MSB First, 24-bit Left-Justified
Right channel
LRCK
Left channel
BCK
1
DATA IN
2
3
22 23 24
MSB
1
DATA OUT
1
LSB
2
3
22 23 24
MSB
2
3
22 23 24
2
3
22 23 24
MSB
1
LSB
LSB
MSB
LSB
MSB First, 24-bit Right-Justified
Right channel
LRCK
Left channel
BCK
DATA IN
24
1
3
2
22 23 24
MSB
DATA OUT
24
1
LSB
3
2
22 23 24
MSB
LSB
1
2
3
22 23 24
2
3
22 23 24
MSB
1
LSB
MSB
LSB
MSB First, 16-bit Right-Justified
Right channel
LRCK
Left channel
BCK
DATA IN
16
1
3
2
MSB
DATA OUT
16
1
14 15 16
LSB
3
2
MSB
14 15 16
LSB
1
2
3
14 15 16
2
3
14 15 16
MSB
1
LSB
MSB
LSB
Figure 2. Audio Data Input/Output Format
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Digital Audio Interface Receiver (RXIN0 to RXIN11)
Input Details for Pins RXIN0 Through RXIN11
Up to 12 single-ended S/PDIF input pins are available. Two of the S/PDIF input pins integrate coaxial amplifiers.
The other 10 pins are designed to be directly connected to CMOS sources or standard S/PDIF optical modules.
Each of the inputs can tolerate 5-V inputs.
The DIR module in the DIX9211 complies with these Digital Audio I/F standards:
• S/PDIF
• IEC60958 (formerly IEC958)
• JEITA CPR-1205 (formerly EIAJ CP-1201/340)
• AES3
• EBU Tech 3250 (also known as AES/EBU)
In addition, the DIR module within the DIX9211 also meets and exceeds jitter tolerance limits as specified by
IEC60958-3 for sampling frequencies between 28 kHz and 216 kHz.
Each of the physical connections used for these standards (optical, differential, and single-ended) have different
signal levels. Care should be taken to ensure that each of the RXIN pins is not overdriven or underdriven, such
as driving a coaxial 0.2-VPP signal into a CMOS 3.3-V input.
RXIN0 and RXIN1 integrate coaxial input amplifiers. This architecture means that they can be directly connected
to either coaxial input (or RCA/Phono) S/PDIF sources. They can accept a minimum of 0.2VPP. They can also be
connected to maximum 5-V TTL sources, such as optical receivers. (NOTE: Consideration should be made for
electrostatic discharge, or ESD, on the input connectors.)
RXIN2 to RXIN11 are 5-V tolerant TTL level inputs. These inputs are typically used as connections to optical
receiver modules (known as TOSLINK™ connectors).
RXIN8 through RXIN11 are also part of the MPIO_A (Multipurpose Input/Output A) group. These I/O pins can
either be set as S/PDIF inputs, or reassigned to other functions (see the MPIO section). To configure MPIO_A as
S/PDIF inputs, set Register MPASEL[1:0] to '00'.
Typically, no additional components are required to connect an optical receiver to any RXIN pin. However,
consideration should be given to the output characteristics of the specific receiver modules used, especially if
there is a long printed circuit board (PCB) trace between the receiver and the DIX9211 itself.
For differential inputs (such as the AES/EBU standard), differential to single-ended circuitry is required.
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PLL Clock Source (Built-in PLL and VCO) Details
The DIX9211 an has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock from
the S/PDIF input signal.
The VCO-derived clock is identified as the PLL clock source.
When locked, the onboard PLL generates a system clock that synchronizes with the input biphase signal. When
unlocked, the PLL generates its own free-run clock (from the VCO).
The generated system clocks from the PLL can be set to fixed multiples of the input S/PDIF frequency. Register
30h/PSCK[2:0] can configure the output clock to 128fS, 256fS or 512fS.
The DIX9211 also has an automatic default output rate that is calculated based on the incoming S/PDIF
frequency. This calculation and rate are controlled by Register 30h/PSCKAUTO. In its default mode, the SCK
dividing ratio is configured according to these parameters:
• 512fS: 54 kHz and below.
• 256fS: 54 kHz to 108 kHz
• 128fS: 108 kHz and above (or unlocked)
PSCKAUTO takes priority over any settings in PSCK[2:0]. PSCK[2:0] only becomes relevant in the system when
the PSCKAUTO Register is set to '0'.
The DIX9211 can decode S/PDIF input signals between sampling frequencies of 7 kHz and 216 kHz for all
PSCK[2:0] settings. The relationship between the output clock (SCKO, BCKO, LRCKO) at the PLL source and
PSCK[2:0] selection is shown in Table 3.
Table 3. SCKO, BCKO and LRCKO Frequency Set by PSCK[2:0]
OUTPUT CLOCK AT PLL SOURCE
SCKO
BCKO
LRCKO
PSCK2
PSCK1
PSCK0
128fS
64fS
fS
0
0
0
256fS
64fS
fS
0
1
0
64fS
fS
1
0
0
512fS
(1)
PSCK[2:0] SETTING
(1)
512fS SCK is only supported at 108 kHz or lower sampling frequency of incoming biphase signal.
In PLL mode, the output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock.
The relationship between the sampling frequencies (fS) of the input S/PDIF signal and the frequency of LRCKO,
BCKO, and SCKO are shown in Table 4.
Table 4. Output Clock Frequency at PLL Lock State
LRCK
BCK
fS
64fS
128fS
SCK (Depends on PSCK[2:0] Setting)
256fS
512fS
8 kHz
0.512 MHz
1.024MHz
2.048 MHz
4.096 MHz
11.025 kHz
0.7056 MHz
1.4112 MHz
2.8224 MHz
5.6448 MHz
12 kHz
0.768 MHz
1.536 MHz
3.072 MHz
6.144 MHz
16 kHz
1.024 MHz
2.048 MHz
4.096 MHz
8.192 MHz
22.05 kHz
1.4112 MHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
24 kHz
1.536 MHz
3.072 MHz
6.144 MHz
12.288 MHz
32 kHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
44.1 kHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
22.5792 MHz
48 kHz
3.072 MHz
6.144 MHz
12.288 MHz
24.576 MHz
64 kHz
4.096 MHz
8.192 MHz
16.384 MHz
32.768 MHz
88.2 kHz
5.6448 MHz
11.2896 MHz
22.5792 MHz
45.1584 MHz
96 kHz
6.144 MHz
12.288 MHz
24.576 MHz
49.152 MHz
128 kHz
8.192 MHz
16.384 MHz
32.768 MHz
N/A
176.4 kHz
11.2896 MHz
22.5792 MHz
45.1584 MHz
N/A
192 kHz
12.288 MHz
24.576 MHz
49.152 MHz
N/A
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DIR and PLL Loop Filter Details
The DIX9211 incorporates a PLL for generating clocks synchronized with the input biphase signal (S/PDIF). The
onboard PLL requires an external loop filter. The components and configuration shown in Figure 3 and Table 5
are recommended for optimal performance, with these considerations:
• The resistor and capacitors that configure the filter should be located and routed as close as possible to the
DIX9211. The external loop filter must be placed on the FILT pins.
• The GND node of the external loop filter must be directly connected with AGND pin of the DIX9211; it must
be not combined with other signals.
Figure 3 shows the configuration of the external loop filter and the connection with the DIX9211.
DIX9211
PLL Section
Charge
Pump
VCO
FILT
AGND
DGND
C2
R1
C1
Figure 3. Loop Filter Connection
The recommended value of loop filter components is shown in Table 5.
Table 5. Recommended Value of Loop Filter Components
REF. NO.
RECOMMENDED VALUE
TYPE
TOLERANCE
R1
680 Ω
Metal film or carbon
≤ 5%
C1
0.068 µF
Film or ceramic (CH or C0G)
≤ 5%
C2
0.0047 µF
Film or ceramic (CH or C0G)
≤ 5%
External (XTI) Clocks, Oscillators, and Supporting Circuitry
An external clock source (CMOS or crystal/resonator) is known as the XTI source. The XTI source can be either
a CMOS logic source, or a crystal resonator (internal circuitry in the DIX9211 can start the crystal resonating).
Whichever clock source is used, it must be 24.576 MHz.
The DIX9211 uses the XTI source as a reference clock in order to calculate the sampling frequency of the
incoming S/PDIF stream. It is also used as the clock source in XTI clock source mode.
When using a resonator as an XTI source, the following points should be considered:
• The 24.576-MHz resonator should be connected between the XTI and XTO pins
• The resonator should be a fundamental mode type
• A crystal or ceramic resonator can be used as the XTI source
• The values of the load capacitors CL1 and CL2 and the current limiting resistor Rd all depend on the
characteristics of the resonator
• No external feedback resistor between the XTI and XTO pins is required, because the resistor is integrated
into the device
• No loads other than the resonator should be used on the XTO pin
When using an external oscillation circuit with a CMOS output, the following points should be considered:
• Always supply a 24.576-MHz clock on the XTI pin
• Only 3.3 V is supported on the XTI pin; 5 V is not supported
• XTO should be left floating
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Figure 4 illustrates the connections for the XTI and XTO pins for both a resonator connection and an external
clock input connection.
CL1
CL2
Crystal
OSC
Circuit
Resonator
XTI
RD
Crystal
OSC
Circuit
24.576 MHz
Internal Clock
XTO
24.576 MHz
Internal Clock
XTI
External
Clock
XTO
Must be open
(Optional)
DIX9211
DIX9211
Resonator Connection
External Clock Input Connection
Figure 4. XTI and XTO Connection Diagram
In XTI mode, the output clocks (SCKO, BCKO, and LRCKO) are generated from the XTI source clock.
Register 24h/OSCAUTO controls whether or not the internal oscillator functions while it is not required. When
using the DIR as a clock source, the XTI source is not required; thus, the internal oscillator can be switched off.
There is a constraint, however, that when the DIR wide mode is being set (for example, in 192-kHz support), the
XTI is always used. The sampling frequency calculator also requires the XTI source.
XMCKO (the XTI clock buffered output) provides a buffered (and divided) XTI clock that can be output to
MPIO_A. Register 24h/XMCKEN controls whether the XMCKO should be muted or not, and Register
24h/XMCKDIV controls the division factor.
DIR Data Description
Decoded Serial Audio Data Output and Interface Format
The DIX9211 supports the following four data formats for the decoded data:
• 16-bit MSB First, Right-Justified
• 24-bit MSB First, Right-Justified
• 24-bit MSB First, Left-Justified
• 24-bit MSB First, I2S
Decoded data are MSB first and twos complement in all formats.
The format of the decoded data is selected by the RXFMT[2:0] register. The possible data formats are shown in
Table 6.
Table 6. DIR Serial Audio Data Output Format Set by RXFMT[2:0]
RXFMT[2:0] SETTING
DIR SERIAL AUDIO DATA OUTPUT FORMAT
RXFMT2
RXFMT1
RXFMT0
24-bit MSB First, Right-Justified
0
0
0
16-bit MSB First, Right-Justified
0
1
1
24-bit MSB First, I2S (Default)
1
0
0
24-bit MSB First, Left-Justified
1
0
1
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Figure 5 shows the latency time between the input biphase signal and LRCKO/DOUT. Figure 6 illustrates the
DIR decoded audio data output timing.
Biphase Signal (IN)
0R
W
0L
B
M
1L
W
1R
tLATE
BFRAME (OUT)
LRCK (OUT)
2
(I S)
LRCK (OUT)
2
(All except I S)
DATA (OUT)
0L
0R
1L
1R
17±1BCK
SYMBOL
tLATE
DESCRIPTION
MIN
LRCKO/DOUT latency
TYP
4/fS
MAX
UNITS
s
Figure 5. Latency Time Between Input Biphase and LRCKO/DOUT
tSCY
SCKO
(OUT)
VDD/2
LRCKO
(OUT)
VDD/2
tBCH
tBCL
tCKLR
BCKO
(OUT)
VDD/2
tBCY
tBCDO
DOUT
(OUT)
SYMBOL
tSCY
tCKLR
tBCY
tBCH
tBCL
tBCDO
tR
tF
VDD/2
DESCRIPTION
System clock pulse cycle time
Delay time of BCKO falling edge to LRCKO valid
BCKO pulse cycle time
BCKO pulse width high
BCKO pulse width low
Delay time of BCKO falling edge to DOUT valid
Rising time of all signals
Falling time of all signals
MIN
18
–10
TYP
MAX
10
1/64fS
60
60
–10
10
5
5
UNITS
ns
ns
s
ns
ns
ns
ns
ns
NOTE: Load capacitance of LRCKO, BCKO, and DOUT pin is 20 pF. DOUT, LRCKO, and BCKO are synchronized with
SCKO.
Figure 6. DIR Decoded Audio Data Output Timing
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Channel Status Data, User Data, and Validity Flag
The DIX9211 can output decoded channel status data, user data, and a validity flag synchronized with audio
data from the input S/PDIF signal. These signals can be transmitted from any of the three MPIOs (MPIO_A,
MPIO_B, or MPIO_C). To assign this function to the MPIOs, see the MPIO section.
Each type of output data has own dedicated output pin:
• Channel status data (C) are output through MPIOs assigned as COUT.
• User data (U) are output through MPIOs assigned as UOUT.
• Validity flag (V) is output through MPIOs assigned as VOUT
• Data (left and right) are identified as DOUT.
C, U, and V output data are synchronized with the recovered LRCKO (left-right clock output) from the S/PDIF
input signal.
The polarity of the recovered LRCKO from the S/PDIF input depends on the Register 2Fh/RXFMT[2:0] setting.
The beginning of each S/PDIF frame (BFRAME) is provided as one of the outputs on the MPIO. It can be used to
indicate the start of the frame to the decoding DSP. If the DIR decodes a start-of-frame preamble on the decoded
data, then it sets BFRAME high for 8xLRCK periods to signify the start of the frame.
LRCKO can be used as a reference clock for each of the data outputs, BFRAME, DOUT, COUT, UOUT, and
VOUT. The relationship between each output is shown in Figure 7.
Numbers 0 to 191 of DOUT, COUT, UOUT, and VOUT in Figure 7 indicate the frame number of the input
biphase signal.
RECOVERED
2
LRCKO (I S)
RECOVERED
2
LRCKO (All except I S)
17±1BCK
BFRAME
DOUT
191R
0L
0R
1L
1R
2L
3L
2R
COUT
C191R
C0L
C0R
C1L
C1R
C2L
C2R
VOUT
U191R
U0L
U0R
U1L
U1R
U2L
U2R
Figure 7. LRCKO, DOUT, BFRAME, COUT, UOUT, and VOUT Output Timing
The RXVDLY Register in Register 22h controls when the VOUT pin goes high (either immediately, or at the start
of the sample/frame). Figure 8 shows these timing sequences.
DOUT
L(n)
R(n)
L(n+1)
R(n+1)
L(n+2)
R(n+2)
V-bit = 1
VOUT
(RXVDLY = 1)
17 BCLK
VOUT
(RXVDLY = 0)
Figure 8. RXVDLY and VOUT Timing
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DIR: Parity Error Processing
Error detection and processing for parity errors behave in the following manner:
• For PCM data, when an error is detected (for example, a parity error), then the data from the previous sample
are repeated. This sequence is shown in Figure 9, where sample Ln+1 is repeated because the incoming data
(Ln+2) had an error.
• For non-PCM data, the data are output as is with no changes. (Non-PCM data implies data which has
Channel Status bit 1 = '1'.)
Figure 9 shows the processing for parity error occurrence.
[FOR PCM SIGNAL]
Internal LOCK
LRCKO (I 2S)
ERROR
DOUT
MUTE (Low)
Ln
Rn
L n+1
Rn+1
Ln+1
Rn+2
L n+3
Rn+3
Interpolation processing by previous data
Parity error
[FOR NON -PCM SIGNAL ]
Internal LOCK
LRCKO (I 2S)
ERROR
DOUT
MUTE (Low)
Ln
Rn
L n+1
Rn+1
Ln+2
Rn+2
L n+3
Rn+3
Parity error
Figure 9. Processing for Parity Error Occurrence
The DIX9211 handles parity errors as directed by the 23h/PRTPRO[1:0] registers.
When set to '01', if the error is received eight times sequentially, the DIR output is muted on the next error. Until
the mute is enabled, the previously accurate sample is repeated. This function is only valid for PCM data.
When set to '10', the device behaves in exactly the same way as it does when set to '01'. However, this function
is enabled for both PCM and non-PCM data.
When set to '00', the device ignores parity errors and continues to output whatever data comes into the device.
The setting on '11' is reserved.
DIR: Errors and Interrupts
The DIX9211 has two pins that are used to inform the system DSP or controller that there is an error, or an
interrupt that it should be aware of.
The ERR/INT0 and NPCM/INT1 pins can be configured in these ways:
HARDWARE PIN
OPTIONS
ERR/INTO0
DIR Error (default), INT0 or Hi-Z
NPCM/INT1
DIR NPCM (default), INT1 or Hi-Z
When configured as direct DIR error connections (ERR, NPCM), the system audio processor typically treats
them as dedicated interrupt pins to change or control audio processing software. An example would be that the
system may mute if an ERR signal is detected. Another example is that if the DSP receives an NPCM interrupt, it
begins looking for AC-3 or DTS preambles in the incoming encoded S/PDIF stream.
For more advanced users, the two pins can be set up as interrupt sources. The seven interrupt sources
(ERROR, NPCM, DTS-CD/LD, Emphasis, Channel Status Start, Burst Preamble Start, fS Calculator Complete)
can be masked into Registers INT0 and INT1.
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Upon receipt of an interrupt source (such as fS Calculator Complete), INT0 or INT1 performs a bitwise evaluation
of AND (&) with an inverted mask [Register 2Ah (INT0) and Register 2Bh (INT1)], then perform an eight-way OR
of the data. If the output is '1', then INTx is set to '1', which can be used to trigger an interrupt in the host DSP.
The host can then poll the INTx register to determine the interrupt source. Figure 10 shows the logic that the
device uses to mask the DIR interrupts from the INTx register.
Interrupt Source
To INTx
Mask Bit
Figure 10. DIR Interrupt Mask Logic
Once the register is read, each of the bits in the register (INT0 and INT1) are cleared. If the signal is routed to
ERR/INT0 or NPCM/INT1, the output pin is also cleared.
By default, the mask registers are set to mask all inputs; that is, all inputs are rejected, in which case no interrupt
can be seen on the output until the mask is changed.
Register 20h
ERRHZ
ERR/INT0
External Pin
Register 20h
Hi-Z
NPCMHZ
ERRSEL
Register 28h
Register 20h
INT1P
Hi-Z
NPCM/INT1
External Pin
Register 2Eh
NPCMP
Register 2Eh
ERRCON
Register 6Bh
‘1’
NPCMSEL
DIR
INT0P
Register 20h
fS Calculator
Complete
Register 2Ch/2Dh
INT0/1
Register
MOPSRC
Channel Status
Burst Preamble
Emphasis
DTS-CD/LD
INT0/1
Mask
Register 20h
Register 2Ah/2Bh
A block diagram for the error output and interrupt output is shown in Figure 11.
Figure 11. Error Output and Interrupt Output Block Diagram
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There are several allowable error sources from the DIR:
• Change of incoming S/PDIF sample frequency (Register 25h / EFSCHG)
• Out-of-range incoming S/PDIF signal (Register 25h / EFSLMT)
• Non-PCM data (Register 25h / ENPCM)
• Data invalid flag is the stream (Validity bit = '1') (Register 25h / EVALID)
• Parity error (Register 25h / EPARITY)
• PLL unlock (default) (Register 25h / EUNLOCK)
The error sources can be selected using Register 25h.
There are also several interrupts within the device that can be masked:
• Error in DIR (this error is selectable from the list above in Register 25h)
• When the device detects non-PCM data
• When the Emphasis flag in the channel status of the incoming data has been set
• When DTS-CD data have been detected by the device
• When the Channel Status (CS) is updated
• When Burst Preamble (PC) is updated
• When the sampling frequency is changed.
• When the analog input crosses the Analog Input Detect level (available only on INT1).
Each interrupt source can be masked by Register 2Ah (INT0) and Register 2Bh (INT1).
DIR: Sampling Frequency Calculator for Incoming S/PDIF Inputs
The DIX9211 has two integrated sampling frequency calculators. The first calculator is always connected to the
output of the DIR. It calculates the actual sampling frequency of the incoming S/PDIF signal. The result can be
read from a register, or output through the MPIO pins. Note that this process is not the same as reading the
Channel Status value for the sample rate that the transmitting equipment may be sending.
To use this function, a 24.576-MHz clock source must be supplied to the XTI pin. The 24.576-MHz clock is used
as a reference clock to calculate the incoming S/PDIF sampling frequency. If the XTI pin is connected to DGND,
the function is disabled and the calculation is not performed. If there is an error in the XTI clock frequency, the
calculation result and range will be incorrect.
The result is decoded into 4-bit data and stored in Register 39h/SFSOUT[3:0]; the MPIO pins are then assigned
to the SFSOUT[3:0] function.
The data in the SFSOUT[3:0] register (and available as a signal for the MPIO section) are the calculated
sampling frequency based on the incoming S/PDIF stream, and not what is reported in Channel Status bits 24 to
27. If the PLL becomes unlocked, or attempts to run out of range, SFSOUT[3:0] = '0000' is output, and indicates
abnormal operation.
If the XTI source clock is not supplied before the DIX9211 powers up, SFSOUT [3:0] outputs '0000'. If the XTI
source clock is stopped, the fS calculator holds its most recent calculated result. Once the XTI source clock is
restored, the fS calculator resumes operation.
Register 39h/SFSST indicates the calculator status. Before reading SFSOUT[3:0], it is recommended that the
user verify that the SFSST status is '0'.
24
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The relationship between SFSOUT[3:0] outputs and the range of sampling frequency fS is shown in Table 7.
Table 7. Calculated Biphase Sampling Frequency Output
CALCULATED SAMPLING FREQUENCY OUTPUT (1)
NOMINAL fS
ACTUAL SAMPLING
FREQUENCY RANGE
SFSOUT3
SFSOUT2
SFSOUT1
SFSOUT0
Out of range
Out of range
0
0
0
0
(1)
8 kHz
7.84 kHz to 8.16 kHz
0
0
0
1
11.025 kHz
10.8045 kHz to 11.2455 kHz
0
0
1
0
12 kHz
11.76 kHz to 12.24 kHz
0
0
1
1
16 kHz
15.68 kHz to 16.32 kHz
0
1
0
0
22.05 kHz
21.609 kHz to 22.491 kHz
0
1
0
1
24 kHz
23.52 kHz to 24.48 kHz
0
1
1
0
32 kHz
31.36 kHz to 32.64 kHz
0
1
1
1
44.1 kHz
43.218 kHz to 44.982 kHz
1
0
0
0
48 kHz
47.04 kHz to 48.96 kHz
1
0
0
1
64 kHz
62.72 kHz to 65.28 kHz
1
0
1
0
88.2 kHz
86.436 kHz to 89.964 kHz
1
0
1
1
96 kHz
94.08 kHz to 97.92 kHz
1
1
0
0
128 kHz
125.44 kHz to 130.56 kHz
1
1
0
1
176.4 kHz
172.872 kHz to 179.928 kHz
1
1
1
0
192 kHz
188.16 kHz to 195.84 kHz
1
1
1
1
The flag SFSOUT[3:0] is output from the register and MPIOs are assigned as SFSOUT[3:0].
'0' or '1' indicates the register output data. The symbol 'H' or 'L' refers to the MPIO output electrical signal.
The Biphase Sampling Frequency Calculator is also used for restricting the type of data that can be received.
1. If Register 27h/MSK128 is set to '1', the DIX9211 does not accept 128-kHz sampling frequency data
2. If Register 27h/MSK64 is set to '1', the DIX9211 does not accept 64-kHz sampling frequency data.
3. If Register 27h/NOMLMT is set to '1', the DIX9211 only accepts the nominal audio sampling frequency within
±2%.The nominal audio sampling frequencies are 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz,32
kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz, and 192 kHz.
4. For Register 27h/HILMT[1:0] and Register 27h/LOLMT[1:0]: These registers are used for setting a higher or
lower limit to the acceptable sampling frequency.
Register 21h/RXFSRNG is used for global control of the acceptable sampling frequencies. If normal mode is
selected, the range of acceptable sampling frequency is restricted from 28 kHz to 108 kHz. If wide mode is
selected, the range is from 7 kHz to 216 kHz.
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DIR: Audio Port Sampling Frequency Calculator
The second sampling frequency calculator can be used to calculate the sampling frequency of DIR, XTI,
AUXIN0, AUXIN1, AUXIN2, Main Output Port, AUX Output Port, and DIT Input. Figure 12 illustrates the sampling
frequency calculator sources.
PFSTGT[2:0]
DIR (default)
000
XTI
001
AUXIN0
010
AUXIN1
011
AUXIN2
100
Main Output Port
101
AUX Output Port
110
DIT
111
Audio Port
Sampling Frequency
Calculator
Figure 12. Sampling Frequency Calculator Sources
The calculated sampling frequency fS is decoded to 4-bit data and stored in the PFSOUT[3:0] register. The input
source of this counter is selectable from AUXIN0, AUXIN1, AUXIN2, DIR, XTI, Main Output Port, AUX Output
Port, and DIT by using the Register 37h/PFSTGT[3:0].
To use this function, a 24.576-MHz clock source must be supplied to the XTI pin. The 24.576-MHz clock is used
as a reference clock. If the XTI pin is connected to DGND, the calculation is not performed. If there is an error in
the XTI clock frequency, the calculation result and range will be incorrect.
Register 38h/PFSST indicates the calculator status. It is recommended that PFSST is checked (for complete
status) before reading PFSOUT[3:0].
26
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OUTPUT REGISTER CONSTRUCTION
The output 8-bit register is subdivided into three sections. The first four bits show the decoded result. The next
three bits signify the source; the final bit signifies the calculator status (finished or not).
The lock range of the counter (to the specified fS given in Table 8) are any clock rate within ±2%. The relation
between the nominal fS and actual measured fS range is shown in Table 8.
Table 8. Calculated Port Sampling Frequency Output
CALCULATED SAMPLING FREQUENCY OUTPUT
NOMINAL fS
ACTUAL SAMPLING
FREQUENCY RANGE (MIN)
PFSOUT3
PFSOUT2
PFSOUT1
PFSOUT0
Out of range
Out of range
0
0
0
0
8 kHz
7.84 kHz to 8.16 kHz
0
0
0
1
11.025 kHz
10.8045 kHz to 11.2455 kHz
0
0
1
0
12 kHz
11.76 kHz to 12.24 kHz
0
0
1
1
16 kHz
15.68 kHz to 16.32 kHz
0
1
0
0
22.05 kHz
21.609 kHz to 22.491 kHz
0
1
0
1
24 kHz
23.52 kHz to 24.48 kHz
0
1
1
0
32 kHz
31.36 kHz to 32.64 kHz
0
1
1
1
44.1 kHz
43.218 kHz to 44.982 kHz
1
0
0
0
48 kHz
47.04 kHz to 48.96 kHz
1
0
0
1
64 kHz
62.72 kHz to 65.28 kHz
1
0
1
0
88.2 kHz
86.436 kHz to 89.964 kHz
1
0
1
1
96 kHz
94.08 kHz to 97.92 kHz
1
1
0
0
128 kHz
125.44 kHz to 130.56 kHz
1
1
0
1
176.4 kHz
172.872 kHz to 179.928 kHz
1
1
1
0
192 kHz
188.16 kHz to 195.84 kHz
1
1
1
1
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DIR: Auto Source Selector for Main Output and AUX Output
The AUTO source selector is an automatic system that selects the DIR or XTI output based on specific DIR
conditions set by Register 26h. The AUTO source selector is integrated in both the Main Port and the AUX
output separately.
The typical behavior for the AUTO source selector is shown in Figure 13. This example is the default register
setting for Register 26h. In this case, only Register 26h/AUNLOCK is selected.
RXINx
Built-In PLL Status
Non-Biphase
Biphase
Non-Biphase
Unlock
Lock
Unlock
Normal Operation
XTI Status
CLKST
tCLKST2
tCLKST1
ERROR
tXTIWT
SCKO, BCK, LRCK
XTI Source
DOUT
DIR Source
XTI Source
DIR Source
Figure 13. Typical Behavior for AUTO Source Selector
When the DIR is unlocked, the XTI output is automatically routed to the Main Output Port.
Polarity of the CLKST signal is configured by Register 22h/CLKSTP. The default is active low, which means that
clock source either changes from DIR to XTI, or from XTI to DIR.
If the DIR is locked, then the DIR output is routed to the Main Output Port automatically after tCLKST1. During that
period, the output port is muted. tCLKST1 can be configured using Register 23h/ERRWT[1:0]. tCLKST2 is 50 ms,
providing that an XTI clock of 24.576 MHz is applied.
If the DIR loses its lock a subsequent time, the XTI output is routed to the Main Output Port automatically after
tXTIWT. Once again, the output port is muted during this time. tXTIWT can be configured using Register
23h/XTIWT[1:0].
The auto source selector can be triggered by the following changes in the DIR (Register 26h is used to select
which variable to use as the trigger):
• DIR error (discussed earlier in DIR: Errors and Interrupts; configured by Register 25h)
• Out-of-range sampling frequency
• Non-PCM data
• When the Validity flag in the S/PDIF stream is '1'
• When the PLL is unlocked (default)
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Figure 14 shows the Clock Tree Diagram for the AUTO source selector.
AUTO select signal defined
by REG.25h excluding AERROR
ERROR defined by REG.25h
DIR
SCK/BCK/LRCK/DOUT
REG.25h/AERROR
SCK/BCK/LRCK
AUTO
Selector
AUTO
DIR
Main Port
XTI
AUXINx
Divider
OSC
SCK/BCK/LRCK
AUXINx
REG.6Bn/
MOSSRC and MOPSRC
Figure 14. Clock Tree Diagram for AUTO Source Selector
Non-PCM Data Detection
The DIX9211 can also detect Non-PCM data (AC-3, DTS-CD, etc.) using one of these two methods:
1. Channel Status Bit 1 is '1'.
If Register 28h/CSBIT is set to '1', this function is enabled. Register 39h/SCSBIT1 always indicates Channel
Status Bit 1 status even if CSBIT1 is disabled.
2. A Burst Preamble (PA/PB) is found in the S/PDIF stream.
If Register 28h/PAPB or Register 28h/DTSCD is set to '1', this function is enabled. If DTS-CD detection is
active, it uses DTSCD, and can also be set in Register 29h/DTS16, 29h/DTS14, and Register
29h/DTSPRD[1:0].
If the DIX9211 detects a Burst Preamble when Non-PCM detection is enabled, an error signal and BPSYNC
signal are generated. The BPSYNC signal can be monitored through MPIO_A/MPIO_B/MPIO_C. For more
details, see the MPIO section of this document. The error signal can be monitored from either the ERR_INT0 pin
or the NPCM_INT1 pin.
PC/PD Monitor
The DIX9211 has a PC and PD buffer for monitoring the latest PC or PD. Registers 3Ah and 3Bh are assigned for
the PC buffer; Registers 3Ch and 3Dh are assigned for the PDbuffer.
The following sequence is an example of reading PC/PD buffers. This example is based on using the INT0
function.
1. Set Register 2Ah/MPCRNW0 to '0'.
2. Check that Register 2Ch/OPCRNW0 is '1'.
3. Read the PC and PD buffers.
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Digital Audio Interface Transmitter
Overview
The DIX9211 has an onboard Digital Audio Interface Transmitter (DIT) that transmits S/PDIF data from 7 kHz to
216 kHz, up to 24-bit audio data. The first 48 bits of the channel status buffer are programmable. The source for
the DIT is selectable from the built-in routing function of the DIX9211 as well as the dedicated inputs assigned to
the MPIOs.
Selection OF DIT Input Source
Selection of the DIT audio and clock sources is done using the Registers 60h/TXSSRC[2:0] and
60h/TXPSRC[2:0]. The system clock source for the DIT is selected using the Register 60h/TXSSRC[2:0]. The
PCM audio data source for the DIT (BCK. LRCK, and Data) is selected using the Register 60h/TXPSRC[2:0].
The DIT can also be operated in a standalone mode. In standalone mode, the data source is provided through
MPIO_C. See the DIT Stand-Alone section for more details.
DIT Output Biphase
The S/PDIF-encoded signal generated by the DIT module is available through the MPO0 and MPO1 pins. The
MPO selection registers (Register 78h/MPOxSEL[3:0]) can be set to '1101' to determine the DIT output through
one of these two pins.
In addition to the standard MPOx pins, the DIT output can also be multiplexed to the RECOUT pin, or back into
the DIR. An example of where this multiplexing might occur is in a jitter cleaner application. The DIR in the
DIX9211 has excellent jitter reduction. Data can be brought in from an auxiliary source, transmitted through the
DIT internally, then routed to the DIR. This process, in turn, cleans the clocks and provides a stable, well-clocked
PCM source. This feature is especially useful for jittery sources, such as HDMI.
Audio Data and Clock
The DIT can accept a 128fS, 256fS, or 512fS system clock. The clock ratio selection is set by using the Register
TXSCK[2:0]. A 216-kHz sampling frequency is supported by using the 128fS or 256fS system clock ratio. A
108-kHz sampling frequency can be supported up to a 512fS clock ratio.
I2S, 24-bit left-justified, 24-bit right-justified, and 16-bit right-justified serial audio interface formats can be used.
Only slave mode is supported. Table 9 shows the relationship between typical audio sampling frequencies and
the respective BCK and SCK frequencies
Table 9. Typical Audio Sampling, BCK, and SCK Frequencies
LRCK
30
BCK
SCK
fS
64fS
128fS
256fS
512fS
8 kHz
0.512 MHz
1.024MHz
2.048 MHz
4.096 MHz
11.025 kHz
0.7056 MHz
1.4112 MHz
2.8224 MHz
5.6448 MHz
12 kHz
0.768 MHz
1.536 MHz
3.072 MHz
6.144 MHz
16 kHz
1.024 MHz
2.048 MHz
4.096 MHz
8.192 MHz
22.05 kHz
1.4112 MHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
24 kHz
1.536 MHz
3.072 MHz
6.144 MHz
12.288 MHz
32 kHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
44.1 kHz
2.8224 MHz
5.6448 MHz
11.2896 MHz
22.5792 MHz
48 kHz
3.072 MHz
6.144 MHz
12.288 MHz
24.576 MHz
64 kHz
4.096 MHz
8.192 MHz
16.384 MHz
32.768 MHz
88.2 kHz
5.6448 MHz
11.2896 MHz
22.5792 MHz
45.1584 MHz
96 kHz
6.144 MHz
12.288 MHz
24.576 MHz
49.152 MHz
128 kHz
8.192 MHz
16.384 MHz
32.768 MHz
N/A
176.4 kHz
11.2896 MHz
22.5792 MHz
45.1584 MHz
N/A
192 kHz
12.288 MHz
24.576 MHz
49.152 MHz
N/A
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Data Mute Function
The DIX9211 has the ability to mute the audio data on its DIT output. This option is set using Register
62h/TXDMUT. During a mute state (TXDMUT = '1'), the biphase stream continues to flow, but all audio data are
zeroed.
The channel status data and validity flag are not zeroed. Mute is done at the LRCK edge for both L-ch and R-ch
data at the same time.
Channel Status Data
The DIT has the ability to transmit channel status (CS) data for the first 48 bits of the 128-bit stream. These 48
bits cover the standards for both S/PDIF and AES/EBU. These bits are set in Registers TXCS0 through TXCS47.
These values are used on both the Left and Right channels of the output stream.
Upon reset, these registers are all '0' by default.
User Data
This DIT does not have the ability to transmit custom user data (known as U Bits in the stream).
Validity Flag
Setting the valid flag is possible in the DIT by using Register 62h/TXVFLG. The same value is used for both left
and right channels.
Standalone Operation
Standalone operation for the DIT module is provided by supplying external clocks and data (SCK, BCK, LRCK,
and Data). In standalone mode, the audio and clock data must be brought into the device through MPIO_C. To
enable standalone mode, set Register 6Fh/MPCSEL[2:0] to '101'. This configuration then bypasses the standard
DIT connections through the device and connects them directly to MPIO_C.
Channel Status and Validity flags continue to be sourced from the same registers as they would during normal
DIT operation.
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MPIO Description
Overview
The DIX9211 offers significant flexibility through its MPIO pins. Depending on the system partitioning of the
specific end product, the pins can be reconfigured to offer various I/Os that complement the design.
There are 14 flexible pins: 12 are Input/Output pins, and two pins that are output only.
The 12 multi-purpose I/O (MPIO) pins are grouped into three banks, each with four pins: MPIO_A, MPIO_B, and
MPIO_C.
The two multi-purpose outputs (MPO) pins are assigned as MPO0 and MPO1.
Assignable Signals for MPIO Pins
The DIX9211 has the following signals that can be brought out to MPIOs. Not all MPIOs are equal; be sure to
review subsequent sections in this document to see which signals can be brought out to which MPIO. The
possible signals are summarized in Table 10.
Table 10. Allowable MPIO Signals
MODULE
ALLOWABLE SIGNALS
Extended biphase input pins for DIR: RXIN8/RXIN9/RXIN10/RXIN11
DIR Flags Output: The details of each signal are described in the Flag
section.
DIR
DIR Interrupt Output: INT0 and INT1
DIR, B frame, serial output of channel status, user data, validity flag
DIR, decoded result of sampling frequency calculated by built-in fS
counter
AUXIN0, external serial audio data input (SCK/BCK/LRCK/Data)
Auxiliary I/O
AUXIN1, external serial audio data input (SCK/BCK/LRCK/Data)
AUXIN2, external serial audio data input (SCK/BCK/LRCK/Data)
AUXOUT, external serial audio data output (SCK/BCK/LRCK/Data)
DIT
Application-Specific
Digital Logic Specific
Serial audio data input for DIT Standalone Operation
AVR Application1: Clock Transition Output, Validity Output, XTI
buffered Output, Interrupt Output
AVR Application2: Secondary BCK/LRCK Output, XTI buffered
Output, Interrupt Output
GPIO (General Purpose I/O), Logical high or low I/O, selectable I/O
direction for each pin
Hi-Z status, selectable for each pin
How to Assign Functions to MPIO
Both MPO0 and MPO1 have a function assignment register. The output of MPO0 can be selected using the
MPO0SEL[3:0] register; in the same way, the output of MPO1 can be selected using the MPO1SEL[3:0] register.
Selecting the biphase source can be done using Register 35h/RO0SEL and Register 36h/RO1SEL. Muting the
MPO can be done using Registers MPO0MUT and MPO1MUT.
Selection Of Output Source
The DIX9211 also has a routing function for serial digital audio clocks and data. This function routes between all
input sources (DIR, XTI, AUXIN0, AUXIN1, AUXIN2) and Main Out, AUXOUT, and DIT. The selection for Main
Out and AUXOUT is set with these registers:
• Main Out: Registers 6Bh, MOSSRC[2:0], and MOPSRC[2:0]
• AUXOUT: Register 6Ch, AOSSRC[2:0], and AOPSC[2:0]
Muting Main Out and AUXOUT is done using Register 6Ah. Hi-Z control for Main Out is set with Register 6Dh.
32
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Assignable Signals to MPO Pins
Both MPO pins have the same function. The following signals can be routed to the MPOs:
• DIR flags output (details of signals are described in the Flag section)
• DIR Interrupt Output: INT0 and INT1
• B frame, serial output of channel status, user data and validity flag of DIR
• GPO (general-purpose output), Hi-Z / Logical high or low
• DIT biphase Output
• XTI buffered Output
• RECOUT0 or RECOUT1, two independent multiplexers, are provided
To use the limited pins of the DIX9211 economically, the DIR flag outputs and the GPIO are used at same time
within the number of MPIO pins assigned to DIR flags or to GPIO functions. DIR flags or GPIO can be selected
for each MPIO zone by using Registers MPASEL[1:0], MPBSEL[2:0], and MPCSEL[2:0]
NOTE
To identify the pins in each MPIO group, the convention * represents 0 to 3.
When DIR flags are required on hardware pins, users should select the desired signals with Registers MPA*FLG,
MPB*FLG, and MPC*FLG.
When GPIOs are required, set the I/O direction with GIOA*DIR, GIOB*DIR, and GIOC*DIR registers. When a
GPO (general-purpose output) function is required, set the output data with Registers GPOA*, GPOB*, and
GPOC*. When a GPI (general-purpose input) function is required, the status of the pins with an assigned GPI
function is stored in the GPIA*, GPIB*, and GPIC* registers (these registers are read-only).
External ADC Mode
To use an external analog-to-digital converter (ADC), the DIX9211 supports External ADC Mode. This option
enables a connection with an external, 192-kHz capable ADC via the MPIO_B ports. The external ADC must be
a clock slave to the DIX9211. The clock source for the external ADC can be selected using Register 42h/ADCLK.
To use the external ADC mode, Register 6Fh/MPBSEL must be set to '101' (External Slave ADC Input). Then,
each MPIO_B port is assigned for MPIO_B0 = EASCKO (output), MPIO_B1 = EABCKO (output), MPIO_B2 =
EALRCKO (output), and MPIO_B3 = EADIN (input). The MPIO_B pins should be connected according to this
configuration:
• MPIO_B0 to ADC system clock input
• MPIO_B1 to ADC bit clock input
• MPIO_B2 to ADC LR clock input
• MPIO_B3 to ADC data output
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MPIO and MPO Assignments
The I/O function of the MPIOs and MPOs are assigned by Registers MPASEL[1:0], MPBSEL[2:0], MPCSEL[2:0],
MPO0SEL[3:0], and MPO1SEL[3:0]. The available functions are shown in Table 11 through Table 15.
Table 11. MPIO Group A (Pins: MPIO_A0 to MPIO_A3)
MPASEL[1:0]
(1)
DIRECTION
MPIO GROUP A FUNCTION
00
IN
01
OUT
Biphase input (RXIN8/RXIN9/RXIN10/RXIN11)
AVR Application 1 (CLKST, VOUT, XMCKO, INT0) (default) (1)
10
OUT
AVR Application 2 (SBCK, SLRCK, XMCKO, INT0)
11
IN/ OUT
DIR Flags output or GPIOs
MPIO_A0 to MPIO_A3 are set to Hi-Z by the MPA0HZ to MPA3HZ registers as default.
Table 12. MPIO Group B (Pins: MPIO_B0 to MPIO_B3)
MPBSEL[2:0]
DIRECTION
000
IN
MPIO GROUP B FUNCTION
001
OUT
AUXOUT, ASCKO/ABCKO/ALRCKO/ADOUT
010
OUT
Sampling frequency calculated result output, SFSOUT[3:0]
011
IN/OUT
AUXIN2, ASCKI2/ABCKI2/ALRCKI2/ADIN2 (default)
DIR Flags Output or GPIO
100
OUT
101
IN/OUT
DIR BCUV_Output (BFRAME/COUT/UOUT/VOUT)
110
N/A
Reserved
111
N/A
Reserved
External slave ADC input (EASCKO/EABCKO/EALRCKO/EADIN)
Table 13. MPIO Group C (Pins: MPIO_C0 to MPIO_C3)
34
MPCSEL[2:0]
DIRECTION
000
IN
001
IN/OUT
010
OUT
011
IN/OUT
100
OUT
MPIO GROUP C FUNCTION
AUXIN1 (ASCKI1/ABCKI1/ALRCKI1/ADIN1) (default)
Reserved
Sampling frequency calculated result output, SFSOUT[3:0]
DIR Flags output or GPIO
DIR BCUV output (BFRAME/COUT/UOUT/VOUT)
101
IN
110
N/A
DIT Standalone, clock, and data (TXSCK/TXBCK/TXLRCK/TXDIN)
Reserved
111
N/A
Reserved
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Table 14. MPO0 Pin
MPO0SEL[3:0]
DIRECTION
0000
OUT
Hi-Z
MPO0 FUNCTION
0001
OUT
GPO0, Output data = Logic high level
0010
OUT
GPO0, Output data = Logic low level
0011
OUT
VOUT
0100
OUT
INT0
0101
OUT
INT1
0110
OUT
CLKST
0111
OUT
EMPH
1000
OUT
BPSYNC
1001
OUT
DTSCD
1010
OUT
PARITY
1011
OUT
LOCK
1100
OUT
XMCKO
1101
OUT
TXOUT (default)
1110
OUT
RECOUT0
1111
OUT
RECOUT1
Table 15. MPO1 Pin
MPO1SEL[3:0]
DIRECTION
0000
OUT
Hi-Z
MPO1 FUNCTION
0001
OUT
GPO1, Output data = Logic high level
0010
OUT
GPO1, Output data = Logic low level
0011
OUT
VOUT (default)
0100
OUT
INT0
0101
OUT
INT1
0110
OUT
CLKST
0111
OUT
EMPH
1000
OUT
BPSYNC
1001
OUT
DTSCD
1010
OUT
PARITY
1011
OUT
LOCK
1100
OUT
XMCKO
1101
OUT
TXOUT
1110
OUT
RECOUT0
1111
OUT
RECOUT1
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MPIO Description
Description for Signal Name Assigned to MPIO
Table 16 through Table 24 list the details of where each of the internal DIX9211 signals can be routed to. For
instance, DIR LOCK can be output to any of the MPIO and MPO pins, while SBCK (Secondary Clock Output)
can only be brought out through MPIO_A0.
Table 16. DIR Flags Output
SIGNAL NAME
MPIO GROUP / PIN
DESCRIPTION
CLKST
All MPIOs, MPO0/1
Clock transient status signal output
INT0
All MPIOs, MPO0/1
Interrupt system 0, Interrupt event detection output
INT1
All MPIOs, MPO0/1
Interrupt system 1, Interrupt event detection output
EMPH
All MPIOs, MPO0/1
Channel status, emphasis detection output
BPSYNC
All MPIOs, MPO0/1
Burst preamble sync signal output
DTSCD
All MPIOs, MPO0/1
DTS-CD/LD detection output
PARITY
All MPIOs, MPO0/1
Biphase parity error detection output
LOCK
All MPIOs, MPO0/1
PLL lock detection output
Table 17. DIR B Frame, Channel Status, User Data, Validity Flag Output
SIGNAL NAME
MPIO GROUP / PIN
BFRAME
All MPIOs, MPO0/1
DESCRIPTION
COUT
All MPIOs
Channel status data
UOUT
All MPIOs
User data
VOUT
All MPIOs
Validity flag
B frame output
Table 18. DIR Calculated Sampling Frequency Output
SIGNAL NAME
MPIO GROUP / PIN
SFSOUT0
All MPIOs
Calculated fS, decoded output, bit0
DESCRIPTION
SFSOUT1
All MPIOs
Calculated fS, decoded output, bit1
SFSOUT2
All MPIOs
Calculated fS, decoded output, bit2
SFSOUT3
All MPIOs
Calculated fS, decoded output, bit3
Table 19. Biphase Input
SIGNAL NAME
MPIO GROUP / PIN
RXIN8
MPIO_A0
Biphase signal input 8
DESCRIPTION
RXIN9
MPIO_A1
Biphase signal input 9
RXIN10
MPIO_A2
Biphase signal input 10
RXIN11
MPIO_A3
Biphase signal input 11
Table 20. Biphase Output
SIGNAL NAME
MPIO GROUP / PIN
RECOUT0
MPO0/1
Independent biphase selector 0, output0
DESCRIPTION
RECOUT1
MPO0/1
Independent biphase selector 1, output1
TXOUT
MPO0/1
Built-in DIT, biphase output
Table 21. AUX Clocks Output
36
SIGNAL NAME
MPIO GROUP / PIN
SBCK
MPIO_A0
Secondary bit clock output
DESCRIPTION
SLRCK
MPIO_A1
Secondary LR clock output
XMCKO
MPIO_A2, MPO0/1
XTI pin input clock buffered output
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Table 22. Audio Clock and Data I/O
SIGNAL NAME
MPIO GROUP / PIN
ASCKI1
MPIO_C0
AUXIN1, system clock input
DESCRIPTION
ABCKI1
MPIO_C1
AUXIN1, bit clock input
ALRCKI1
MPIO_C2
AUXIN1, LR clock input
ADIN1
MPIO_C3
AUXIN1, data input
ASCKI2
MPIO_B0
AUXIN2, system clock input
ABCKI2
MPIO_B1
AUXIN2, bit clock input
ALRCKI2
MPIO_B2
AUXIN2, LR clock input
ADIN2
MPIO_B3
AUXIN2, data input
ASCKO
MPIO_B0
AUXOUT, system clock output
ABCKO
MPIO_B1
AUXOUT, bit clock output
ALRCKO
MPIO_B2
AUXOUT, LR clock output
ADOUT
MPIO_B3
AUXOUT, data output
EASCKO
MPIO_B0
External Slave ADC Input, system clock output
EABCKO
MPIO_B1
External Slave ADC Input, bit clock output
EALRCKO
MPIO_B2
External Slave ADC Input, LR clock output
EADIN
MPIO_B3
External Slave ADC Input, data input
TXSCK
MPIO_C0
DIT Standalone, system clock input
TXBCK
MPIO_C1
DIT Standalone, bit clock input
TXLRCK
MPIO_C2
DIT Standalone, LR clock input
TXDIN
MPIO_C3
DIT Standalone, data input
Table 23. GPIO (General-Purpose Input/Output)
SIGNAL NAME
MPIO GROUP / PIN
DESCRIPTION
GPIA0
MPIO_A0
General-purpose input
GPIA1
MPIO_A1
General-purpose input
GPIA2
MPIO_A2
General-purpose input
GPIA3
MPIO_A3
General-purpose input
GPOA0
MPIO_A0
General-purpose output
GPOA1
MPIO_A1
General-purpose output
GPOA2
MPIO_A2
General-purpose output
GPOA3
MPIO_A3
General-purpose output
GPIB0
MPIO_B0
General-purpose input
GPIB1
MPIO_B1
General-purpose input
GPIB2
MPIO_B2
General-purpose input
GPIB3
MPIO_B3
General-purpose input
GPOB0
MPIO_B0
General-purpose output
GPOB1
MPIO_B1
General-purpose output
GPOB2
MPIO_B2
General-purpose output
GPOB3
MPIO_B3
General-purpose output
GPIC0
MPIO_C0
General-purpose input
GPIC1
MPIO_C1
General-purpose input
GPIC2
MPIO_C2
General-purpose input
GPIC3
MPIO_C3
General-purpose input
GPOC0
MPIO_C0
General-purpose output
GPOC1
MPIO_C1
General-purpose output
GPOC2
MPIO_C2
General-purpose output
GPOC3
MPIO_C3
General-purpose output
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Table 24. GPO (General-Purpose Output)
SIGNAL NAME
MPIO GROUP / PIN
GPO0
MPO0
General-purpose output
DESCRIPTION
GPO1
MPO1
General-purpose output
MPIO and MPO Assignment: Pin Assignment Details
Each MPIO group has four pins. Table 25 through Table 27 describe the signals assigned to each group.
Table 25. MPIO Group A
ASSIGNED PIN FUNCTION
(1)
MPASEL[1:0]
MPIO_A0
MPIO_A1
MPIO_A2
MPIO_A3
00
RXIN8
RXIN9
RXIN10
RXIN11
01 (Default)
CLKST
VOUT
XMCKO
INT0
10
SBCK
SLRCK
XMCKO
11
DIR Flag / GPIO (1)
DIR Flag / GPIO (1)
DIR Flag / GPIO
INT0
(1)
DIR Flag / GPIO (1)
This function, DIR Flag Output or GPIO, is set for each pin by Registers MPA0FLG, MPA1FLG, MPA2FLG, and MPA3FLG.
Table 26. MPIO Group B
ASSIGNED PIN FUNCTION
(1)
MPBSEL[1:0]
MPIO_B0
MPIO_B1
MPIO_B2
MPIO_B3
000 (Default)
ASCKI2
ABCKI2
ALRCKI2
ADIN2
001
ASCKO
ABCKO
ALRCKO
ADOUT
010
SFSOUT3
SFSOUT2
SFSOUT1
SFSOUT0
011
DIR Flag / GPIO (1)
DIR Flag / GPIO (1)
DIR Flag / GPIO (1)
100
BFRAME
COUT
UOUT
VOUT
101
EASCKO
EABCKO
EALRCKO
EADIN
110
Reserved
Reserved
Reserved
Reserved
111
Test Mode
Test Mode
Test Mode
Test Mode
DIR Flag / GPIO
(1)
This function, DIR Flag Output or GPIO, is set for each pin by Registers MPB0FLG, MPB1FLG, MPB2FLG, and MPB3FLG.
Table 27. MPIO Group C
ASSIGNED PIN FUNCTION
MPCSEL[1:0]
38
MPIO_C1
MPIO_C2
MPIO_C3
000 (Default)
ASCKI1
ABCKI1
ALRCKI1
ADIN1
001
Reserved
Reserved
Reserved
Reserved
010
SFSOUT3
011
(1)
MPIO_C0
DIR Flag / GPIO
SFSOUT2
(1)
DIR Flag / GPIO
SFSOUT1
(1)
DIR Flag / GPIO
SFSOUT0
(1)
DIR Flag / GPIO (1)
100
BFRAME
COUT
UOUT
VOUT
101
TXSCK
TXBCK
TXLRCK
TXDIN
110
Reserved
Reserved
Reserved
Reserved
111
Reserved
Reserved
Reserved
Reserved
This function, DIR Flag Output or GPIO, is set for each pin by Registers MPC0FLG, MPC1FLG, MPC2FLG, and MPC3FLG.
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Default Routing Function (After RESET)
The default routing paths are shown in Figure 15 in blue. MPIO_A0-A3 are selected by CLKST, VOUT, XMCKO,
and INT0. Note that by default, MPIO_A0-A3 pins are Hi-Z as set by Registers MPA0HZ, MPA1HZ, MPA2HZ,
and MPA3HZ.
FILT
AUXIN0
AUTO
RXIN0
RXIN0
RXIN1
RXIN1
RXIN2
RXIN2
AUXIN0
RXIN3
RXIN3
AUXIN1
RXIN4/ASCKI0
RXIN4
RXIN5/ABCKI0
RXIN5
RXIN6/ALRCKI0
RXIN6
RXIN7/ADIN0
RXIN7
DIR
RXIN7
SCKO
DIR
XTI
PLL
Main
Output
Port
DOUT
Lock: DIR
Unlock: XTI
Clock/Data
Recovery
BCK
LRCK
DOUT
SCKO/BCK/LRCK
AUXIN2
AUTO
DIR
MPIO_A0 (CLKST)
RXIN8
MPIO_A1 (VOUT)
RXIN9
MPIO_A2 (XMCKO)
MPIO_A
Selector
MPIO_A3 (INT0)
These pins are Hi-Z
at default
XTI
Lock
Detection
DIT
AUXIN0
RXIN10
AUXIN1
RXIN11
RECOUT0
DITOUT
RECOUT1
AUXIN2
RECOUT0
RECOUT1
DITOUT
MPO0
MPO0/1
Selector
MPO1
AUTO
MPIO_C0 (TXSCK)
DIR
MPIO_C1 (TXBCK)
XTI
MPIO_C2 (TXLRCK)
MPIO_C
Selector
MPIO_B0 (ASCKI2)
MPIO_B1 (ABCKI2)
AUXOUT
AUXIN0
AUXIN1
MPIO_C3 (TXDIN)
AUXIN1
MPIO_B
Selector
AUXIN2
MPIO_B2 (ALRCKI2)
MPIO_B3 (ADIN2)
XTI Clock
(SCK/BCK/
LRCK)
Divider
XTI
XTO
OSC
XMCKO
Divider
XMCKO
(To MPIO_A and MPO0/1)
Secondary BCK/LRCK
Divider
Selector
Register
Function
Control
DIR CS
(48-Bit)
DIR PC
and PD
DIR fS
Calculator
GPIO/GPO
Data
DIR CS
(48-Bit)
DIR
Interrupt
All Port fS
Calculator
SBCK/SLRCK
(to MPIO_A)
EXTRA DIR
FUNCTIONS
Error Detection
Non-PCM Detection
fS Calculator
Flags
DTS-CD/LD Detection
Validity Flag
User Data
Channel Status Data
BFRAME Detection
Interrupt System
ERROR/INT0
NPCM/INT1
MPIO_A
MPIO_B
MPIO_C
MPO0
MPO1
Figure 15. Default Routing Block Diagram
By default, the DIR receives data on RXIN2. When the DIR is unlocked, the XTI has priority, and uses the Main
port. When the DIR is locked, data from the MAIN PORT are DIR data.
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Multi-Channel PCM Routing Function
Overview
The DIX9211 has a multi-channel PCM routing function (maximum of eight channels) that can route
multi-channel PCM signals easily. This function is enabled by using all the MPIOs.
MPIO_A and MPIO_C are assigned as multi-channel PCM input ports and clock transition outputs (CLKST).
MPIO_B and the Main audio port are assigned as multi-channel PCM output ports. For some applications, these
multi-channel PCM output ports have five data pins. The DOUT pin and the MDOUT pin share the same data.
A detailed block diagram is shown in Figure 16.
FILT
AUXIN0
AUTO
RXIN0
RXIN0
RXIN1
RXIN1
RXIN2
RXIN2
AUXIN0
RXIN3
RXIN3
AUXIN1
RXIN4/ASCKI0
RXIN4
RXIN5/ABCKI0
RXIN5
RXIN6/ALRCKI0
RXIN6
RXIN7/ADIN0
RXIN7
DIR
XTI
PLL
Clock/Data
Recovery
SCKO
DIR
Lock: DIR
Unlock: XTI
Main
Output
Port
BCK
LRCK
DOUT
AUXIN2
AUTO
DIR
MPIO_A0 (MSCKI)
MPIO_A2 (MLRCKI)
XTI
Lock
Detection
MPIO_A1 (MBCKI)
DIT
AUXIN0
MPIO_A
Selector
AUXIN1
MPIO_A3 (MDIN0)
RECOUT0
DITOUT
AUXIN2
RECOUT1
RECOUT0
RECOUT1
DITOUT
MPO0
MPO0/1
Selector
MPO1
XTI Clock
AUTO
MPIO_C0 (CLKST)
DIR
MPIO_C1 (MDIN1)
XTI
MPIO_C2 (MDIN2)
MPIO_C
Selector
MPIO_B1 (MDOUT1)
AUXOUT
AUXIN0
AUXIN1
MPIO_C3 (MDIN3)
Note:
MPIO_B0 (MDOUT0)
AUXIN1
MPIO_B
Selector
AUXIN2
MPIO_B2 (MDOUT2)
MPIO_B3 (MDOUT3)
Blue lines are default signal path.
Figure 16. Multi-Channel PCM Routing Block Diagram
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Initial Setting
To use the multi-channel function, set Register MCHR to '1'. In the multi-channel function, the assigned MPIO
function for Registers MPASEL[1:0], MPBSEL[2:0], and MPCSEL[2:0], are invalid; in other words, Register
MCHR has greater priority than Registers MPASEL[1:0], MPBSLE[2:0], and MPCSEL[2:0].
NOTE
In multi-channel PCM mode, Register MCHR (20h) and Register MPAxHz (6Eh) must be
set to '0' in order to get the outputs from the main port.
Output Source Selection
The output source for Multi-Channel PCM Output (the Main output port and MPIO_B) is selected by a register.
Table 28 describes the relationship between the output source and the register (MCHRSRC) setting.
Table 28. Multi-Channel PCM Output Source and Register Setting
MULTI-CHANNEL MODE
OUTPUT SOURCE SELECT
(1)
MCHRSRC
'00' or '10'
'01' or '11'
CLOCK SOURCE
MAIN OUT
(1)
DOUT
MAIN OUT
(1)
MDIN0
MDOUT0
MAIN OUT
(1)
MDIN0
MDOUT1
Logic low
MDIN1
MDOUT2
Logic low
MDIN2
MDOUT3
Logic low
MDIN3
MULTI-CH INPUT
The Main OUT data source is discussed in the DIR section of this data sheet. It can either be the DIR
recovered clock and data, or the XTI clock source.
DSD Input Mode
The DIX9211 can also be used to suppress the jitter of the DSCKI signals, typically generated by an HDMI
receiver. DSD signals (DBCKI, DSDRI, DSDLI) are routed to the Main Port as DBCKO, DSDRO, and DSDLO,
respectively.
The DIT works with DSCKI for SCK, DBCKI for BCK, internally-created LRCK, DBCKI divided by 64, and '0' data
for DIN.
MOLRMTEN (Register 6Ah) can be used to mute/unmute DSDRO from the LRCK port. When MOLRMTEN is set
to '1', mute/unmute of DSDRO from LRCK is available by MODMUT = 1/0.
Table 29 summarizes the DSD input mode configuration.
Table 29. DSD Input Mode Summary
SIGNAL NAME
MPIO GROUP / PIN
DSCKI
MPIO_C0 or
MPIO_B0
DESCRIPTION
SCK input (256fS)
DBCKI
MPIO_C1 or
MPIO_B1
DBCK input for DSD format (64fS)
DSDRI
MPIO_C2 or
MPIO_B2
R-channel DSD data input for DSD format
DSDLI
MPIO_C3 or
MPIO_B3
L-channel DSD data input for DSD format
DSCKO
SCKO
DBCKO
BCK
SCK output generated by DIR from DIT output
DBCK output for DSD format (the same signal as DBCKI)
DSDRO
LRCK
R-channel DSD data output for DSD format (the same signal as DSDRI)
DSDLO
DOUT
L-channel DSD data output for DSD format(the same signal as DSDLI)
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Figure 17 illustrates the DSD format.
DBCK
DSDRI
1 2 3
62 63 64 1 2 3
DSDLI
1 2 3
62 63 64 1 2 3
Figure 17. DSD Format
Typical Register Settings
Table 30 and Table 31 show the typical register settings for DSD format.
Table 30. DSD Inputs From MPIO_Cx Ports
REGISTER SETTINGS
DESCRIPTIONS
34h = CFh
RXSEL = TXOUT
61h = 14h
TXDSD = Enable
6Bh = 14h
MOSSRC = DIR
MOPSRC = AUXIN1
Table 31. DSD Inputs From MPIO_Bx Ports
REGISTER SETTINGS
42
DESCRIPTIONS
34h = CFh
RXSEL = TXOUT
60h = 55h
TXSSRC = AUXIN2
TXPSRC = AUXIN2
61h = 14h
TXDSD = Enable
6Bh = 14h
MOSSRC = DIR
MOPSRC = AUXIN1
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Figure 18 shows a block diagram of DSD Input Mode (this illustration includes an example of DSD input =
MPIO_Cx pins).
FILT
AUXIN0
AUTO
RXIN0
RXIN0
RXIN1
RXIN1
RXIN2
RXIN2
AUXIN0
RXIN3
RXIN3
AUXIN1
RXIN4/ASCKI0
RXIN4
AUXIN2
RXIN5/ABCKI0
RXIN5
RXIN6/ALRCKI0
RXIN6
RXIN7/ADIN0
RXIN7
DIR
RXIN7
SCKO (DSCKO)
DIR
XTI
PLL
Main
Output
Port
DOUT
Clock/Data
Recovery
Lock: DIR
Unlock: XTI
BCK (DBCKO)
LRCK (DSDRO)
DOUT (DSDLO)
SCKO from DIR
BCK from AUXIN1
LRCK from AUXIN1
AUTO
DIR
MPIO_A0
RXIN8
MPIO_A1
RXIN9
MPIO_A
Selector
MPIO_A2
MPIO_A3
XTI
Lock
Detection
DIT
AUXIN0
RXIN10
AUXIN1
RXIN11
RECOUT0
DITOUT
RECOUT1
AUXIN2
RECOUT0
RECOUT1
DITOUT
MPO0
MPO0/1
Selector
MPO1
XTI Source
AUTO
MPIO_C0 (DSCKI)
DIR
MPIO_C1 (DBCKI)
XTI
MPIO_C2 (DSDRI)
MPIO_C
Selector
MPIO_B1
AUXOUT
AUXIN0
AUXIN1
MPIO_C3 (DSDLI)
Note:
MPIO_B0
AUXIN1
MPIO_B
Selector
AUXIN2
MPIO_B2
MPIO_B3
Blue lines are through-paths for DBCKI, DSDRI, and DSDLI. Red lines are DSCKO generation paths.
Figure 18. DSD Input Mode Block Diagram
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Serial Control Mode
The DIX9211 supports two types of control interface, which are set using the MODE pin (pin 27), as defined in
Table 32.
Table 32. Mode Control Interface Types
MODE
MODE CONTROL INTERFACE
Tied to DGND
Two-wire (I2C) serial control
Tied to VDD
Four-wire (SPI) serial control
The input state of the MODE pin is only sampled during a power-on reset or external reset event. Therefore, any
change after device power on or external reset is ignored.
Table 33 shows the pin assignments based on the control interface selected.
Table 33. Pin Assignments for SPI and I2C Control Interfaces
DEFINITION
PIN
SPI MODE
I2C MODE
23
MDO
ADR0
24
MDI
SDA
25
MC
SCL
26
MS
ADR1
Four-Wire (SPI) Serial Control
The DIX9211 includes an SPI-compatible serial port, which operates asynchronously to the audio serial interface.
The control interface consists of these data sources: MDI/SDA, MS/ADR1, MC/SCL, and MDO/ADR0.
• MDI is the serial data input to program the mode control registers. In other applications, this source may be
known as MOSI.
• MDO is the serial data output to read back register settings and some flags. In other applications, this source
may be known as MISO.
• MC is the serial bit clock to shift the data into the control port. In other applications, this clock may be known
as SCK.
• MS is the select input to enable the mode control port. In other applications, this control may be known as an
active-low Chip Select (CS).
Control Data Word Format
All single write/read operations via the serial control port use 16-bit data words. Figure 19 shows the control data
word format. The first bit is for read/write control, where '0' indicates a write operation and '1' shows a read
operation. The next seven bits, labeled ADR[6:0], set the register address for the write/read operation. The least
significant eight bits, D[7:0] on MDI or MDO, contain the data to be written to (or read from) the register specified
by ADR[6:0].
MSB
LSB
R/W ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
D7
D6
D5
Register Address
D4
D3
D2
D1
D0
Register Data
Figure 19. Control Data Word Format for MDI
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Register Write Operation
Figure 20 shows the functional timing diagram for a single write operation on the serial control port. MS is held at
'1' until a register must be written. To start the register write cycle, MS should be set to '0'. 16 clocks are then
provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle has
been completed, MS is set to '1' to latch the data into the indexed mode control register.
MS
MC
MDI
DC
‘0’
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
D7
D6
D5
D4
D3
D2
D1
D0
DC
DC
R/W ADR6
Figure 20. Register Write Operation
Channel status data are available from the Channel Status registers. To read the first 48 bits of the Channel
Status registers accurately, the read should be started 48fS after the start of the block. However, once MS is
pulled to '0', there are no time requirements in which to read the data because the registers are locked.
Both INT0 and INT1 can also be masked to highlight when the Channel Status has been updated. In many
cases, Channel Status does not change during playback (of a movie or music). Once the source changes,
though, the Channel Status changes. This change causes an interrupt, which can then be used to trigger the
DSP to read the Channel Status registers. The interrupt source is called OCSRNWx (Output Channel Status
Renewal).
The OCSRNWx flag can be held in the INTx register, or masked and brought out to the ERR/INT0 or
NPCM/INT1 pin.
Register Read Operation
Figure 21 shows the functional timing diagram for single read operations on the SPI serial control port. MS is
held high until a register is to be read. To start the register read cycle, MS is set to a low state. 16 clocks are
then provided on MC, corresponding to the first eight bits of the control data word on MDI, and second eight bits
of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is set to high for next
write or read operation. MDO remains in a Hi-Z (or high impedance) state except for a period of eight MC clocks
for actual data transfer.
MS
MC
MDI
MDO
DC
‘1’
Don’t Care (DC)
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Hi-Z
D7
D6
D5
D4
D3
D2
D1
R/W ADR6
D0
Hi-Z
Figure 21. Register Read Operation
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Timing Requirements
Figure 22 shows a detailed timing diagram for the four-wire serial control interface. These timing parameters are
critical for proper control port operation.
t MHH
MS
1.4 V
t MCH
tM S S
t MCL
t MS H
MC
1.4 V
t MCY
t MDS
MSB (R/W)
MDI
t MDH
LSB (D0)
ADR0
t MD D
Hi - Z
MDO
SYMBOL
tMCY
tMCL
tMCH
tMHH
tMSS
tMSH
tMDH
tMDS
tMDD
tMDR
t M DD
MSB (D7)
1.4 V
t MDR
LSB (D0 )
DESCRIPTION
MC Pulse cycle time
MC Low level time
MC High level time
MS High level time
MS Falling edge to MC rising edge
MS Rising edge from MC rising edge for LSB
MDI Hold time
MDI Set-up time
MDO Enable or delay time from MC falling edge
MDO Disable time from MS rising edge
Hi - Z
MIN
100
40
40
tMCY
30
15
15
15
0
0
0.5*VDD
MAX
30
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 22. Control Interface Timing Requirements
Two-Wire (I2C) Serial Control
The DIX9211 also supports the I2C serial bus and data transmission protocol. It can be configured for fast mode
as a slave device. This protocol is explained fully in the I2C specification 2.1.
Slave Address
MSB
1
LSB
0
0
0
0
ADR1
ADR0
R/W
The DIX9211 has seven bits for its own slave address. The first five bits (MSB) of the slave address are
factory-preset to '10000'. The next two bits of the address byte are selectable bits that can be set by MDO/ADR0
and MS/ADR1. A maximum of four DIX9211s can be connected on the same bus at one time. Each DIX9211
responds when it receives its own slave address.
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Packet Protocol
A master device must control the packet protocol, which consists of a start condition, slave address with
read/write bit, data if a write procedure is desired, or an acknowledgment if read and stop conditions exist. The
DIX9211 supports both slave receiver and transmitter functions. Details of the DATA pulse for both write and
read operations are described in Figure 23.
SDA
SCL
1–7
Slave address
St
Start
condition
R/W:
ACK:
DATA:
8
R/W
9
ACK
1–8
DATA
9
ACK
1– 8
DATA
9
ACK
9
ACK
Sp
Stop
condition
Read o peration if 1; otherwise, write operation
Acknowledgement of a byte if 0, n ot Acknowledgement of a bite if 1
8 b its ( byte) , Details are described in write and read operation
.
2
Figure 23. I C Packet Protocol
Write Operation
The DIX9211 can only function as an I2C slave. A master can write to any DIX9211 registers using either single
or multiple accesses. The master sends a DIX9211 slave address with a write bit, a register address, and the
data. When undefined registers are accessed, the DIX9211 does not send an acknowledgment. Figure 24
illustrates the write operation. The register address and the write data are 8-bit, MSB-first format.
Transmitter
Data Type
M
St
M
slave
address
M
W
S
ACK
M
reg
address
S
ACK
M
write
data 1
S
ACK
M
write
data 2
S
ACK
S
ACK
M
Sp
M: Master Device S: Slave Device St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition
Figure 24. Framework for Write Operation
Read Operation
A master can read the DIX9211 registers. The value of the register address is stored in an indirect index register
in advance. The master sends the DIX9211 slave address with a read bit after storing the register address. The
DIX9211 then transfers the data to which the index register points. Figure 25 shows the read operation.
Transmitter
Data Type
M
St
M
slave
address
M
W
S
ACK
M
S
reg address ACK
M
Sr
M
slave address
M
R
S
ACK
S
read
data
M
NACK
M
Sp
M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition W: Write R: Read
ACK: Acknowledge NACK: Not Acknowledge Sp: Stop Condition
Note:
The slave address after the repeated start condition must be the same as the previous slave address.
Figure 25. Framework for Read Operation
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Timing Diagram
Figure 26 shows the detailed timing diagram for SCL and SDA.
Start
Repeated Start
Stop
tSDA-F
tD-HD
tD-SU
tBUF
tP-SU
tSDA-R
SDA
tSCL-R
tGW
tS-HD
tLOW
SCL
tS-HD
tS-SU
tHI
tSCL-F
SYMBOL
fSCL
tBUF
tLOW
tHI
tS-SU
tS-HD
tD-SU
tD-HD
tSCL-R
tSCL-F
tSDA-R
tSDA-F
tP-SU
tGW
CB
VNH
VNL
VHYS
DESCRIPTION
SCL clock frequency
Bus free time between STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for START/Repeated START condition
Hold time for START/Repeated START condition
Data setup time
Data hold time
Rise time of SCL signal
Fall time of SCL signal
Rise time of SDA signal
Fall time of SDA signal
Setup time for STOP condition
Allowable glitch width
Capacitive load for SDA and SCL line
Noise margin at High level for each connected device
(including hysteresis)
Noise margin at Low level for each connected device
(including hysteresis)
Hysteresis of Schmitt-trigger input
STANDARD MODE
MIN
MAX
100
4.7
4.7
4.0
4.7
4.0
250
0
3450
1000
1000
1000
1000
4.0
n/a
400
20
20
20
20
FAST MODE
MIN
MAX
400
1.3
1.3
0.6
0.6
0.6
100
0
900
+ 0.1CB
300
+ 0.1CB
300
+ 0.1CB
300
+ 0.1CB
300
0.6
50
100
UNITS
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ms
ns
pF
0.2 × VDD
0.2 × VDD
V
0.1 × VDD
0.1 × *VDD
V
n/a
0.05 × VDD
V
Figure 26. Control Interface Timing
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APPLICATION INFORMATION
TYPICAL CIRCUIT CONNECTION
Figure 27 illustrates a typical circuit connection.
0V
0 V +3.3 V
C8
C5
0V
X1
Coax Input
C9
C7
R3
R1
R2
C6
48
47
46
45
44
43
42
41
40
39
38
37
RSV2
RSV1
RSV1
RSV2
FILT
VCC
AGND
XTO
XTI
GNDRX
RXIN0
1
RSV2
Interrupt
Flag
Functions
C10
ERROR/INT0
C12
VDDRX
36
+3.3 V
R4
2
NPCM/INT1
RXIN1
Coax Input
35
C11
29
9
MPIO_C2
RXIN7/ADIN0
28
10
MPIO_C3
MODE
27
11
MPIO_B0
MS/ADR1
26
12
MPIO_
B1
MC/SCL
25
22
MDI/
SDA
RXIN6/ALRCKIO
24
MPIO_C1
MDO/ADR0
8
23
30
DVDD
RXIN5/ABCKIO
DGND
MPIO_C0
21
7
SCKO
31
20
RXIN4/ASCKIO
BCK
MPIO_A3
19
6
LRCK
32
18
RXIN3
DOUT
MPIO_A2
17
5
MPO1
33
16
RXIN2
MPO0
MPIO_A1
15
4
MPIO_B3
34
14
MPIO_B
Assigned
Functions
RST
MPIO_
B2
MPIO_C
Assigned
Functions
MPIO_A0
13
MPIO_A
Assigned
Functions
3
Optical
Inputs
or
PCM Audio
Interface
0 V or 3.3 V
Serial Control
Interface
C13
0 V +3.3 V
MPIO_B
Assigned
Functions
MPOx_
Assigned
Functions
PCM Audio
Interface
Serial Control
Interface
R1: Loop filter resistor, 680 Ω.
R2: Current-limiting resistor; generally, a 100-Ω to 500-Ω resistor is used, but it depends on the crystal resonator.
R3, R4: Coax input termination resisters, 75 Ω.
C7, C12, C13: 0.1-mF ceramic capacitor and 10-mF electrolytic capacitor, depending on the power supply.
C5: Loop filter capacitor, 0.068 mF.
C6: Loop filter capacitor, 0.0047 mF.
C8, C9: OSC load capacitor; generally, a 10-pF to 30-pF capacitor is used, but it depends on the crystal resonator
and PCB layout.
C10, C11: DC blocking capacitor for coax input, 0.1 mF.
X1: Crystal resonator. Use a 24.576-MHz fundamental resonator when the XTI clock source is needed.
Figure 27. Typical Circuit Connection
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REGISTER INFORMATION
Table 34. REGISTER MAP
ADR
R/W
B7
B6
B5
B4
B3
B2
B1
B0
20h
ERROR Output Condition and Shared Port
Settings
R/W
RSV
ERRCON
MCHR
RSV
ERRHZ
ERRSEL
NPCMHZ
NPCMSEL
21h
DIR Initial Settings 1/3
R/W
RSV
RSV
RSV
RXFSRNG
RSV
RSV
RSV
RSV
22h
DIR Initial Settings 2/3
R/W
RSV
CLKSTCON
RSV
CLKSTP
RSV
RSV
RSV
RXVDLY
23h
DIR Initial Settings 3/3
R/W
RSV
RSV
XTIWT1
XTIWT0
PRTPRO1
PRTPRO0
ERRWT1
ERRWT0
24h
Oscillation Circuit Control
R/W
OSCAUTO
RSV
RSV
XMCKEN
XMCKDIV1
XMCKDIV0
RSV
RSV
25h
ERROR Cause Setting
R/W
RSV
RSV
EFSCHG
EFSLMT
ENPCM
EVALID
EPARITY
EUNLOCK
26h
AUTO Source Selector Cause Setting
R/W
RSV
AERROR
RSV
AFSLMT
ANPCM
AVALID
RSV
AUNLOCK
27h
DIR Acceptable fS Range Setting and Mask
R/W
MSK128
MSK64
RSV
NOMLMT
HILMT1
HILMT0
LOLMT1
LOLMT0
28h
Non-PCM Definition Setting
R/W
RSV
RSV
CS1BPLS
NPCMP
RSV
DTSCD
PAPB
CSBIT1
29h
DTS CD/LD Detection Setting
R/W
RSV
RSV
RSV
RSV
DTS16
DTS14
DTSPRD1
DTSPRD0
2Ah
INT0 Output Cause Mask Setting
R/W
MERROR0
MNPCM0
MEMPHF0
MDTSCD0
MCSRNW0
MPCRNW0
MFSCHG0
RSV
2Bh
INT1 Output Cause Mask Setting
R/W
MERROR1
MNPCM1
MEMPHF1
MDTSCD1
MCSRNW1
MPCRNW1
MFSCHG1
RSV
2Ch
INT0 Output Register
R
OERROR0
ONPCM0
OEMPHF0
ODTSCD0
OCSRNW0
OPCRNW0
OFSCHG0
RSV
2Dh
INT1 Output Register
R
OERROR1
ONPCM1
OEMPHF1
ODTSCD1
OCSRNW1
OPCRNW1
OFSCHG1
OADLVL1
2Eh
INT0, INT1 Output Polarity Setting
R/W
RSV
INT1P
RSV
RSV
RSV
INT0P
RSV
RSV
2Fh
DIR Output Data Format
R/W
RSV
RSV
RSV
RSV
RSV
RXFMT2
RXFMT1
RXFMT0
30h
DIR Recovered System Clock Ratio Setting
R/W
RSV
RSV
RSV
PSCKAUTO
RSV
PSCK2
PSCK1
PSCK0
31h
XTI Source Clock Frequency Setting
R/W
RSV
RSV
XSCK1
XSCK0
XBCK1
XBCK0
XLRCK1
XLRCK0
32h
DIR Source, Sec. Bit/LR Clock Frequency
Setting
R/W
RSV
PSBCK2
PSBCK1
PSBCK0
RSV
PSLRCK2
PSLRCK1
PSLRCK0
33h
XTI Source, Sec. Bit/LR Clock Frequency
Setting
R/W
RSV
XSBCK2
XSBCK1
XSBCK0
RSV
XSLRCK2
XSLRCK1
XSLRCK0
34h
DIR Input Biphase Source Select, Coax Amp.
Control
R/W
RX0DIS
RX1DIS
RSV
RSV
RXSEL3
RXSEL2
RXSEL1
RXSEL0
35h
RECOUT0 Output Biphase Source Select
R/W
RSV
RSV
RSV
MPO0MUT
RO0SEL3
RO0SEL2
RO0SEL1
RO0SEL0
36h
RECOUT1 Output Biphase Source Select
R/W
RSV
RSV
RSV
MPO1MUT
RO1SEL3
RO1SEL2
RO1SEL1
RO1SEL0
37h
Port fS Calculator Measurement Target Setting
R/W
RSV
RSV
RSV
RSV
RSV
PFSTGT2
PFSTGT1
PFSTGT0
38h
Port fS Calculator Result Output
R
PFSST
PFSPO2
PFSPO1
PFSPO0
PFSOUT3
PFSOUT2
PFSOUT1
PFSOUT0
39h
Incoming Biphase Information and Calculated
fS Output
R
SFSST
SCSBIT1
RSV
RSV
SFSOUT3
SFSOUT2
SFSOUT1
SFSOUT0
3Ah
PC Buffer Byte0 (Burst Preamble PC Output
Register)
R
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
3Bh
PC Buffer Byte1 (Burst Preamble PC Output
Register)
R
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
3Ch
PD Buffer Byte0 (Burst Preamble PD Output
Register)
R
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
3Dh
PD Buffer Byte1 (Burst Preamble PD Output
Register)
R
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
40h
System Reset Control
R/W
MRST
RSV
ADDIS
RXDIS
RSV
RSV
TXDIS
XODIS
42h
External ADC Function Control
R/W
RSV
RSV
RSV
ADDTRX7
RSV
EADCLK2
EADCLK1
EADCLK0
5Ah
DIR Channel Status Data Buffer 1/6
R
RXCS7
RXCS6
RXCS5
RXCS4
RXCS3
RXCS2
RXCS1
RXCS0
5Bh
DIR Channel Status Data Buffer 2/6
R
RXCS15
RXCS14
RXCS13
RXCS12
RXCS11
RXCS10
RXCS9
RXCS8
5Ch
DIR Channel Status Data Buffer 3/6
R
RXCS23
RXCS22
RXCS21
RXCS20
RXCS19
RXCS18
RXCS17
RXCS16
5Dh
DIR Channel Status Data Buffer 4/6
R
RXCS31
RXCS30
RXCS29
RXCS28
EXCS27
RXCS26
RXCS25
RXCS24
5Eh
DIR Channel Status Data Buffer 5/6
R
RXCS39
RXCS38
RXCS37
RXCS36
RXCS35
RXCS34
RXCS33
RXCS32
5Fh
DIR Channel Status Data Buffer 6/6
R
RXCS47
RXCS46
RXCS45
RXCS44
RXCS43
RXCS42
RXCS41
RXCS40
60h
DIT Function Control 1/3
R/W
RSV
TXSSRC2
TXSSRC1
TXSSRC0
RSV
TXPSRC2
TXPSRC1
TXPSRC0
61h
DIT Function Control 2/3
R/W
RSV
TXSCK2
TXSCK1
TXSCK0
RSV
RSV
TXFMT1
TXFMT0
62h
DIT Function Control 3/3
R/W
RSV
RSV
TXDMUT
RSV
TXVFLG
RSV
RSV
RSV
63h
DIT Channel Status Data Buffer 1/6
R/W
TXCS7
TXCS6
TXCS5
TXCS4
TXCS3
TXCS2
TXCS1
TXCS0
64h
DIT Channel Status Data Buffer 2/6
R/W
TXCS15
TXCS14
TXCS13
TXCS12
TXCS11
TXCS10
TXCS9
TXCS8
65h
DIT Channel Status Data Buffer 3/6
R/W
TXCS23
TXCS22
TXCS21
TXCS20
TXCS19
TXCS18
TXCS17
TXCS16
66h
DIT Channel Status Data Buffer 4/6
R/W
TXCS31
TXCS30
TXCS29
TXCS28
TXCS27
TXCS26
TXCS25
TXCS24
67h
DIT Channel Status Data Buffer 5/6
R/W
TXCS39
TXCS38
TXCS37
TXCS36
TXCS35
TXCS34
TXCS33
TXCS32
68h
DIT Channel Status Data Buffer 6/6
R/W
TXCS47
TXCS46
TXCS45
TXCS44
TXCS43
TXCS42
TXCS41
TXCS40
50
REGISTER DESCRIPTION
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Table 34. REGISTER MAP (continued)
ADR
R/W
B7
B6
B5
B4
B3
B2
B1
B0
6Ah
Main Output and AUXOUT Port Data Mute
Control
REGISTER DESCRIPTION
R/W
AOMUTAS
MOMUTAS
RSV
RSV
AOLRMTEN
AODMUT
MOLRMTE
N
MODMUT
6Bh
Main Output Port, Output Source Setting
R/W
RSV
MOSSRC2
MOSSRC1
MOSSRC0
RSV
MOPSRC2
MOPSRC1
MOPSRC0
6Ch
AUX Output Port, Output Source Setting
R/W
RSV
AOSSRC2
AOSSRC1
AOSSRC0
RSV
AOPSRC2
AOPSRC1
AOPSRC0
6Dh
MPIO_B & Main Output Port Hi-Z Control
R/W
MPB3HZ
MPB2HZ
MPB1HZ
MPB0HZ
SCKOHZ
BCKHZ
LRCKHZ
DOUTHZ
6Eh
MPIO_C and MPIO_A Hi-Z Control
R/W
MPC3HZ
MPC2HZ
MPC1HZ
MPC0HZ
MPA3HZ
MPA2HZ
MPA1HZ
MPA0HZ
6Fh
MPIO_A, MPIO_B, MPIO_C Group Function
Assign
R/W
MPASEL1
MPASEL0
MPBSEL2
MPBSEL1
MPBSEL0
MPCSEL2
MPCSEL1
MPCSEL0
70h
MPIO_A, Flags/GPIO Assign Setting
R/W
RSV
RSV
MCHSRC1
MCHSRC0
MPA3SEL
MPA2SEL
MPA1SEL
MPA0SEL
71h
MPIO_B, MPIO_C, Flags/GPIO Assign Setting
R/W
MPB3SEL
MPB2SEL
MPB1SEL
MPB0SEL
MPC3SEL
MPC2SEL
MPC1SEL
MPC0SEL
72h
MPIO_A1, MPIO_A0 Output Flag Select
R/W
MPA1FLG3
MPA1FLG2
MPA1FLG1
MPA1FLG0
MPA0FLG3
MPA0FLG2
MPA0FLG1
MPA0FLG0
73h
MPIO_A3, MPIO_A2 Output Flag Select
R/W
MPA3FLG3
MPA3FLG2
MPA3FLG1
MPA3FLG0
MPA2FLG3
MPA2FLG2
MPA2FLG1
MPA2FLG0
74h
MPIO_B1, MPIO_B0 Output Flag Select
R/W
MPB1FLG3
MPB1FLG2
MPB1FLG1
MPB1FLG0
MPB0FLG3
MPB0FLG2
MPB0FLG1
MPB0FLG0
75h
MPIO_B3, MPIO_B2 Output Flag Select
R/W
MPB3FLG3
MPB3FLG2
MPB3FLG1
MPB3FLG0
MPB2FLG3
MPB2FLG2
MPB2FLG1
MPB2FLG0
76h
MPIO_C1, MPIO_C0 Output Flag Select
R/W
MPC1FLG3
MPC1FLG2
MPC1FLG1
MPC1FLG0
MPC0FLG3
MPC0FLG2
MPC0FLG1
MPC0FLG0
77h
MPIO_C3, MPIO_C2 Output Flag Select
R/W
MPC3FLG3
MPC3FLG2
MPC3FLG1
MPC3FLG0
MPC2FLG3
MPC2FLG2
MPC2FLG1
MPB2FLG0
78h
MPO1, MPO0 Function Assign Setting
R/W
MPO1SEL3
MPO1SEL2
MPO1SEL1
MPO1SEL0
MPO0SEL3
MPO0SEL2
MPO0SEL1
MPO0SEL0
79h
GPIO I/O Direction control for MPIO_A,
MPIO_B
R/W
GIOB3DIR
GIOB2DIR
GIOB1DIR
GIOB0DIR
GIOA3DIR
GIOA2DIR
GIOA1DIR
GIOA0DIR
7Ah
GPIO I/O Direction control for MPIO_C
R/W
RSV
RSV
RSV
RSV
GIOC3DIR
GIOC2DIR
GIOC1DIR
GIOC0DIR
7Bh
GPIO Output Data Setting for MPIO_A,
MPIO_B
R/W
GPOB3
GPOB2
GPOB1
GPOB0
GPOA3
GPOA2
GPOA1
GPOA0
7Ch
GPIO Output Data Setting for MPIO_C
R/W
RSV
RSV
RSV
RSV
GPOC3
GPOC2
GPOC1
GPOC0
7Dh
GPIO Input Data Register for MPIO_A,
MPIO_B
R
GPIB3
GPIB2
GPIB1
GPIB0
GPIA3
GPIA2
GPIA1
GPIA0
7Eh
GPIO Input Data Register for MPIO_C
R
RSV
RSV
RSV
RSV
GPIC3
GPIC2
GPIC1
GPIC0
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REGISTER DESCRIPTIONS
NOTE
Memo boxes are provided to aid in development. Record your register settings below for
future reference.
Register 20h, ERROR Output Condition and Shared Port Settings
(Address: 20h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
ERRCON
0
B5
MCHR
0
B4
RSV
0
B3
ERRHZ
0
B2
ERRSEL
0
B1
NPCMHZ
0
B0
NPCMSEL
0
ERRCON: ERROR Output Condition Setting
0: ERROR pin output is always DIR status (default)
1: ERROR output depends on source control MOPSRC[2:0]
DIR/AUTO: Output DIR status
Except DIR: ERROR outputs high (error status).
MCHR: MPIO/Multi-Channel PCM Routing Select
0: All MPIOs are controlled by MPASEL[1:0], MPBSEL[1:0], MPCSEL[2:0] (Default)
1: All MPIOs are assigned for Multi-Channel PCM Routing I/O.
ERRHZ: ERROR/INT0 Port Output Hi-Z Control
0: Output (default)
1: Hi-Z
ERRSEL: ERROR/INT0 Port Output Source Select
0: ERROR (default)
1: INT0
NOTE: ERRSEL must be '0' when Register 26h/AERROR = 1 or Register 42h/ADFSLMT = 1, or if the
signal CLKST is used.
NPCMHZ: NPCM/INT1 Port Output Hi-Z Control
0: Output (default)
1: Hi-Z
NPCMSEL: NPCM/INT1 Port Output Source Select
0: NPCM (default)
1: INT1
spacer
52
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Register 21h, DIR Initial Settings 1/3
(Address: 21h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
RXFSRNG
0
B3
RSV
0
B2
RSV
0
B1
RSV
0
B0
RSV
0
B1
RSV
0
B0
RXVDLY
1
RXFSRNG: DIR Receivable Incoming Biphase Sampling Frequency Range Setting
0: Wide Mode (7 kHz to 216 kHz) (default)
1: Normal Mode (28 kHz to 108 kHz)
spacer
Register 22h, DIR Initial Settings 2/3
(Address: 22h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
CLKSTCON
0
B5
RSV
0
B4
CLKSTP
0
B3
RSV
0
B2
RSV
0
CLKSTCON: CLKST Output Condition Setting
0: Only PLL Lock status change (default)
1: All events where the Main port output clock condition changes, as well as these cases:
1. MOSSRC/MOPSRC Register is updated to XTI, AUXIN0, AUXIN1, or AUXIN2
2. DIR and XTI are switched by DIR status when MOSSRC = 000(AUTO) and MOPSRC =
000(AUTO)
3. Main port sampling frequency changes when PFSTGT = 101(Main output port)
NOTES:
• CLKST never outputs when updating MOSSRC and MOPSRC to AUTO or DIR.
• OSCAUTO must be '0' when CLKST is used because CLKST is generated by frequency counting of
built-in oscillator circuit.
• To output CLKST, MOSSRC and MOPSRC are set simultaneously.
CLKSTP: CLKST Polarity Setting
0: Active low (default)
1: Active high
RXVDLY: VOUT Delay Setting
0: VOUT is active immediately after validity flag is detected
1: VOUT is active after synchronization with DOUT data (default)
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Register 23h, DIR Initial Settings 3/3
(Address: 23h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
XTIWT1
0
B4
XTIWT0
0
B3
PRTPRO1
0
B2
PRTPRO0
1
B1
ERRWT1
0
B0
ERRWT0
0
XTIWT[1:0]: Crystal OSC, Oscillation Start-up Wait Time Setting
00: 25 ms
01: 50 ms
10: 100 ms
11: 200 ms
XTIWT is counted by the PLL generated clock.
These are the resulting values when the PLL is running with a free-run clock because of no S/PDIF input.
After these delay times, the Main Port source changes from DIR to XTI when DIR is unlocked.
PRTPRO[1:0]: Process for Parity Error Detection
00: No process
01: For PCM data only, an 8x continuous parity error is replaced by previous data and muted after ninth
parity error at EPARITY = 1 (default)
10: For PCM and non-PCM data, an 8x continuous parity error is replaced by previous data and muted
after ninth parity error at EPARITY = 1
11: Reserved (The definition of Non-PCM depends on the Non-PCM Definition Setting Register)
Validity flag, user bit, channel status, Non-PCM and DTS-CD detection should be refreshed by waiting
more than 192/fS without any parity error.
ERRWT[1:0]: ERROR Release Wait Time Setting
00: ERROR Release after 48 counts of preamble B (Default), 192 ms at fS = 48 kHz
01: ERROR Release after 12 counts of preamble B
10: ERROR Release after six counts of preamble B
11: ERROR Release after three counts of preamble B
These counts are only available when DIR is unlocked or DIR sampling frequency is changed or exceeds
limits defined by DIR Acceptable fS Range Setting and Mask registers.
CLKST also uses ERRWT to release.
54
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Register 24h, Oscillation Circuit Control
(Address: 24h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
OSCAUTO
0
B6
RSV
0
B5
RSV
0
B4
XMCKEN
0
B3
XMCKDIV1
0
B2
XMCKDIV0
0
B1
RSV
0
B0
RSV
0
OSCAUTO: Oscillation Circuit Automatic Operation Control
0: Built-in oscillator circuit always operates (default)
1: Built-in oscillator circuit is stopped during lock state of DIR but is active when DIR locks and CLKST
is active
NOTES:
• The XODIS command has more priority than this OSCAUTO register.
• If XODIS is set to power down, the XTI source is not output.
XMCKENX: MCKO (XTI Clock Buffered Output) Output Enable Control
0: MUTE (Logic low level) (default)
1: Output
XMCKDIV[1:0]: XMCKO (XTI Clock Buffered Output) Output Clock Dividing Ratio
00: XTI/1 (24.576 MHz) (default)
01: XTI/2 (12.288 MHz)
10: XTI/4 (6.144 MHz)
11: XTI/8 (3.072 MHz)
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Register 25h, ERROR Cause Setting
(Address: 25h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
EFSCHG
0
B4
EFSLMT
0
B3
ENPCM
0
B2
EVALID
0
B1
EPARITY
0
B0
EUNLOCK
1
The following ERROR Cause Setting registers are independent of the AUTO Source Selector Cause Setting
Register (Register 26h).
EFSCHG: DIR Sampling Frequency Change
0: Not selected (default)
1: Selected
EFSLMT: DIR Limiting Acceptable Sampling Frequency
0: Not selected (default)
1: Selected
The definition of receivable sampling frequency range depends on the fS Limit Setting Register.
ENPCM: Non-PCM
0: Not selected (default)
1: Selected
The definition of non-PCM is depend on the Non-PCM Definition Setting Register.
EVALID: Validity Flag
0: Not selected (default)
1: Selected
EPARITY: Parity Error
0: Not selected (default)
1: Selected
EUNLOCK: PLL Lock Error
0: Not selected
1: Selected (default)
This register is used for setting the ERROR output factor.
The required factors of ERROR set to '1' are selected based on OR logic.
56
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Register 26h, AUTO Source Selector Cause Setting
(Address: 26h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
AERROR
0
B5
RSV
0
B4
AFSLMT
0
B3
ANPCM
0
B2
AVALID
0
B1
RSV
0
B0
AUNLOCK
1
The AUTO source selector is an automatic selector that outputs DIR or XTI output based on the following
register settings. The following AUTO Source Selector Cause Setting registers are independent of the ERROR
Cause Setting Register (Register 25h).
AERROR: ERROR
0: Not selected (default)
1: Selected
ERROR condition is defined by the ERROR Cause Setting Register (Register 25h).
AFSLMT: Limiting Acceptable Sampling Frequency
0: Not selected (default)
1: Selected
The definition of receivable sampling frequency range depends on the fS Limit Setting Register.
ANPCM: Non-PCM
0: Not selected (default)
1: Selected
The definition of Non PCM is depend on the Non-PCM Definition Setting Register.
AVALID: Validity Flag
0: Not selected (default)
1: Selected
AUNLOCK: PLL Lock Error
0: Not selected
1: Selected (default)
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Register 27h, DIR Acceptable fS Range Setting and Mask
(Address: 27h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MSK128
0
B6
MSK64
0
B5
RSV
0
B4
NOMLMT
0
B3
HILMT1
0
B2
HILMT0
0
B1
LOLMT1
0
B0
LOLMT0
0
MSK128: Mask for fS = 128 kHz
0: No mask (default)
1: Mask
DIX9211 does not receive 128-kHz sampling frequency.
This register setting is effective with NOMLMT = '1'.
MSK64: Mask for fS = 64 kHz
0: No mask (default)
1: Mask
DIX9211 does not receive 64-kHz sampling frequency.
This register setting is effective with NOMLMT = '1'.
NOMLMT: Receive Nominal Audio fS within ±2%
0: No limit (default)
1: Limit
DIX9211 receives the nominal audio sampling frequencies within ±2%.
The nominal audio sampling frequencies are: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz,
32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz, 192 kHz
HILMT[1:0]: Acceptable fS Higher Limit Setting
00: No limit (default)
01: fS = 54 kHz
10: fS = 108 kHz
11: fS = 216 kHz
LOLMT[1:0]: Acceptable fS Lower Limit Setting
00: No limit (default)
01: fS = 7 kHz
10: fS = 14 kHz
11: fS = 28 kHz
This condition of receivable sampling frequency is used as the ERROR and AUTO source selection when
EFSLMT or AFSLMT is set to '1'.
58
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Register 28h, Non-PCM Definition
(Address: 28h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
CS1BPLS
0
B4
NPCMP
0
B3
RSV
0
B2
DTSCD
0
B1
PAPB
1
B0
CSBIT1
1
CS1BPLS: CSBIT1 Detection Signal Select
0: Hold value (default)
1: Pulse
NPCMP: NPCM Pin Output Polarity
0: Active high (default)
1: Active low
DTSCD: DTS CD/LD Detection
0: Unselected (default)
1: Selected
PAPB: Burst Preamble PA and PB Detection
0: Unselected
1: Selected (default)
CSBIT1: Channel Status Bit1 = 1 Detection
0: Unselected
1: Selected (default)
This register is used to set the definition of non-PCM data. The NPCM pin output and NPCM Register Flag
output follow this definition.
There are three types of non-PCM factors to be selected, based on OR logic.
NOTE
The DTSCD Register (Register 29h) must be '1' (that is, selected) in order to output the
DTSCD flag from the MPIO, MPO, and INT pins as DIR Flag outputs.
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Register 29h, DTS-CD/LD Sync Word and Period Detection Setting
(Address: 29h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
RSV
0
B3
DTS16
1
B2
DTS14
1
B1
DTSPRD1
0
B0
DTSPRD0
0
DTS16: DTS-CD/LD 16-bit Sync Word Detection
0: Unselected
1: Selected (default)
DTS14: DTS-CD/LD 14-bit Sync Word Detection
0: Unselected
1: Selected (default)
DTSPRD[1:0]: DTS-CD/LD Sync Word Detection Period
00: No period, detect one sync word (default)
01: One period
10: Two periods
11: Four periods
NOTE
The DTSCD Register (Register 28h) must be '1' (that is, selected) in order to output the
DTSCD flag from the MPIO, MPO, and INT pins as DIR Flag outputs.
60
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Register 2Ah, INT0 Output Cause Mask Setting
(Address: 2Ah, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MERROR0
1
B6
MNPCM0
1
B5
MEMPHF0
1
B4
MDTSCD0
1
B3
MCSRNW0
1
B2
MPCRNW0
1
B1
MFSCHG0
1
B0
RSV
1
MERROR0: ERROR Port Output Status
0: Not masked
1: Masked (default)
MNPCM0: NPCM Port Output Status
0: Not masked
1: Masked (default)
This register setting follows the register setting of non-PCM data identification.
MEMPHF0: Emphasis Flag in Channel Status
0: Not masked
1: Masked (default)
MDTSCD0: DTS-CD/LD Sync Detection
0: Not masked
1: Masked (default)
This detection condition depends on the register setting for DTS-CD/LD detection conditions.
MCSRNW0: Channel Status Data of Beginning 48-bit Renewal
0: Not masked
1: Masked (default)
MPCRNW0: Burst Preamble PC Renewal
0: Not masked
1: Masked (default)
MFSCHG0: Renewal Flag of fS Calculator Result
0: Not masked
1: Masked (default)
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Register 2Bh, INT1 Output Cause Mask Setting
(Address: 2Bh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MERROR1
1
B6
MNPCM1
1
B5
MEMPHF1
1
B4
MDTSCD1
1
B3
MCSRNW1
1
B2
MPCRNW1
1
B1
MFSCHG1
1
B0
RSV
1
MERROR1: ERROR Port Output Status
0: Not masked
1: Masked (default)
MNPCM1: NPCM Port Output Status
0: Not masked
1: Masked (default)
This register setting follows the register setting of non-PCM data identification.
MEMPHF1: Emphasis Flag in Channel Status
0: Not masked
1: Masked (default)
MDTSCD1: DTS-CD/LD Sync Detection
0: Not masked
1: Masked (default)
This detection condition depends on the register setting for DTS-CD/LD detection conditions.
MCSRNW1: Channel Status Data of Beginning 48-bit Renewal
0: Not masked
1: Masked (default)
MPCRNW1: Burst Preamble PC Renewal
0: Not masked
1: Masked (default)
MFSCHG1: Renewal Flag of fS Calculator Result
0: Not masked
1: Masked (default)
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Register 2Ch, INT0 Output Register
(Address: 2Ch, Read-Only)
DATA
Reg Name
Default Value
Memo
B7
OERROR0
N/A
B6
ONPCM0
N/A
B5
OEMPHF0
N/A
B4
ODTSCD0
N/A
B3
OCSRNW0
N/A
B2
OPCRNW0
N/A
B1
OFSCHG0
N/A
B0
RSV
0
OERROR0: ERROR Port Output Status
0: No ERROR
1: Detect ERROR
This register setting follows the register setting of the ERROR factor.
ONPCM0: NPCM Port Output Status
0: PCM data
1: Non-PCM data
This register setting follows the register setting of non-PCM data identification.
OEMPHF0: Emphasis Flag in Channel Status
0: No emphasis
1: Emphasis
ODTSCD0: DTS-CD/LD Detection
0: No DTS-CD/LD
1: DTS-CD/LD
This register setting follows the register setting for DTS-CD/LD detection conditions.
OCSRNW0: Channel Status Data of Beginning 48-bit Renewal
0: Not detect renewal
1: Detect renewal
OPCRNW0: Burst Preamble PC Renewal
0: Not detect renewal
1: Detect renewal
OFSCHG0: Renewal Flag of fS Calculator Result
0: Not detect renewal
1: Detect renewal
When this register is read, the INT0 output is cleared.
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Register 2Dh, INT1 Output Register
(Address: 2Dh, Read-Only)
DATA
Reg Name
Default Value
Memo
B7
OERROR1
N/A
B6
ONPCM1
N/A
B5
OEMPHF1
N/A
B4
ODTSCD1
N/A
B3
OCSRNW1
N/A
B2
OPCRNW1
N/A
B1
OFSCHG1
N/A
B0
OADLVL1
N/A
OERROR1: ERROR Port Output Status
0: No ERROR
1: Detect ERROR
This register setting follows the register setting of the ERROR factor.
ONPCM1: NPCM Port Output Status
0: PCM data
1: Non-PCM data
This register setting follows the register setting of non-PCM data identification.
OEMPHF1: Emphasis Flag in Channel Status
0: No emphasis
1: Emphasis
ODTSCD1: DTS-CD/LD Detection
0: No DTS-CD/LD
1: DTS-CD/LD
This register setting follows the register setting for DTS-CD/LD detection conditions.
OCSRNW1: Channel Status Data of Beginning 48-bit Renewal
0: Not detect renewal
1: Detect renewal
OPCRNW1:Burst Preamble PC Renewal
0: Not detect renewal
1: Detect renewal
OFSCHG1: Renewal Flag of fS Calculator Result
0: Not detect renewal
1: Detect renewal
OADLVL1: ADC Input Level Detection Status
0: Not detect the defined threshold input level
1: Detect the defined threshold input level
NOTE: The threshold input level is defined by Register 2Eh, ADLVLTH[1:0].
When this register is read, the INT1 output is cleared.
64
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Register 2Eh, INT0, INT1 Output Polarity Setting
(Address: 2Eh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
INT1P
0
B5
RSV
0
B4
RSV
0
B3
RSV
0
B2
INT0P
0
B1
RSV
0
B0
RSV
0
INT1P: INT1 Port, Polarity Setting
0: Negative logic (default)
1: Positive logic
INT0P: INT0 Port, Polarity Setting
0: Negative logic (default)
1: Positive logic
When the INT0 or INT1 Information Register is read, Register INT0 or INT1 port output is cleared.
Register 2Fh, DIR Output Data Format
(Address: 2Fh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
RSV
0
B3
RSV
0
B2
RXFMT2
1
B1
RXFMT1
0
B0
RXFMT0
0
RXFMT[2:0]: DIR Output Data Format Setting
000: 24-bit MSB first, right-justified
001: Reserved
010: Reserved
011: 16-bit MSB first, right-justified
100: 24-bit MSB first, I2S (default)
101: 24-bit MSB first, left-justified
110: Reserved
111: Reserved
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Register 30h, DIR Recovered System Clock (SCK) Ratio Setting
(Address: 30h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
PSCKAUTO
0
B3
RSV
0
B2
PSCK2
0
B1
PSCK1
1
B0
PSCK0
0
PSCKAUTO: PLL SCK Dividing Ratio Automatic Control Setting
0: Disable (default)
1: Enable
This register is used to set the PLL SCK dividing ratio automatic control function.
SCK setting is automatically set depending on the input sampling frequency.
512fS: 54 kHz and below
256fS: 54 kHz to 108 kHz
128fS: 108 kHz and above or unlocked
The register setting of PSCKAUTO is prioritized higher than the PSCK[2:0] register setting.
For instance, if PSCKAUTO = '1', the PSCK[2:0] register setting is ignored.
To use this function, the XTI clock source is required.
PSCK[2:0]: DIR Recovered Clock Frequency Setting
000: 128fS
001: Reserved
010: 256fS (default)
011: Reserved
100: 512fS
101: Reserved
110: Reserved
111: Reserved
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Register 31h, XTI Source, Clock (SCK/BCK/LRCK) Frequency Setting
(Address: 31h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
XSCK1
0
B4
XSCK0
1
B3
XBCK1
1
B2
XBCK0
0
B1
XLRCK1
1
B0
XLRCK0
0
XSCK[1:0]: XTI Clock Source Frequency Setting
00: XTI/1 (24.576 MHz)
01: XTI/2 (12.288 MHz) (default)
10: XTI/4 (6.144 MHz)
11: XTI/8 (3.072 MHz)
XBCK[1:0]: XTI Clock Source BCK Frequency Setting
00: XTI/2 (12.288 MHz)
01: XTI/4 (6.144 MHz)
10: XTI/8 (3.072 MHz) (default)
11: XTI/16 (1.536 MHz)
XLRCK[1:0]: XTI Clock Source LRCK Frequency Setting
00: XTI/128 (192 kHz)
01: XTI/256 (96 kHz)
10: XTI/512 (48 kHz) (default)
11: XTI/1024 (24 kHz)
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Register 32h, DIR Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
(Address: 32h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
PSBCK2
0
B5
PSBCK1
1
B4
PSBCK0
0
B3
RSV
0
B2
PSLRCK2
0
B1
PSLRCK1
1
B0
PSLRCK0
0
PSBCK[2:0]: DIR Clock Source, Secondary BCK (SBCK) Frequency Setting
000: 16fS (BCK/4)
001: 32fS (BCK/2)
010: 64fS (1x BCK) (default)
011: 128fS (2x BCK)
100: 256fS (4x BCK)
101: Reserved
110: Reserved
111: Reserved
PSLRCK[2:0]: DIR Clock Source, Secondary LRCK (SLRCK) Frequency Setting
000: fS/4 (LRCK/4)
001: fS/2 (LRCK/2)
010: fS (1x LRCK) (default)
011: 2fS (2x LRCK)
100: 4fS (4x LRCK)
101: Reserved
110: Reserved
111: Reserved
spacer
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Register 33h, XTI Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
(Address: 33h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
XSBCK2
0
B5
XSBCK1
1
B4
XSBCK0
0
B3
RSV
0
B2
XSLRCK2
0
B1
XSLRCK1
1
B0
XSLRCK0
0
XSBCK[2:0]: XTI Clock Source, Secondary BCK (SBCK) Frequency Setting
000: XTI/2 (12.288 MHz)
001: XTI/4 (6.144 MHz)
010: XTI/8 (3.072 MHz) (default)
011: XTI/16 (1.536 MHz)
100: XTI/32 (0.768 MHz)
101: Reserved
110: Reserved
111: Reserved
XSLRCK[2:0]: XTI Clock Source, Secondary LRCK (SLRCK) Frequency Setting
000: XTI/128 (192 kHz)
001: XTI/256 (96 kHz)
010: XTI/512 (48 kHz) (default)
011: XTI/1024 (24 kHz)
100: XTI/2048 (12 kHz)
101: Reserved
110: Reserved
111: Reserved
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Register 34h, DIR Input Biphase Source Select, Coax Amplifier Control
(Address: 34h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RX0DIS
1
B6
RX1DIS
1
B5
RSV
0
B4
RSV
0
B3
RXSEL3
0
B2
RXSEL2
0
B1
RXSEL1
1
B0
RXSEL0
0
RX0DIS: Power Down for RXIN0 Coaxial Amplifier
0: Normal operation
1: Power down (default)
RX1DIS: Power Down for RXIN1 Coaxial Amplifier
0: Normal operation
1: Power down (default)
RXSEL[3:0]: DIR Input Biphase Signal Source Select
0000: RXIN0
0001: RXIN1
0010: RXIN2 (default)
0011: RXIN3
0100: RXIN4
0101: RXIN5
0110: RXIN6
0111: RXIN7
1000: RXIN8
1001: RXIN9
1010: RXIN10
1011: RXIN11
1100: Reserved
1101: Reserved
1110: Reserved
1111: TXOUT (internal DIT output)
NOTE
RX0DIS or RX1DIS must be set to '0', even when an S/PDIF, TTL, or OPTICAL input is
provided into RXIN0 or RXIN1, without use of the built-in COAX amplifier.
70
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Register 35h, RECOUT0 Output Biphase Source Settings
(Address: 35h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
MPO0MUT
0
B3
RO0SEL3
0
B2
RO0SEL2
0
B1
RO0SEL1
1
B0
RO0SEL0
0
RO0SEL0[3:0]: RECOUT0 Output Biphase Source Select
0000: RXIN0
0001: RXIN1
0010: RXIN2 (default)
0011: RXIN3
0100: RXIN4
0101: RXIN5
0110: RXIN6
0111: RXIN7
1000: RXIN8
1001: RXIN9
1010: RXIN10
1011: RXIN11
1100: Reserved
1101: Reserved
1110: Reserved
1111: TXOUT (internal DIT output)
MPO0MUT: MPO0 Mute Control
0: Output (default)
1: MUTE (Logic low level)
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Register 36h, RECOUT1 Output Biphase Source Settings
(Address: 36h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
MPO1MUT
0
B3
RO1SEL3
0
B2
RO1SEL2
0
B1
RO1SEL1
1
B0
RO1SEL0
0
RO1SEL0[3:0]: RECOUT1 Output Biphase Source Select
0000: RXIN0
0001: RXIN1
0010: RXIN2 (default)
0011: RXIN3
0100: RXIN4
0101: RXIN5
0110: RXIN6
0111: RXIN7
1000: RXIN8
1001: RXIN9
1010: RXIN10
1011: RXIN11
1100: Reserved
1101: Reserved
1110: Reserved
1111: TXOUT (internal DIT output)
MPO1MUT: MPO1 Mute Control
0: Output (default)
1: MUTE (Logic low level)
Register 37h, Port Sampling Frequency Calculator Measurement Target Setting
(Address: 37h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
RSV
0
B3
RSV
0
B2
PFSTGT2
0
B1
PFSTGT1
0
B0
PFSTGT0
0
PFSTGT[2:0]: Port fS Calculator, Target Port Setting
000: DIR (default)
001: XTI
010: AUXIN0
011: AUXIN1
100: AUXIN2
101: Main output port
110: AUX output port
111: DIT
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Register 38h, Port Sampling Frequency Calculator Result Output
(Address: 38h, Read-Only)
DATA
Reg Name
Default Value
Memo
B7
PFSST
N/A
B6
PFSPO2
N/A
B5
PFSPO1
N/A
B4
PFSPO0
N/A
B3
PFSOUT3
N/A
B2
PFSOUT2
N/A
B1
PFSOUT1
N/A
B0
PFSOUT0
N/A
PFSST: Port Sampling Frequency Calculate Status
0: Calculated
1: Calculating
PFSPO[2:0]: Calculated Port Information
000: DIR
001: XTI
010: AUXIN0
011: AUXIN1
100: AUXIN2
101: Main output port
110: AUX output port
111: DIT
PFSOUT[3:0]: Calculated Sampling Frequency
0000: Out of range
0001: 8 kHz
0010: 11.025 kHz
0011: 12 kHz
0100: 16 kHz
0101: 22.05 kHz
0110: 24 kHz
0111: 32 kHz
1000: 44.1 kHz
1001: 48 kHz
1010: 64 kHz
1011: 88.2 kHz
1100: 96 kHz
1101: 128 kHz
1110: 176.4 kHz
1111: 192 kHz
NOTE
PFSST, PFSPO, and PFSOUT always output the status when these registers are read.
The other registers do not have clear functions when these are read. To enable these
registers, DIR must be powered on. For example, (Register 40h/RXDIS = 0) PFSST
indicates Calculating and PFSOUT indicates the previous value when no source comes to
the port that is selected by Register 37h/PFSTGT.
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Register 39h, Incoming Biphase Information and Sampling Frequency
(Address: 39h, Read-Only)
DATA
Reg Name
Default Value
Memo
B7
SFSST
N/A
B6
SCSBIT1
N/A
B5
RSV
N/A
B4
RSV
N/A
B3
SESOUT3
N/A
B2
SESOUT2
N/A
B1
SESOUT1
N/A
B0
SESOUT0
N/A
SFSST: Incoming Biphase Signal, Sampling Frequency Calculate Status
0: SFSOUT[3:0] Output is calculated
1: In the process of calculating or unlocked
SCSBIT1: Detected Channel Status Bit1 Flag
0: CS Bit1 = 0 (Audio data)
1: CS Bit1 = 1 (Non-audio data)
SFSOUT[3:0]: Incoming Biphase Signal, Actual Sampling Frequency
0000: Out of range
0001: 8 kHz
0010: 11.025 kHz
0011: 12 kHz
0100: 16 kHz
0101: 22.05 kHz
0110: 24 kHz
0111: 32 kHz
1000: 44.1 kHz
1001: 48 kHz
1010: 64 kHz
1011: 88.2 kHz
1100: 96 kHz
1101: 128 kHz
1110: 176.4 kHz
1111: 192 kHz
NOTE
When SFSST becomes '1' (that is, in the process of calculating or unlocked), SFSOUT
holds the previous data. SFSST and SFSOUT always output the status when these
registers are read. The other registers do not have clear functions when these are read.
To enable these registers, DIR must be powered on (Register 40h/RXDIS = 0).
74
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Register 3Ah–3Bh, PC Buffer (Burst Preamble PC Output Register)
DATA
Reg Name
Default Value
Memo
B7
PC7
N/A
B6
PC6
N/A
B5
PC5
N/A
Address: 3Ah, Read-Only
B4
B3
PC4
PC3
N/A
N/A
B2
PC2
N/A
B1
PC1
N/A
B0
PC0
N/A
DATA
Reg Name
Default Value
Memo
B7
PC15
N/A
B6
PC14
N/A
Address: 3Bh, Read-Only
B5
B4
B3
PC13
PC12
PC11
N/A
N/A
N/A
B2
PC10
N/A
B1
PC9
N/A
B0
PC8
N/A
PC[4:0]: Burst Preamble PC, data type
PC[6:5]: Burst Preamble PC, reserved
PC7: Burst Preamble PC, Error
PC[12:8]: Burst Preamble PC, data type dependent information
PC[15:13]: Burst Preamble PC, bit stream no.
Read PC/PD after ONPCM1/0 goes high by setting MNPCM1 = 1 or MNPCM0 = 1. Polling PC/PD [15:0] is not
allowed.
SPACER
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Register 3Ch–3Dh, PD Buffer (Burst Preamble PD Output Register)
DATA
Reg Name
Default Value
Memo
B7
PD7
N/A
B6
PD6
N/A
B5
PD5
N/A
Address: 3Ch, Read-Only
B4
B3
PD4
PD3
N/A
N/A
B2
PD2
N/A
B1
PD1
N/A
B0
PD0
N/A
DATA
Reg Name
Default Value
Memo
B7
PD15
N/A
B6
PD14
N/A
Address: 3Dh, Read-Only
B5
B4
B3
PD13
PD12
PD11
N/A
N/A
N/A
B2
PD10
N/A
B1
PD9
N/A
B0
PD8
N/A
PD[15:0]: Burst Preamble PD, Length Code (Number of bits)
PD[15:0] is updated at the time when PC[15:0] is updated. PD[15:0] is never updated when only PC[15:0] is
updated. Register 2Ch/OPCRNW0 or Register 2Dh/OPCRNW1 inform the system that PC[15:0] is updated.
Register 40h, System Reset Control
(Address: 40h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MRST
1
B6
RSV
1
B5
ADDIS
0
B4
RXDIS
0
B3
RSV
0
B2
RSV
0
B1
TXDIS
0
B0
XODIS
0
MRST: Mode Control Register Reset for All Functions
0: Set default value
1: Normal operation (default)
ADDIS: Power-Saving for Digital Power Supply (DVDD)
0: Normal operation (default)
1: Power-saving mode
NOTE : Even in power-saving mode, all functions are active. However, without power-saving mode,
DOUT outputs certain data at the power-supply injection.
RXDIS: Power Down for DIR
0: Normal operation (default)
1: Power down
TXDIS: Power Down for DIT
0: Normal operation (default)
1: Power down
XODIS: Power Down for OSC
0: Normal operation (default)
1: Power down
XODIS is superior to OSCAUTO.
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Register 42h, External ADC Function Control
(Address: 42h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
ADDTRX7
0
B3
RSV
0
B2
EADCLK2
0
B1
EADCLK1
1
B0
EADCLK0
0
ADDTRX7: ADC Output Data Select to Main Port, DOUT Pin
0: DOUT = ADC DOUT (default)
1: DOUT = RXIN7 (ADIN0)
This register can select an external ADC data from RXIN7 (ADIN0) to Main Port DOUT pin when
an external ADC is used.
When ADFSLMT = 1, ADCLK[2:0] = 001 (ADC clock is DIR output clock) and DIR locks at
frequency from 14 kHz to 111 kHz, the ADC is forced into power down.
EADCLK[2:0]: ADC Clock Source (SCK/BCK/LRCK) Select
000: AUTO (DIR or XTI)
001: DIR
010: XTI (default)
011: AUXIN0
100: AUXIN1
100: AUXIN2
110: Reserved
111: Reserved
The external ADC clock source must be normally set to XTI source with fixed frequency (the clocks at the XTI
source select are generated by the SCK/BCK/LRCK dividers). Its frequency is set by the register of XSCK[1:0],
XBCK[1:0], and XLRCK[1:0].).
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Register 5Ah–5Fh, DIR Channel Status Data Buffer
(Address : 5Ah–5Fh, Read-Only)
DATA
Address
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
B7
RXCS7
CS Bit7
RXCS15
CS Bit15
RXCS23
CS Bit23
RXCS31
CS Bit31
RXCS39
CS Bit39
RXCS47
CS Bit47
B6
RXCS6
CS Bit6
RXCS14
CS Bit14
RXCS22
CS Bit22
RXCS30
CS Bit30
RXCS38
CS Bit38
RXCS46
CS Bit46
B5
RXCS5
CS Bit5
RXCS13
CS Bit13
RXCS21
CS Bit21
RXCS29
CS Bit29
RXCS37
CS Bit37
RXCS45
CS Bit45
B4
RXCS4
CS Bit4
RXCS12
CS Bit12
RXCS20
CS Bit20
RXCS28
CS Bit28
RXCS36
CS Bit36
RXCS44
CS Bit44
B3
RXCS3
CS Bit3
RXCS11
CS Bit11
RXCS19
CS Bit19
RXCS27
CS Bit27
RXCS35
CS Bit35
RXCS43
CS Bit43
B2
RXCS2
CS Bit2
RXCS10
CS Bit10
RXCS18
CS Bit18
RXCS26
CS Bit26
RXCS34
CS Bit34
RXCS42
CS Bit42
B1
RXCS1
CS Bit1
RXCS9
CS Bit9
RXCS17
CS Bit17
RXCS25
CS Bit25
RXCS33
CS Bit33
RXCS41
CS Bit41
B0
RXCS0
CS Bit0
RXCS8
CS Bit8
RXCS16
CS Bit16
RXCS24
CS Bit24X
RXCS32
CS Bit32
RXCS40
CS Bit40
RXCS0: Use of channel status block
RXCS1: Linear PCM information
RXCS2: Copyright information
RXCS5 – RXCS3: Additional format information
RXCS7– RXCS6: Channel status mode
RXCS15 – RXCS8: Category code
RXCS19 – RXCS16: Source number
RXCS23 – RXCS20: Channel number
RXCS27 – RXCS24: Sampling frequency
RXCS29 – RXCS28: Clock accuracy
RXCS31 – RXCS30: Not defined
RXCS32: Maximum audio sample word length
RXCS35 – RXCS33: Sample word length
RXCS39 – RXCS36: Original sampling frequency
RXCS47 – RXCS40: Not defined
xx of RXCSxx represents the serial number of the channel status data. L-channel data of the channel status is
stored in this register. Its default value is not specified. Therefore, wait until the ERROR/INT0 port goes low and
192 samples pass to read RXCS. RXCS is cleared when DIR unlocks and an L-ch parity error is detected.
78
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Register 60h, DIT Function Control 1/3
(Address: 60h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
TXSSRC2
1
B5
TXSSRC1
0
B4
TXSSRC0
0
B3
RSV
0
B2
TXPSRC2
1
B1
TXPSRC1
0
B0
TXPSRC0
0
TXSSRC[2:0]: DIT System Clock Source Select
000: DIR/XTI Automatic (DIR lock = DIR, DIR unlock = XTI)
001: DIR
010: XTI
011: AUXIN0
100: AUXIN1 (default)
100: AUXIN2
110: Reserved
111: Reserved
TXPSRC[2:0]: DIT Bit Clock, LR Clock, Data Source Select
000: DIR/XTI Automatic (DIR lock = DIR, DIR unlock = XTI)
001: DIR
010: XTI
011: AUXIN0
100: AUXIN1 (default)
100: AUXIN2
110: Reserved
111: Reserved
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Register 61h, DIT Function Control 2/3
(Address: 61h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
TXSCL2
0
B5
TXSCK1
0
B4
TXSCK0
1
B3
RSV
0
B2
TXDSD
0
B1
TXFMT1
0
B0
TXFMT0
0
TXSCK[2:0]: DIT System Clock Control
000: 128fS
001: 256fS (default)
010: 512fS
011: Reserved
100: Controlled by DIR system clock rate
100: Controlled by DIR system clock rate
110: Controlled by DIR system clock rate
111: Controlled by DIR system clock rate
TXDSD: DIT DSD Input Enable
0: DSD input disable (default)
1: DSD input enable
NOTE
When TXDSD is set to '1', the DIT LR clock is generated by the Bit Clock divided by 64.
The DIT source data are forced to all '0's. Provide the DSD source to MPIO_B0 for the
system clock (256fS), MPIO_B1 for the DSD bit clock (64fS), MPIO_B2 for L-ch data, and
MPIO_B3 for R-ch data.
This function is useful when it is desired to suppress system clock jitter by using the path
that is DIT to DIR. Jitter of the system clock generated by DIR is also reduced if the jitter
is high frequency.
TXFMT[1:0]:DIT Audio I/F Format Setting
00: 24-bit I2S (default)
01: 24-bit left-justified
10: 24-bit right-justified
11: 16-bit right-justified
80
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Register 62h, DIT Function Control 3/3
(Address: 62h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
TXDMUT
0
B4
RSV
0
B3
TXVFLG
0
B2
RSV
0
B1
RSV
0
B0
RSV
0
B1
TXCS1
CS Bit1
TXCS9
CS Bit9
TXCS17
CS Bit17
TXCS25
CS Bit25
TXCS33
CS Bit33
TXCS41
CS Bit41
B0
TXCS0
CS Bit0
TXCS8
CS Bit8
TXCS16
CS Bit16
TXCS24
CS Bit24X
TXCS32
CS Bit32
TXCS40
CS Bit40
TXDMUT: DIT Output Audio Data Mute Control
0: No mute (default)
1: Audio data on biphase signal is Mute (zero data)
TXVFLG: DIT Output Validity Flag Control
0: V = '0', Valid (default)
1: V = '1', Invalid
Register 63h–68h, DIT Channel Status Data Buffer
(Address: 63h–68h, Write and Read)
DATA
Address
63h
64h
65h
66h
67h
68h
B7
TXCS7
CS Bit7
TXCS15
CS Bit15
TXCS23
CS Bit23
TXCS31
CS Bit31
TXCS39
CS Bit39
TXCS47
CS Bit47
B6
TXCS6
CS Bit6
TXCS14
CS Bit14
TXCS22
CS Bit22
TXCS30
CS Bit30
TXCS38
CS Bit38
TXCS46
CS Bit46
B5
TXCS5
CS Bit5
TXCS13
CS Bit13
TXCS21
CS Bit21
TXCS29
CS Bit29
TXCS37
CS Bit37
TXCS45
CS Bit45
B4
TXCS4
CS Bit4
TXCS12
CS Bit12
TXCS20
CS Bit20
TXCS28
CS Bit28
TXCS36
CS Bit36
TXCS44
CS Bit44
B3
TXCS3
CS Bit3
TXCS11
CS Bit11
TXCS19
CS Bit19
TXCS27
CS Bit27
TXCS35
CS Bit35
TXCS43
CS Bit43
B2
TXCS2
CS Bit2
TXCS10
CS Bit10
TXCS18
CS Bit18
TXCS26
CS Bit26
TXCS34
CS Bit34
TXCS42
CS Bit42
TXCS0: Use of channel status block.
TXCS1: Linear PCM information.
TXCS2: Copyright information.
TXCS5 – TXCS3: Additional format information.
TXCS7 – TXCS6: Channel status mode.
TXCS15 – TXCS8: Category code.
TXCS19 – TXCS16: Source number.
TXCS23 – TXCS20: Channel number.
TXCS27 – TXCS24: Sampling frequency.
TXCS29 - TXCS28: Clock accuracy.
TXCS31 – TXCS30: Not defined.
TXCS32: Maximum audio sample word length.
TXCS35 – TXCS33: Sample word length.
TXCS39 – TXCS36: Original sampling frequency.
TXCS47 – TXCS40: Not defined.
The data in this register are used for both channels (L-ch and R-ch). When these register data are used for the
DIT channel status data, a channel status data of bit 48 or later is all '0'. All initial values of this register are all '0'.
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Register 6Ah, Main Output and AUXOUT Port Control
(Address: 6Ah, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
AOMUTAS
0
B6
MOMUTAS
0
B5
RSV
0
B4
RSV
0
B3
AOLRMTEN
0
B2
AODMUT
0
B1
MOLRMTEN
0
B0
MODMUT
0
AOMUTAS: AUX Output Port, Mute Synchronization Select (MPIO_B2 and MPIO_B3)
0: AODMUT works with synchronization with LRCK edge. (default)
1: AODMUT works without synchronization with LRCK edge
MOMUTAS: Main Output Port, Mute Synchronization Select (LRCK and DOUT)
0: MODMUT works with synchronization with LRCK edge. (default)
1: MODMUT works without synchronization with LRCK edge
AOLRMTEN: AODMUT Signal Select (MPIO_B2)
0: Only DOUT (default)
1: Both of LRCK and DOUT
AODMUT: AUX Output Port, Data Mute Control
0: Output (default)
1: Mute (the affected signals are selected by Register 6Ah, AOLRMTEN)
MOLRMTEN : MODMUT signal select
0: Only DOUT (default)
1: Both LRCK and DOUT
MODMUT: Main Output Port, DOUT Mute Control
0: Output (default)
1: Mute (the affected signals are selected by Register 6Ah, MOLRMTEN)
Data mutes are done in synchronization with a LRCK edge.
82
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Register 6Bh, Main Output Port (SCKO/BCK/LRCK/DOUT) Source Setting
(Address: 6Bh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
MOSSRC2
0
B5
MOSSRC1
0
B4
MOSSRC0
0
B3
RSV
0
B2
MOPSRC2
0
B1
MOPSRC1
0
B0
MOPSRC0
0
MOSSRC[2:0]: Main Output Port, SCK Source Control
000: DIR/XTI Automatic (DIR lock:DIR, DIR unlock:XTI) (default)
001: DIR
010: XTI
011: AUXIN0
100: AUXIN1
101: AUXIN2
110: Reserved
111: Reserved
MOPSRC[2:0]: Main Output Port, BCK/LRCK/DATA Source Control
000: DIR/XTI Automatic (DIR lock:DIR, DIR unlock:XTI) (default)
001: DIR
010: XTI
011: AUXIN0
100: AUXIN1
101: AUXIN2
110: Reserved
111: Reserved
This source control register is divided into two parts (MOSSRC and MOPSRC). This architecture allows some
additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI
receiver S/PDIF output is connected with the DIX9211 S/PDIF input, and the HDMI receiver I2S outputs
(BCK/LRCK/DATA) are connected with the DIX9211 PCM input port.
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Register 6Ch, AUX Output Port (AUXSCKO/AUXBCKO/AUXLRCKO/AUXDOUT) Source Setting
(Address: 6Ch, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
AOSSRC2
0
B5
AOSSRC1
0
B4
AOSSRC0
0
B3
RSV
0
B2
AOPSRC2
0
B1
AOPSRC1
0
B0
AOPSRC0
0
AOSSRC[2:0]: AUX Output Port, SCK Source Control
000: DIR/XTI automatic (DIR lock:DIR, DIR unlock:XTI) (default)
001: DIR
010: XTI
011: AUXIN0
100: AUXIN1
101: Reserved
110: Reserved
111: Reserved
AOPSRC[2:0]: AUX Output Port, BCK/LRCK/DATA Source Control
000: DIR/XTI automatic (DIR lock:DIR, DIR unlock:XTI) (default)
001: DIR
010: XTI
011: AUXIN0
100: AUXIN1
101: Reserved
110: Reserved
111: Reserved
This source control register is divided into two parts (MOSSRC and MOPSRC). This design allows some
additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI
receiver S/PDIF output is connected to the DIX9211 S/PDIF input, and the HDMI receiver I2S outputs
(BCK/LRCK/DATA) are connected with the DIX9211 PCM input port.
84
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Register 6Dh, MPIO_B and Main Output Port Hi-Z Control
(Address: 6Dh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPB3HZ
0
B6
MPB2HZ
0
B5
MPB1HZ
0
B4
MPB0HZ
0
B3
SCKOHZ
0
B2
BCKHZ
0
B1
LRCKHZ
0
B0
DOUTHZ
0
MPB3HZ: MPIO_B3, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPBSEL. (default)
1: Hi-Z
MPB2HZ: MPIO_B2, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPBSEL. (default)
1: Hi-Z
MPB1HZ: MPIO_B1, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPBSEL. (default)
1: Hi-Z
MPB0HZ: MPIO_B0, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPBSEL. (default)
1: Hi-Z
SCKOHZ: Main Output Port, SCKO Hi-Z Control
0: Output (default)
1: Hi-Z
BCKHZ: Main Output Port, BCKO Hi-Z Control
0: Output (default)
1: Hi-Z
LRCKHZ: Main Output Port, LRCKO Hi-Z Control
0: Output (default)
1: Hi-Z
DOUTHZ: Main Output Port, DOUT Hi-Z Control
0: Output (default)
1: Hi-Z
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Register 6Eh, MPIO_C and MPIO_A Hi-Z Control
(Address: 6Eh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPC3HZ
0
B6
MPC2HZ
0
B5
MPC1HZ
0
B4
MPC0HZ
0
B3
MPA3HZ
1
B2
MPA2HZ
1
B1
MPA1HZ
1
B0
MPA0HZ
1
MPC3HZ: MPIO_C3, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPCSEL. (default)
1: Hi-Z
MPC2HZ: MPIO_C2, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPCSEL. (default)
1: Hi-Z
MPC1HZ: MPIO_C1, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPCSEL. (default)
1: Hi-Z
MPC0HZ: MPIO_C0, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPCSEL. (default)
1: Hi-Z
MPA3HZ:M PIO_A3, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPASEL.
1: Hi-Z (default)
MPA2HZ:M PIO_A2, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPASEL.
1: Hi-Z (default)
MPA1HZ:M PIO_A1, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPASEL.
1: Hi-Z (default)
MPA0HZ:M PIO_A0, Hi-Z Control
0: Defined by Group Function Assign register, 6Fh/MPASEL.
1: Hi-Z (default)
NOTE
In multi-channel PCM mode, the MCHR and MPAxHz registers (20h) must be set to '0' to
get the outputs from the main port.
86
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Register 6Fh, MPIO_A, MPIO_B, MPIO_C Group Function Assign
(Address: 6Fh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPASEL1
0
B6
MPASEL0
1
B5
MPBSEL2
0
B4
MPBSEL1
0
B3
MPBSEL0
0
B2
MPCSEL2
0
B1
MPCSEL1
0
B0
MPCSEL0
0
MPASEL[1:0]: MPIO_A Group Function Assign Setting
00: Biphase Input Extension (RXIN8 to RXIN11)
01: CLKST Output, VOUT Output, XMCKO Output, INT0 Output (default)
10: Secondary BCK/LRCK Output, XMCKO Output, INT0 Output
11: DIR Flags Output or GPIO (Selected by MPA3SEL, MPA2SEL, MPA1SEL, MPA0SEL)
MPBSEL[2:0]: MPIO_B Group Function Assign Setting
000: AUXIN2 (default)
001: AUXOUT
010: Sampling Frequency Calculated Result: FSOUT[3:0]
011: DIR Flags Output or GPIO (Selected by MPB3SEL, MPB2SEL, MPB1SEL, MPB0SEL)
100: DIR BCUV OUT, BFRAME/VOUT/UOUT/COUT
101: External Slave ADC Input (Clocks: Out, Data: In, EASCKO/EABCKO/EALRCKO/EADIN)
110: Reserved
111: Test Mode
MPCSEL[2:0]: MPIO_C Group Function Assign Setting
000: AUXIN1 (default)
001: Reserved
010: Sampling Frequency Calculated Result: FSOUT[3:0]
011: DIR Flags Output or GPIO (Selected by MPC3SEL, MPC2SEL, MPC1SEL, MPC0SEL)
100: DIR BCUV OUT, BFRAME/VOUT/UOUT/COUT
101: DIT Standalone Operation, Clock, and Data I/O, TXSCK/TXBCK/TXLRCK/TXDIN
110: Reserved
111: Reserved
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Register 70h, MPIO_A Flags or GPIO Assign Setting
(Address: 70h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
MCHRSRC1
0
B4
MCHRSRC0
0
B3
MPA3SEL
0
B2
MPA2SEL
0
B1
MPA1SEL
0
B0
MPA0SEL
0
MCHRSRC: AUX Output Port, SCK Source Control
00: See Table 28, Multi-Channel PCM Routing (default)
01: See Table 28, Multi-Channel PCM Routing
10: See Table 28, Multi-Channel PCM Routing
11: See Table 28, Multi-Channel PCM Routing
MPA3SEL: MPIO_A3 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA3FLG[3:0] (default)
1: GPIO, set by GIOA3DIR/GPOA3/GPIA3
MPA2SEL: MPIO_A2 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA2FLG[3:0] (default)
1: GPIO, set by GIOA2DIR/GPOA2/GPIA2
MPA1SEL: MPIO_A1 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA1FLG[3:0] (default)
1: GPIO, set by GIOA1DIR/GPOA1/GPIA1
MPA0SEL: MPIO_A0 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA0FLG[3:0] (default)
1: GPIO, set by GIOA0DIR/GPOA0/GPIA0
88
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Register 71h, MPIO_B, MPIO_C Flags or GPIO Assign Setting
(Address: 71h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPB3SEL
0
B6
MPB2SEL
0
B5
MPB1SEL
0
B4
MPB0SEL
0
B3
MPC3SEL
0
B2
MPC2SEL
0
B1
MPC1SEL
0
B0
MPC0SEL
0
MPB3SEL: MPIO_B3 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPB3FLG[3:0] (default)
1: GPIO, set by GIOB3DIR/GPOB3/GPIB3
MPB2SEL: MPIO_B2 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPB2FLG[3:0] (default)
1: GPIO, set by GIOB2DIR/GPOB2/GPIB2
MPB1SEL: MPIO_B1 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPB1FLG[3:0] (default)
1: GPIO, set by GIOB1DIR/GPOB1/GPIB1
MPB0SEL: MPIO_B0 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPB0FLG[3:0] (default)
1: GPIO, set by GIOB0DIR/GPOB0/GPIB0
MPC3SEL: MPIO_C3 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPC3FLG[3:0] (default)
1: GPIO, set by GIOC3DIR/GPOC3/GPIC3
MPC2SEL: MPIO_C2 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPC2FLG[3:0] (default)
1: GPIO, set by GIOC2DIR/GPOC2/GPIC2
MPC1SEL: MPIO_C1 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPC1FLG[3:0] (default)
1: GPIO, set by GIOC1DIR/GPOC1/GPIC1
MPC0SEL: MPIO_C0 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPC0FLG[3:0] (default)
1: GPIO, set by GIOC0DIR/GPOC0/GPIC0
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Register 72h, MPIO_A1, MPIO_A0 Output Flag Select
(Address: 72h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPA1FLG3
0
B6
MPA1FLG2
0
B5
MPA1FLG1
0
B4
MPA1FLG0
0
B3
MPA0FLG3
0
B2
MPA0FLG2
0
B1
MPA0FLG1
0
B0
MPA0FLG0
0
MPA1FLG[3:0]: MPIO_A1 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPA0FLG[3:0]: MPIO_A0 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPASEL[1:0] = '11', MPA3SEL = '0', and MPA2SEL = '0'.
90
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Register 73h, MPIO_A3, MPIO_A0 Output Flag Select
(Address: 73h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPA3FLG3
0
B6
MPA3FLG2
0
B5
MPA3FLG1
0
B4
MPA3FLG0
0
B3
MPA2FLG3
0
B2
MPA2FLG2
0
B1
MPA2FLG1
0
B0
MPA2FLG0
0
MPA3FLG[3:0]: MPIO_A3 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPA2FLG[3:0]: MPIO_A2 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPASEL[1:0] = '11', MPA3SEL = '0', and MPA2SEL = '0'.
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Register 74h, MPIO_B1, MPIO_B0 Output Flag Select
(Address: 74h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPB1FLG3
0
B6
MPB1FLG2
0
B5
MPB1FLG1
0
B4
MPB1FLG0
0
B3
MPB0FLG3
0
B2
MPB0FLG2
0
B1
MPB0FLG1
0
B0
MPB0FLG0
0
MPB1FLG[3:0]: MPIO_B1 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPB0FLG[3:0]: MPIO_B0 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPBSEL[2:0] = '011', MPB1SEL = '0', and MPB0SEL = '0'.
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Register 75h, MPIO_B3, MPIO_B2 Output Flag Select
(Address: 75h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPB3FLG3
0
B6
MPB3FLG2
0
B5
MPB3FLG1
0
B4
MPB3FLG0
0
B3
MPB2FLG3
0
B2
MPB2FLG2
0
B1
MPB2FLG1
0
B0
MPB2FLG0
0
MPB3FLG[3:0]: MPIO_B3 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPB2FLG[3:0]: MPIO_B2 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPBSEL[2:0] = '011', MPB3SEL = '0', and MPB2SEL = '0'.
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Register 76h, MPIO_C1, MPIO_C0 Output Flag Select
(Address: 76h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPC1FLG3
0
B6
MPC1FLG2
0
B5
MPC1FLG1
0
B4
MPC1FLG0
0
B3
MPC0FLG3
0
B2
MPC0FLG2
0
B1
MPC0FLG1
0
B0
MPC0FLG0
0
MPC1FLG[3:0]: MPIO_C1 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPC0FLG[3:0]: MPIO_C0 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPCSEL[2:0] = '011', MPC1SEL = '0', and MPC0SEL = '0'.
94
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Register 77h, MPIO_C3, MPIO_C2 Output Flag Select
(Address: 77h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPC3FLG3
0
B6
MPC3FLG2
0
B5
MPC3FLG1
0
B4
MPC3FLG0
0
B3
MPC2FLG3
0
B2
MPC2FLG2
0
B1
MPC2FLG1
0
B0
MPC2FLG0
0
MPC3FLG[3:0]: MPIO_C3 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPC2FLG[3:0]: MPIO_C2 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPCSEL[2:0] = '011', MPC3SEL = '0', and MPC2SEL = '0'.
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Register 78h, MPO1, MPO0 Function Assign Setting
(Address: 78h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
MPO1SEL3
0
B6
MPO1SEL2
0
B5
MPO1SEL1
1
B4
MPO1SEL0
1
B3
MPO0SEL3
1
B2
MPO0SEL2
1
B1
MPO0SEL1
0
B0
MPO0SEL0
1
MPO1SEL[3:0]: MPO1 Pin, Output Control
0000: Hi-Z
0001: GPO, Output data = High level
0010: GPO, Output data = Low level
0011: VOUT (default)
0100: INT0
0101: INT1
0110: CLKST
0111: EMPH
1000: BPSYNC
1001: DTSCD
1010: PARITY
1011: LOCK
1100: XMCKO
1101: TXOUT
1110: RECOUT0
1111: RECOUT1
MPO0SEL[3:0]: MPO0 Pin, Output Control
0000: Hi-Z
0001: GPO, Output data = High level
0010: GPO, Output data = Low level
0011: VOUT
0100: INT0
0101: INT1
0110: CLKST
0111: EMPH
1000: BPSYNC
1001: DTSCD
1010: PARITY
1011: LOCK
1100: XMCKO
1101: TXOUT (default)
1110: RECOUT0
1111: RECOUT1
96
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Register 79h, GPIO I/O Direction Control for MPIO_A, MPIO_B
(Address: 79h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
GIOB3DIR
0
B6
GIOB2DIR
0
B5
GIOB1DIR
0
B4
GIOB0DIR
0
B3
GIOA3DIR
0
B2
GIOA2DIR
0
B1
GIOA1DIR
0
B0
GIOA0DIR
0
GIOB3DIR: MPIO_B3 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB2DIR: MPIO_B2 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB1DIR: MPIO_B1 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOB0DIR: MPIO_B0 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA3DIR: MPIO_A3 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA2DIR: MPIO_A2 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA`DIR: MPIO_A1 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOA0DIR: MPIO_A0 Pin Function, GPIO I/O Direction Control
0: Input (default)
1: Output
These registers are effective only at MPIO_A and MPIO_B assigned as GPIO. I/O direction setting is available by
pin.
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Register 7Ah, GPIO I/O Direction Control for MPIO_C
(Address: 7Ah, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
RSV
0
B3
GIOC3DIR
0
B2
GIOC2DIR
0
B1
GIOC1DIR
0
B0
GIOC0DIR
0
GIOC3DIR: MPIO_C3 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOC2DIR: MPIO_C2 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOC1DIR: MPIO_C1 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
GIOC0DIR: MPIO_C0 Pin, GPIO I/O Direction Control
0: Input (default)
1: Output
These registers are effective only at MPIO_C assigned as GPIO. I/O direction setting is available by pin.
98
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Register 7Bh, GPIO Output Data Setting for MPIO_A, MPIO_B
(Address: 7Bh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
GPOB3
0
B6
GPOB2
0
B5
GPOB1
0
B4
GPOB0
0
B3
GPOA3
0
B2
GPOA2
0
B1
GPOA1
0
B0
GPOA0
0
GPOB3: MPIO_B3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB2: MPIO_B2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB1: MPIO_B1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOB0: MPIO_B0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA3: MPIO_A3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA2: MPIO_A2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA1: MPIO_A1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOA0: MPIO_A0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
These registers are effective only as GPIOs are assigned to output.
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Register 7Ch, GPIO Output Data Setting for MPIO_C
(Address: 7Ch, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
RSV
0
B3
GPOC3
0
B2
GPOC2
0
B1
GPOC1
0
B0
GPOC0
0
GPOC3: MPIO_C3 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOC2: MPIO_C2 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOC1: MPIO_C1 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
GPOC0: MPIO_C0 Pin, GPIO Output Data Setting
0: Output low level (default)
1: Output high level
These registers are effective only as GPIOs are assigned to output.
100
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Register 7Dh, GPIO Input Data Register for MPIO_A, MPIO_B
(Address: 7Dh, Read-Only)
DATA
Reg Name
Default Value
Memo
B7
GPIB3
N/A
B6
GPIB2
N/A
B5
GPIB1
N/A
B4
GPIB0
N/A
B3
GPIA3
N/A
B2
GPIA2
N/A
B1
GPIA1
N/A
B0
GPIA0
N/A
GPIB3: MPIO_B3 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIB2: MPIO_B2 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIB1: MPIO_B1 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIB0: MPIO_B0 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIA3: MPIO_A3 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIA2: MPIO_A2 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIA1: MPIO_A1 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIA0: MPIO_A0 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
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Register 7Eh, GPIO Input Data Register for MPIO_C
(Address: 7Eh, Read-Only)
DATA
Reg Name
Default Value
Memo
B7
RSV
N/A
B6
RSV
N/A
B5
RSV
N/A
B4
RSV
N/A
B3
GPIC3
N/A
B2
GPIC2
N/A
B1
GPIC1
N/A
B0
GPIC0
N/A
GPIC3: MPIO_C3 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIC2: MPIO_C2 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIC1: MPIO_C1 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
GPIC0: MPIO_C0 Pin, GPIO Input Data
0: Detect low level
1: Detect high level
102
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
DIX9211PT
ACTIVE
LQFP
PT
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
DIX9211PTR
ACTIVE
LQFP
PT
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DIX9211PTR
Package Package Pins
Type Drawing
LQFP
PT
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
1.9
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DIX9211PTR
LQFP
PT
48
1000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This may also be a thermally enhanced plastic package with leads conected to the die pads.
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