TAS5711 www.ti.com SLOS600 – DECEMBER 2009 20-W DIGITAL AUDIO-POWER AMPLIFIER WITH EQ, DRC, AND 2.1 MODE Check for Samples: TAS5711 FEATURES 1 • 2 • • Audio Input/Output – 20-W Into an 8-Ω Load From an 18-V Supply – Wide PVDD Range, From 8 V to 26 V – Efficient Class-D Operation Eliminates Need for Heatsinks – One Serial Audio Input (Two Audio Channels) – 2.1 Mode (2 SE + 1 BTL) – 2.0 Mode (2 BTL) – Single-Filter PBTL Mode Support – I2C Address Selection Pin (Chip Select) – Supports 8-kHz to 48-kHz Sample Rate (LJ/RJ/I2S) Audio/PWM Processing – Independent Channel Volume Controls With 24-dB to Mute – Separate Dynamic Range Control for Satellite and Subchannels – 21 Programmable Biquads for Speaker EQ and Other Audio Processing Features – Programmable Coefficients for DRC Filters – DC Blocking Filters – Support for 3D Effects General Features – Serial Control Interface Operational Without MCLK – Factory-Trimmed Internal Oscillator for Automatic Rate Detection – Surface Mount, 48-Pin, 7-mm × 7-mm HTQFP Package – Thermal and Short-Circuit Protection – Support for AD or BD Mode • • Benefits – Up to 90% Efficient – AD and BD Filter Mode Support – SNR: 106 dB, A-Weighted – EQ: Speaker Equalization Improves Audio Performance – DRC: Dynamic Range Compression. Can Be Used As Power Limiter. Enables Speaker Protection, Easy Listening, Night-Mode Listening. – Separate DRC for Satellite and Subchannels – Autobank Switching: Preload Coefficients for Different Sample Rates. No Need to Write new Coefficients to the Part When Sample Rate Changes. – Autodetect: Automatically Detects Sample-Rate Changes. No Need for External Microprocessor Intervention Requires Only 3.3 V and PVDD APPLICATIONS • • • Television iPod™ Dock Sound Bar DESCRIPTION The TAS5711 is a 20-W, efficient, digital audio power amplifier for driving stereo bridge-tied speakers. One serial data input allows processing of up to two discrete audio channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a wide range of input data and data rates. A fully programmable data path routes these channels to the internal speaker drivers. The TAS5711 is an I2S slave-only device receiving all clocks from external sources. The TAS5711 operates with a PWM carrier between 384-kHz switching rate and 352-KHz switching rate depending on the input sample rate. Oversampling combined with a fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. iPod is a trademark of Apple Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated TAS5711 SLOS600 – DECEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SIMPLIFIED APPLICATION DIAGRAM 3.3 V 8 V–26 V AVDD/DVDD PVDD LRCLK Digital Audio Source OUT_A LCSE PVDD SCLK MCLK BST_A SDIN BST_B 2 I C Control OUT_B SDA PVDD SCL A_SEL(FAULT) RESET Control Inputs LCSE OUT_C BST_C PDN LCBTL BST_D PLL_FLTP Loop Filter OUT_D (1) PLL_FLTM B0264-09 (1) See TAS5711 EVM User's Guide (SLOU280) for loop filter values. 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 FUNCTIONAL VIEW OUT_A th SDIN Serial Audio Port S R C Digital Audio Processor (DAP) 4 Order Noise Shaper and PWM 2´ HB FET Out OUT_B OUT_C 2´ HB FET Out OUT_D Protection Logic MCLK SCLK LRCLK SDA SCL Click and Pop Control Sample Rate Autodetect and PLL Serial Control Microcontroller Based System Control Terminal Control B0262-06 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 3 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com FAULT Undervoltage Protection FAULT 4 4 Power On Reset Protection and I/O Logic AGND Temp. Sense GND VALID Overcurrent Protection Isense OC_ADJ BST_D PVDD_D PWM Controller PWM_D PWM Rcv Ctrl Timing Gate Drive OUT_D Pulldown Resistor PGND_CD GVDD_CD Regulator GVDD_CD BST_C PVDD_C PWM_C PWM Rcv Ctrl Timing Gate Drive OUT_C Pulldown Resistor PGND_CD BST_B PVDD_B PWM_B PWM Rcv Ctrl Timing Gate Drive OUT_B Pulldown Resistor GVDD_AB Regulator PGND_AB GVDD_AB BST_A PVDD_A PWM_A PWM Rcv Ctrl Timing Gate Drive OUT_A Pulldown Resistor PGND_AB B0034-05 Figure 1. Power Stage Functional Block Diagram 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 R L Input Muxing Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 ½ 61 + 31 1BQ 21 (D8, D9) I2C:54 – V2IM + 2A 1BQ 5A 1BQ 1 1 + + 6BQ 5B 1BQ 32–36, 5C 6BQ 2B–2F, 58 55 + Vol1 + Auto-lp (0x46 Bit 5) 0 –1 + 5E 1BQ 1BQ 5D 1BQ 59 3D ealpha 3D ealpha Vol2 Vol2 ealpha 3A 3A ealpha Vol1 Attack Decay Attack Decay Master ON/OFF (0x46[1]) Log Math Master ON/OFF (0x46[0]) Log Math 1 1 + + 60 V6OM + 52 V2OM 1 1 51 V1OM I2C:56 VDISTA B0321-08 www.ti.com R 1 + 2 I C Subaddress in Red Energy MAXMUX ½ L 30 1BQ 29 1BQ 1 I2C:53 – V1IM TAS5711 SLOS600 – DECEMBER 2009 DAP Process Structure I2C:57 VDISTB Energy MAXMUX Submit Documentation Feedback 5 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com DEVICE INFORMATION PIN ASSIGNMENT PGND_CD PGND_CD PVDD_C OUT_C PVDD_C BST_C PVDD_B BST_B PVDD_B OUT_B PGND_AB PGND_AB PHP Package (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 OUT_A 1 36 OUT_D PVDD_A 2 35 PVDD_D PVDD_A 3 34 PVDD_D BST_A 4 33 BST_D GVDD_OUT 5 32 GVDD_OUT SSTIMER 6 31 VREG OC_ADJ 7 30 AGND PBTL 8 29 GND AVSS DVSS TAS5711 9 28 PLL_FLTM 10 27 DVDD PLL_FLTP 11 26 STEST VR_ANA 12 25 RESET SCL SDA SDIN SCLK LRCLK PDN VR_DIG DVSSO MCLK OSC_RES AVDD A_SEL 13 14 15 16 17 18 19 20 21 22 23 24 P0075-08 PIN FUNCTIONS PIN NAME NO. TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION AGND 30 P A_SEL 14 DIO AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.3-V supply ground BST_A 4 P High-side bootstrap supply for half-bridge A BST_B 43 P High-side bootstrap supply for half-bridge B BST_C 42 P High-side bootstrap supply for half-bridge C BST_D 33 P High-side bootstrap supply for half-bridge D DVDD 27 P 3.3-V digital power supply DVSSO 17 P Oscillator ground (1) (2) 6 Analog ground for power stage A value of 0 (15-kΩ pulldown) makes the I2C device address 0x34, and a value of 1 (15-kΩ pullup) makes it 0x36. This pin can be programmed after RESET to be an output by writing 1 to bit 0 of I2C register 0x05. In that mode, the A_SEL pin is redefined as FAULT (see ERROR REPORTING for details). TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 PIN FUNCTIONS (continued) PIN NAME NO. TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION DVSS 28 P Digital ground GND 29 P Analog ground for power stage 5, 32 P Gate drive internal regulator output. This pin must not be used to drive external devices. LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock) MCLK 15 DI 5-V Pulldown Master clock input OC_ADJ 7 AO Analog overcurrent programming. Requires resistor to ground. OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO. OUT_A 1 O Output, half-bridge A OUT_B 46 O Output, half-bridge B OUT_C 39 O Output, half-bridge C OUT_D 36 O Output, half-bridge D PBTL 8 DI Low means BTL or SE mode; high means PBTL mode. Information goes directly to power stage. PDN 19 DI PGND_AB 47, 48 P Power ground for half-bridges A and B PGND_CD 37, 38 P Power ground for half-bridges C and D PLL_FLTM 10 AO PLL negative loop filter terminal PLL_FLTP 11 AO PLL positive loop filter terminal PVDD_A 2, 3 P Power supply input for half-bridge output A PVDD_B 44, 45 P Power supply input for half-bridge output B PVDD_C 40, 41 P Power supply input for half-bridge output C PVDD_D 34, 35 P RESET 25 DI 5-V SCL 24 DI 5-V SCLK 21 DI 5-V SDA 23 DIO 5-V SDIN 22 DI 5-V SSTIMER 6 AI Controls ramp time of OUT_x to minimize pop. Leave this pin floating for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The capacitor determines the ramp time. STEST 26 DI Factory test pin. Connect directly to DVSS. VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be used to power external devices. VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be used to power external devices. VREG 31 P Digital regulator output. Not to be used for powering external circuitry. GVDD_OUT 5-V Pullup Power down, active-low. PDN prepares the device for loss of power supplies by shutting down the Noise Shaper and initiating PWM stop sequence. Power supply input for half-bridge output D Pullup Reset, active-low. A system reset is generated by applying a logic low to this pin. RESET is an asynchronous control signal that restores the DAP to its default conditions, and places the PWM in the hard mute state (tristated). I2C serial control clock input Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port input data bit clock. I2C serial control data interface input/output Pulldown Serial audio data input. SDIN supports three discrete (stereo) data formats. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 7 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage (1) VALUE UNIT DVDD, AVDD –0.3 to 3.6 V PVDD_x –0.3 to 30 V OC_ADJ –0.3 to 4.2 V 3.3-V digital input Input voltage –0.5 to DVDD + 0.5 V 5-V tolerant (2) digital input (except MCLK) –0.5 to DVDD + 2.5 (3) V 5-V tolerant MCLK input –0.5 to AVDD + 2.5 (3) V (4) OUT_x to PGND_x 32 BST_x to PGND_x 43 (4) V Input clamp current, IIK ±20 mA Output clamp current, IOK V ±20 mA Operating free-air temperature 0 to 85 °C Operating junction temperature range 0 to 150 °C –40 to 125 °C Storage temperature range, Tstg (1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL. Maximum pin voltage should not exceed 6.0V DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions. (2) (3) (4) DISSIPATION RATINGS (1) PACKAGE DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 45°C POWER RATING TA = 70°C POWER RATING 7-mm × 7-mm HTQFP 40 mW/°C 5W 4.2 W 3.2 W (1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad RECOMMENDED OPERATING CONDITIONS MIN NOM MAX Digital/analog supply voltage DVDD, AVDD 3 3.3 3.6 V 26 V Half-bridge supply voltage PVDD_x 8 VIH High-level input voltage 5-V tolerant 2 VIL Low-level input voltage 5-V tolerant TA TJ (1) V 0.8 V Operating ambient temperature range 0 85 °C Operating junction temperature range 0 125 °C RL (BTL) Load impedance Output filter: L = 15 μH, C = 680 nF. LO (BTL) Output-filter inductance Minimum output inductance under short-circuit condition (1) UNIT 6 Ω 8 10 μH Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS PARAMETER Output sample rate 8 VALUE UNIT 11.025/22.05/44.1-kHz data rate ±2% TEST CONDITIONS 352.8 kHz 48/24/12/8/16/32-kHz data rate ±2% 384 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK Frequency 2.8224 MCLK duty cycle 40% TYP 50% MAX UNIT 24.576 MHz 60% Rise/fall time for MCLK 5 ns LRCLK allowable drift before LRCLK reset 4 MCLKs External PLL filter capacitor C1 SMD 0603 X7R 47 nF External PLL filter capacitor C2 SMD 0603 X7R 4.7 nF External PLL filter resistor R SMD 0603, metal film 470 Ω ELECTRICAL CHARACTERISTICS DC Characteristics TA = 25°, PVCC_x = 18V, DVDD = AVDD = 3.3V, RL= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted) TEST CONDITIONS MIN VOH High-level output voltage PARAMETER A_SEL and SDA IOH = –4 mA DVDD = AVDD = 3 V 2.4 VOL Low-level output voltage A_SEL and SDA IOL = 4 mA DVDD = AVDD = 3 V 0.5 IIL Low-level input current VI < VIL ; DVDD = AVDD = 3.6V 75 IIH High-level input current VI > VIH ; DVDD = AVDD = 3.6V IDD 3.3 V supply current 3.3 V supply voltage (DVDD, AVDD) IPVDD Half-bridge supply current No load (PVDD_x) rDS(on) (2) TYP MAX UNIT V 75 (1) Normal Mode 48 70 Reset (RESET = low, PDN = high) 24 32 Normal Mode 30 55 5 13 Reset (RESET = low, PDN = high) Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance 180 Drain-to-source resistance, HS TJ = 25°C, includes metallization resistance 180 V μA μA mA mA mΩ I/O Protection Vuvp Undervoltage protection limit PVDD falling 7.2 V Vuvp,hyst Undervoltage protection limit PVDD rising 7.6 V 150 °C 30 °C 0.63 ms OTE (3) OTEHYST Overtemperature error (3) Extra temperature drop required to recover from error OLPC Overload protection counter fPWM = 384 kHz IOC Overcurrent limit protection Resistor—programmable, max. current, ROCP = 22 kΩ IOCT Overcurrent response time ROCP OC programming resistor range Resistor tolerance = 5% for typical value; the minimum resistance should not be less than 20 kΩ. RPD Internal pulldown resistor at the output of each half-bridge Connected when drivers are tristated to provide bootstrap capacitor charge. (1) (2) (3) 20 4.5 A 150 ns 22 kΩ 3 kΩ IIH for the PBTL pin has a maximum limit of 200 µA due to an intenal pulldown on the pin. This does not include bond-wire or pin resistance. Specified by design Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 9 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com AC Characteristics (BTL) PVDD_x = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN PVDD = 18 V, 10% THD, 1-kHz input signal PO Power output per channel THD+N Vn Total harmonic distortion + noise Output integrated noise (rms) Crosstalk SNR (1) 10 Signal-to-noise ratio (1) TYP MAX UNIT 21 PVDD = 18 V, 7% THD, 1-kHz input signal 20 PVDD = 12 V, 10% THD, 1-kHz input signal 9.5 PVDD = 12 V, 7% THD, 1-kHz input signal 9 PVDD = 8 V, 10% THD, 1-kHz input signal 4.1 PVDD = 8 V, 7% THD, 1-kHz input signal 3.9 PBTL mode, PVDD = 12 V, RL = 4 Ω, 10% THD, 1-kHz input signal 19.2 PBTL mode, PVDD = 12 V, RL = 4 Ω, 7% THD, 1-kHz input signal 18 PBTL mode, PVDD = 18 V, RL = 4 Ω, 10% THD, 1-kHz input signal 42.8 PBTL mode, PVDD = 18 V, RL = 4 Ω, 7% THD, 1-kHz input signal 40 SE mode, PVDD = 12 V, RL = 4 Ω, 10% THD, 1-kHz input signal 4.6 SE mode, PVDD = 12 V, RL = 4 Ω, 7% THD, 1-kHz input signal 4.3 SE mode, PVDD = 24 V, RL = 4 Ω, 10% THD, 1-kHz input signal 17.8 SE mode, PVDD = 24 V, RL = 4 Ω, 7% THD, 1-kHz input signal 16 PVDD = 18 V, PO = 1 W 0.06% PVDD = 12 V, PO = 1 W 0.08% PVDD = 8 V, PO = 1 W 0.2% W 44 μV PO = 0.25 W, f = 1 kHz (BD Mode) –82 dB PO = 0.25 W, f = 1 kHz (AD Mode) –69 dB A-weighted, f = 1 kHz, maximum power at THD < 1% 106 dB A-weighted SNR is calculated relative to 0-dBFS input level. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 12.288 MHz fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 ns LRCLK frequency 8 48 48 SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60% SCLK rising edges between LRCLK rising edges t(edge) LRCLK clock edge with respect to the falling edge of SCLK tr/tf Rise/fall time for SCLK/LRCLK kHz 32 64 SCLK edges –1/4 1/4 SCLK period 8 tr ns tf SCLK (Input) t(edge) th1 tsu1 LRCLK (Input) th2 tsu2 SDIN T0026-04 Figure 2. Slave Mode Serial Data Interface Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 11 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.3 μs tr Rise time, SCL and SDA 300 ns tf Fall time, SCL and SDA 300 ns tsu1 Setup time, SDA to SCL th1 Hold time, SCL to SDA 0 ns t(buf) Bus free time between stop and start condition 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 CL Load capacitance for each bus line 100 ns μs 400 tw(H) tw(L) pF tf tr SCL tsu1 th1 SDA T0027-01 Figure 3. SCL and SDA Timing SCL t(buf) th2 tsu2 tsu3 SDA Start Condition Stop Condition T0028-01 Figure 4. Start and Stop Conditions Timing 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) Pulse duration, RESET active td(I2C_ready) Time to enable I2C MIN TYP MAX UNIT 12.0 ms 100 µs RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C. T0421-01 NOTES: On power up, it is recommended that the TAS5711 RESET be held LOW for at least 100 μs after DVDD has reached 3 V. If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH). Figure 5. Reset Timing Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 13 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 8V RL = 8Ω T A = 25°C PO = 2.5W 0.1 0.1 PO = 0.5W PO = 1W 0.01 0.001 20 PO = 5W 1 PO = 2.5W THD+N (%) THD+N (%) 1 PVDD = 12V RL = 8Ω T A = 25°C 0.01 100 1k Frequency (Hz) 10k PO = 1W 0.001 20 20k 100 G001 Figure 6. PVDD = 24V RL = 8Ω T A = 25°C 1 1 PO = 2.5W THD+N (%) PO = 5W THD+N (%) G002 10 PVDD = 18V RL = 8Ω T A = 25°C 0.1 PO = 1W 100 PO = 5W 0.1 0.01 1k Frequency (Hz) 10k 20k PO = 2.5W 0.001 20 G003 Figure 8. 14 20k TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 0.001 20 10k Figure 7. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.01 1k Frequency (Hz) 100 PO = 1W 1k Frequency (Hz) 10k 20k G004 Figure 9. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 8Ω T A = 25°C PVDD = 12V RL = 8Ω T A = 25°C f = 20Hz 1 1 f = 1kHz THD+N (%) THD+N (%) f = 1kHz 0.1 0.01 f = 20Hz 0.1 0.01 f = 10kHz f = 10kHz 0.001 0.01 0.1 1 Output Power (W) 10 0.001 0.01 50 0.1 G005 Figure 10. 1 Output Power (W) 50 G006 Figure 11. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 18V RL = 8Ω T A = 25°C PVDD = 24V RL = 8Ω T A = 25°C 1 1 f = 1kHz THD+N (%) f = 1kHz THD+N (%) 10 0.1 0.1 f = 20Hz f = 20Hz f = 10kHz 0.01 0.01 f = 10kHz 0.001 0.01 0.1 1 Output Power (W) 10 50 0.001 0.01 G007 Figure 12. 0.1 1 Output Power (W) 10 50 G008 Figure 13. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 15 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 40 100 RL = 8Ω T A = 25°C 35 90 80 THD+N = 10% PVDD = 24V PVDD = 18V 70 PVDD = 12V 25 Efficiency (%) Output Power (W) 30 20 15 60 PVDD = 8V 50 40 THD+N = 1% 30 10 20 5 RL = 8Ω T A = 25°C 10 0 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 5 10 G009 Figure 14. 40 G010 0 PO = 1W PVDD = 8V RL = 8Ω T A = 25°C -10 -20 PO = 1W PVDD = 12V RL = 8Ω T A = 25°C -30 Crosstalk (dB) -30 Crosstalk (dB) 35 CROSSTALK vs FREQUENCY 0 -20 30 Figure 15. CROSSTALK vs FREQUENCY -10 15 20 25 Total Output Power (W) -40 -50 -60 -70 -40 -50 -60 -70 Right to Left Left to Right -80 -80 -90 -100 20 100 1k Frequency (Hz) 10k 20k -100 20 G011 Figure 16. 16 Right to Left -90 Left to Right 100 1k Frequency (Hz) 10k 20k G012 Figure 17. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 -10 -20 0 PO = 1W PVDD = 18V RL = 8Ω T A = 25°C -10 -20 -30 Crosstalk (dB) Crosstalk (dB) -30 PO = 1W PVDD = 24V RL = 8Ω T A = 25°C -40 -50 -60 -70 -40 -50 -60 Right to Left -70 Right to Left -80 -80 Left to Right -90 -90 Left to Right -100 20 100 1k Frequency (Hz) 10k 20k -100 20 G013 Figure 18. 100 1k Frequency (Hz) 10k 20k G014 Figure 19. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 17 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, SE CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 4Ω T A = 25°C PVDD = 18V RL = 4Ω T A = 25°C 1 PO = 5W 1 PO = 2.5W THD+N (%) THD+N (%) PO = 2.5W 0.1 0.1 PO = 1W PO = 1W PO = 0.5W 0.01 0.001 20 0.01 100 1k Frequency (Hz) 10k 0.001 20 20k 100 1k Frequency (Hz) G015 Figure 20. 10k 20k G016 Figure 21. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 24V RL = 4Ω T A = 25°C f = 1kHz RL = 4Ω T A = 25°C 1 1 PO = 5W PVDD = 18V THD+N (%) THD+N (%) PO = 2.5W 0.1 PVDD = 12V 0.1 PVDD = 24V PO = 1W 0.01 0.001 20 0.01 100 1k Frequency (Hz) 10k 20k 0.001 0.01 G017 Figure 22. 18 0.1 1 Output Power (W) 10 50 G018 Figure 23. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 100 22 RL = 4Ω T A = 25°C 20 90 18 80 16 70 PVDD = 24V Efficiency (%) Output Power (W) THD+N = 10% 14 12 10 60 PVDD = 12V 50 40 8 30 6 THD+N = 1% 4 20 2 10 0 RL = 4Ω T A = 25°C 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 G019 Figure 24. 3 6 9 Total Output Power (W) 12 15 G020 Figure 25. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 19 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 8V RL = 4Ω T A = 25°C PVDD = 12V RL = 4Ω T A = 25°C 1 1 PO = 5W THD+N (%) THD+N (%) PO = 5W 0.1 PO = 1W 0.1 PO = 2W 0.01 0.01 PO = 2W PO = 1W 0.001 20 100 1k Frequency (Hz) 10k 0.001 20 20k 100 G021 Figure 26. PVDD = 24V RL = 4Ω T A = 25°C 1 THD+N (%) 1 THD+N (%) G022 10 PVDD = 18V RL = 4Ω T A = 25°C PO = 5W 0.01 PO = 2W 100 0.01 PO = 1W 1k Frequency (Hz) PO = 2W 0.1 10k 20k 0.001 20 G023 Figure 28. 20 20k TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 0.001 20 10k Figure 27. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 0.1 1k Frequency (Hz) PO = 5W 100 PO = 1W 1k Frequency (Hz) 10k 20k G024 Figure 29. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 4Ω T A = 25°C PVDD = 12V RL = 4Ω T A = 25°C 1 1 THD+N (%) THD+N (%) f = 20Hz 0.1 0.01 f = 20Hz 0.1 f = 10kHz 0.01 f = 1kHz f = 1kHz 0.001 0.01 0.1 1 Output Power (W) f = 10kHz 10 0.001 0.01 50 0.1 G025 Figure 30. 10 50 G026 Figure 31. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 18V RL = 4Ω T A = 25°C PVDD = 24V RL = 4Ω T A = 25°C 1 THD+N (%) 1 THD+N (%) 1 Output Power (W) f = 20Hz 0.1 f = 1kHz f = 20Hz 0.1 f = 1kHz 0.01 0.01 f = 10kHz 0.001 0.01 0.1 1 Output Power (W) f = 10kHz 10 50 0.001 0.01 G027 Figure 32. 0.1 1 Output Power (W) 10 50 G028 Figure 33. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 21 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, PBTL CONFIGURATION (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 100 60 RL = 4Ω T A = 25°C 90 50 80 40 30 60 PVDD = 8V 50 40 THD+N = 1% 20 30 20 10 RL = 4Ω T A = 25°C 10 0 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 G029 NOTE: Dashed lines represent thermally limited regions. 10 20 30 40 Total Output Power (W) 50 60 G030 NOTE: Dashed line represents thermally limited region. Figure 34. 22 PVDD = 24V PVDD = 12V THD+N = 10% Efficiency (%) Output Power (W) PVDD = 18V 70 Figure 35. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5711 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x), and power-stage supply pins (PVDD_x). The gate drive voltages (GVDD_AB and GVDD_CD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_x) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF 50-V X7R capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_x). For optimal electrical performance, EMC compliance, and system reliability, it is important that each PVDD_x pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin. The TAS5711 is fully protected against erroneous power-stage turnon due to parasitic gate charging. ERROR REPORTING The A_SEL pin has two functions: I2C device-address select and fault indication. On RESET, this pin is an input and defines the I2C address. But this pin can be programmed after RESET to be an output by writing 1 to bit 0 of I2C register 0x05. In that mode, the A_SEL pin has the definition shown in Table 1. Any fault resulting in device shutdown is signaled by the A_SEL pin going low (see Table 1). A latched version of this pin is available on D1 of register 0x02. The bit can be cleared only by an I2C write. Table 1. FAULT Output States FAULT DESCRIPTION 0 Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or over voltage ERROR 1 No faults (normal operation) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 23 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com Table 1. FAULT Output States (continued) Power Stage Fault State FAULT NO-FAULT NO-FAULT FAULT Programmable Recovery Time ~300 ns T0450-01 Figure 36. Fault Timing Diagram DEVICE PROTECTION SYSTEM Overcurrent (OC) Protection With Current Limiting The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down. Overtemperature Protection The TAS5711 has over temperature-protection system. If the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5711 recovers automatically once the temperature drops approximately 30°. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5711 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 SSTIMER FUNCTIONALITY The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time determines the rate at which the output transitions from a near zero duty cycle to the desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is shutdown the drivers are tristated and transition slowly down through a 3K resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of SSTIMER pin capacitance. Larger capacitors will increase the start-up time, while capacitors smaller than 2.2 nF will decrease the start-up time. The SSTIMER pin should be left floating for BD modulation (BTL and PBTL modes) and in 2.1 mode. CLOCK, AUTO DETECTION, AND PLL The TAS5711 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the clock control register . The TAS5711 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 × fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 time the PWM switching frequency. The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register. TAS5711 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute) and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process, the default volume will be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E). SERIAL DATA INTERFACE Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5711 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats. PWM Section The TAS5711 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs two BTL PWM audio output channels. The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be enabled and disabled. Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. For detailed description of using audio processing features like DRC, EQ, 3D, and Bass Boost, please refer to User's Guide and TAS570X GDE software development tool documentation. Also refer to GDE software development tool for device data path. SERIAL INTERFACE CONTROL AND TIMING The I2S mode is set by writing to register 0x04. I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 25 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com 2 2-Channel I S (Philips Format) Stereo Input 32 Clks LRCLK (Note Reversed Phase) 32 Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 9 8 5 4 5 4 1 0 1 0 1 0 LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 37. I2S 64-fS Format 2 2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size) LRCLK 24 Clks 24 Clks Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 3 2 1 0 LSB 23 22 17 16 9 8 5 4 19 18 13 12 5 4 1 0 15 14 9 1 0 3 2 1 20-Bit Mode 19 18 16-Bit Mode 15 14 8 8 T0092-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 38. I2S 48-fS Format 26 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 2 2-Channel I S (Philips Format) Stereo Input LRCLK 16 Clks 16 Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode MSB LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 0 LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 T0266-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 39. I2S 32-fS Format Left-Justified Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions. 2-Channel Left-Justified Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 40. Left-Justified 64-fS Format Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 27 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 21 LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 1 0 MSB LSB 21 17 16 9 8 5 4 19 18 17 13 12 5 4 1 0 15 14 13 9 1 0 23 22 1 0 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 8 8 T0092-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 41. Left-Justified 48-fS Format 2-Channel Left-Justified Stereo Input 16 Clks 16 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 16-Bit Mode 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 MSB 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 T0266-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 42. Left-Justified 32-fS Format Right-Justified Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions. 2-Channel Right-Justified (Sony Format) Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode LSB 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 MSB LSB 23 22 19 18 15 14 1 0 19 18 15 14 1 0 15 14 1 0 20-Bit Mode 16-Bit Mode T0034-03 Figure 43. Right Justified 64-fS Format Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 29 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 44. Right Justified 48-fS Format Figure 45. Right Justified 32-fS Format 30 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 I2C SERIAL CONTROL INTERFACE The TAS5711 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status. The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation (400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles. General I2C Operation The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 46. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5711 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus. SDA R/ A W 7-Bit Slave Address 7 6 5 4 3 2 1 0 8-Bit Register Address (N) 7 6 5 4 3 2 1 0 8-Bit Register Data For Address (N) A 7 6 5 4 3 2 1 8-Bit Register Data For Address (N) A 0 7 6 5 4 3 2 1 A 0 SCL Start Stop T0035-01 2 Figure 46. Typical I C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 46. Pin A_SEL defines the I2C device address. An external 15-kΩ pulldown on this pin gives a device address of 0x34 and a 15-kΩ pullup gives a device address of 0x36. The 7-bit address is 0011011 (0x36) or 0011010 (0x34). I2C Device Address Change Procedure • Write to device address change enable register, 0xF8 with a value of 0xF9 A5 A5 A5. • Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address. • Any writes after that should use the new device address XX. Single- and Multiple-Byte Transfers The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses 0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 31 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0. During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded. Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5711 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5711. For I2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded. Single-Byte Write As shown in Figure 47, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5711 internal memory address being accessed. After receiving the address byte, the TAS5711 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5711 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Start Condition Acknowledge A6 A5 A4 A3 A2 A1 A0 Acknowledge R/W ACK A7 A6 A5 2 A4 A3 A2 A1 Acknowledge A0 ACK D7 D6 Subaddress I C Device Address and Read/Write Bit D5 D4 D3 D2 D1 D0 ACK Stop Condition Data Byte T0036-01 Figure 47. Single-Byte Write Transfer Multiple-Byte Write A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 48. After receiving each data byte, the TAS5711 responds with an acknowledge bit. Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 2 I C Device Address and Read/Write Bit A6 A5 A4 A3 Subaddress A1 Acknowledge Acknowledge Acknowledge Acknowledge A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-02 Figure 48. Multiple-Byte Write Transfer 32 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Single-Byte Read As shown in Figure 49, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5711 address and the read/write bit, TAS5711 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5711 address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5711 again responds with an acknowledge bit. Next, the TAS5711 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. Repeat Start Condition Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 Acknowledge A6 2 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 2 I C Device Address and Read/Write Bit Subaddress I C Device Address and Read/Write Bit Not Acknowledge Acknowledge D1 D0 ACK Stop Condition Data Byte T0036-03 Figure 49. Single-Byte Read Transfer Multiple-Byte Read A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5711 to the master device as shown in Figure 50. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Repeat Start Condition Start Condition Acknowledge A6 2 A0 R/W ACK A7 I C Device Address and Read/Write Bit Acknowledge A6 A6 A0 ACK A5 Subaddress 2 Acknowledge Acknowledge Acknowledge Not Acknowledge A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK I C Device Address and Read/Write Bit First Data Byte Other Data Bytes Last Data Byte Stop Condition T0036-04 Figure 50. Multiple Byte Read Transfer Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 33 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com Output Mode and MUX Selection 2.0 BTL AD Reg setting 0x20 (23) = 0 0x20 (19) = 0 0x05 (3) = X 0x05 (2) = 0 2.0 BTL BD Reg setting 0x20 (23) = 1 0x20 (19) = 1 0x05 (3) = X 0x05 (2) = 0 2.1 SE, BTL-AD Reg setting 0x20 (23) = 0 0x20 (19) = 0 0x05 (3) = 0 0x05 (2) = 1 2.1 SE, BTL-BD Reg setting 0x20 (23) = 0 0x20 (19) = 0 0x05 (3) = 1 0x05 (2) = 1 PWM1 CH1_audio A PWM2 B C PWM3 CH2_audio D PWM4 PWM1 CH1_audio A PWM2 B C PWM3 CH2_audio D PWM4 PWM1 CH1_audio A PWM2 B CH2_audio C PWM3 CH3_audio D PWM4 PWM1 CH1_audio A PWM2 B CH2_audio C PWM3 CH3_audio D PWM4 B0378-01 Figure 51. Output Mode and MUX Selection 2.1-Mode Support The TAS5711 uses a special mid-Z ramp sequence to reduce click and pop in SE-mode and 2.1-mode operation.To enable the mid-Z ramp, register 0x05 bit D7 must be set to 1. To enable 2.1 mode, register 0x05 bit D2 must be set to 1. The SSTIMER pin should be left floating in this mode. Single-Filter PBTL-Mode Support The TAS5711 supports parallel BTL (PBTL) mode with OUT_A/OUT_B (and OUT_C/OUT_D) connected before the LC filter. In order to put the part in PBTL configuration, drive PBTL (pin 8) HIGH. This synchronizes the turnoff of half-bridges A and B (and similarly C/D) if an overcurrent condition is detected in either half-bridge. There is a pulldown resistor on the PBTL pin that configures the part in BTL mode if the pin is left floating. PWM output multiplexers should be updated to set the device in PBTL mode. Output Mux Register (0x25) should be written with a value of 0x01 10 32 45. Also, the PWM shutdown register (0x19) should be written with a value of 0x3A. 34 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subchannel. The DRC input/output diagram is shown in Figure 52. Refer to GDE software tool for more description on T, K, and O parameters. Output Level (dB) K 1:1 Transfer Function O Implemented Transfer Function T Input Level (dB) M0091-02 Professional-quality dynamic range compression automatically adjusts volume to flatten volume level. • Each DRC has adjustable threshold, offset, and compression levels • Programmable energy, attack, and decay time constants • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging, and decay times can be set slow enough to avoid pumping. Figure 52. Dynamic Range Control Energy Filter Compression Control Attack and Decay Filters a, w T, K, O aa, wa / ad, wd DRC1 0x3A 0x40, 0x41, 0x42 0x3B / 0x3C DRC2 0x3D 0x43, 0x44, 0x45 0x3E / 0x3F Audio Input DRC Coefficient Alpha Filter Structure S a w –1 Z NOTE: w=1–α B0265-01 T = 9.23 format, all other DRC coefficients are 3.23 format Figure 53. DRC Structure Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 35 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com BANK SWITCHING The TAS5711 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is used in 44.1/48 kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5711 to detect automatically a change in the input sample rate and switch to the appropriate bank without any MCU intervention. An external controller configures bankable locations (0x29-0x36, 0x3A-0x3F, and 0x58-0x5F) for all three banks during the initialization sequence. If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5711 automatically swaps the coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate change. By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5711 automatically swaps banks based on the sample rate. Command sequences for updating DAP coefficients can be summarized as follows: 1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not influenced by subsequent sample rate changes. OR Bank switching enabled: (a) Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients. (b) Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients. (c) Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients. (d) Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50. 26-Bit 3.23 Number Format All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 54 . 2 –23 2 2 –5 –1 Bit Bit Bit 0 2 Bit 1 2 Bit Sign Bit S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx M0125-01 Figure 54. 3.23 Format 36 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 54. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 55 applied to obtain the magnitude of the negative number. 1 0 2 Bit 2 Bit 1 2 –1 Bit 2 0 (1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2 –1 –4 Bit 2 + ....... (1 or 0) ´ 2 –4 –23 Bit + ....... (1 or 0) ´ 2 –23 M0126-01 Figure 55. Conversion Weighting Factors—3.23 Format to Floating Point Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 56 Fraction Digit 6 Sign Bit Fraction Digit 1 Integer Digit 1 Fraction Digit 2 Fraction Digit 3 Fraction Digit 4 Fraction Digit 5 u u u u u u S x x. x x x x x x x x x x x x x x x x x x x x x x x 0 Coefficient Digit 8 Coefficient Digit 7 Coefficient Digit 6 Coefficient Digit 5 Coefficient Digit 4 Coefficient Digit 3 Coefficient Digit 2 Coefficient Digit 1 u = unused or don’t care bits Digit = hexadecimal digit M0127-01 Figure 56. Alignment of 3.23 Coefficient in 32-Bit I2C Word Table 2. Sample Calculation for 3.23 Format dB Linear Decimal Hex (3.23 Format) 0 1 8,388,608 0080 0000 5 1.7782794 14,917,288 00E3 9EA8 –5 0.5623413 4,717,260 0047 FACC X L = 10(X/20) D = 8,388,608 × L H = dec2hex (D, 8) Table 3. Sample Calculation for 9.17 Format dB Linear Decimal 0 1 131,072 2 0000 5 1.77 231,997 3 8A3D –5 0.56 73,400 1 1EB8 D = 131,072 × L H = dec2hex (D, 8) X (X/20) L = 10 Hex (9.17 Format) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 37 38 2 Submit Documentation Feedback Product Folder Link(s): TAS5711 PVDD RESET SCL SDA 0 ns 0 ns 100 ms 100 μs 3V 10 ms 8V 6V 13.5 ms Trim 50 ms DAP Config Other Config (1) tPLL has to be greater than 240 ms + 1.3 tstart. This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets. (2) tstart/tstop = PWM start/stop time as defined in register 0X1A (3) When Mid-Z ramp is enabled (for 2.1 mode), tstart = 300 ms I C PDN AVDD/DVDD Initialization Exit SD (1) tPLL 1 ms + 1.3 tstart (2)(3) Volume and Mute Commands Normal Operation Enter SD (2) 1 ms + 1.3 tstop Shutdown 2 ms 2 ms 2 ms 8V 6V 0 ns Powerdown T0419-05 3V TAS5711 SLOS600 – DECEMBER 2009 www.ti.com Recommended Use Model Figure 57. Recommended Command Sequence Copyright © 2009, Texas Instruments Incorporated TAS5711 www.ti.com SLOS600 – DECEMBER 2009 3V AVDD/DVDD 0 ns 2 ms PDN 0 ns 2 I C 2 ms RESET 2 ms 0 ns 8V PVDD 6V T0420-05 Figure 58. Power Loss Sequence Recommended Command Sequences Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V. 2. Initialize digital inputs and PVDD supply as follows: • Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.5 V above AVDD/DVDD. Wait at least 100 µs, drive RESET = 1, and wait at least another 13.5 ms. • Ramp up PVDD to at least 8 V while ensuring that it remains below 6 V for at least 100 µs after AVDD/DVDD reaches 3 V. Then wait at least another 10 µs. 3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50 ms. 4. Configure the DAP via I2C (see Users's Guide for typical values). 5. Configure remaining registers. 6. Exit shutdown (sequence defined below). Normal Operation The following are the only events supported during normal operation: 1. Writes to master/channel volume registers. 2. Writes to soft mute register. 3. Enter and exit shutdown (sequence defined below). Note: Event 3 is not supported for 240 ms + 1.3 × tstart after trim following AVDD/DVDD powerup ramp (where tstart is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 39 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com Shutdown Sequence Enter: 1. Write 0x40 to register 0x05. 2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A). 3. If desired, reconfigure by returning to step 4 of initialization sequence. 1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD powerup ramp). 2. Wait at least 1 ms + 1.3 × tstart (where tstart is 300 ms when mid-Z ramp is enabled and is otherwise specified by register 0x1A). 3. Proceed with normal operation. Exit: Power-Down Sequence Use the following sequence to powerdown the device and its supplies: 1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert PDN = 0 and wait at least 2 ms. 2. Assert RESET = 0. 3. Drive digital inputs low and ramp down PVDD supply as follows: 4. 40 • Drive all digital inputs low after RESET has been low for at least 2 µs. • Ramp down PVDD while ensuring that it remains above 8 V until RESET has been low for at least 2 µs. Ramp down AVDD/DVDD while ensuring that it remains above 3 V until PVDD is below 6 V and that it is never more than 2.5 V below the digital inputs. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Table 4. Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES INITIALIZATION VALUE CONTENTS A u indicates unused bits. 0x00 Clock control register 1 Description shown in subsequent section 0x6C 0x01 Device ID register 1 Description shown in subsequent section 0x70 0x02 Error status register 1 Description shown in subsequent section 0x00 0x03 System control register 1 1 Description shown in subsequent section 0xA0 0x04 Serial data interface register 1 Description shown in subsequent section 0x05 0x05 System control register 2 1 Description shown in subsequent section 0x40 0x06 Soft mute register 1 Description shown in subsequent section 0x00 0x07 Master volume 1 Description shown in subsequent section 0xFF (mute) 0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x0B - 0x0D 0x0E Volume configuration register 0x0F 1 Reserved 1 Description shown in subsequent section 1 Reserved (1) 0x91 0x10 Modulation limit register 1 Description shown in subsequent section 0x02 0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC 0x12 IC delay channel 2 1 Description shown in subsequent section 0x54 0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC 0x14 IC delay channel 4 1 Description shown in subsequent section 0x54 1 Reserved (1) Description shown in subsequent section 0x15-0x18 0x19 PWM channel shutdown group register 1 0x1A Start/stop period register 1 0x0F 0x1B Oscillator trim register 1 0x82 0x1C BKND_ERR register 1 0x1D–0x1F 0x30 0x02 1 Reserved (1) 0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772 0x21 Ch 4 source select register 4 Description shown in subsequent section 0x0000 4303 4 Reserved (1) 4 Description shown in subsequent section 0x22 -0x24 0x25 PWM MUX register 0x26-0x28 0x29 0x2A (1) (1) ch1_bq[0] ch1_bq[1] 0x0102 1345 (1) 4 Reserved 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 20 Reserved registers should not be accessed. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 41 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 42 REGISTER NAME ch1_bq[2] ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] NO. OF BYTES 20 20 20 20 20 20 20 20 20 CONTENTS INITIALIZATION VALUE u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x34 0x35 0x36 REGISTER NAME ch2_bq[4] ch2_bq[5] ch2_bq[6] 0x37 - 0x39 0x3A DRC1 ae (3) NO. OF BYTES 20 20 20 DRC1 aa DRC1 ad DRC2 ae DRC2 aa DRC2 ad 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 (2) 0x0080 0000 0x0000 0000 u[31:26], aa[25:0] 0x0080 0000 u[31:26], (1 – aa)[25:0] 0x0000 0000 u[31:26], ad[25:0] 0x0080 0000 u[31:26], (1 – ad)[25:0] 0x0000 0000 u[31:26], ae[25:0] 0x0080 0000 u[31:26], (1 – ae)[25:0] 0x0000 0000 u[31:26], aa[25:0] 0x0080 0000 u[31:26], (1 – aa)[25:0] 0x0000 0000 u[31:26], ad[25:0] 0x0080 0000 8 8 8 8 8 DRC2 (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000 0x40 DRC1-T 4 T1[31:0] (9.23 format) 0xFDA2 1490 0x41 DRC1-K 4 u[31:26], K1[25:0] 0x0384 2109 0x42 DRC1-O 4 u[31:26], O1[25:0] 0x0008 4210 0x43 DRC2-T 4 T2[31:0] (9.23 format) 0xFDA2 1490 0x44 DRC2-K 4 u[31:26], K2[25:0] 0x0384 2109 0x45 DRC2-O 4 u[31:26], O2[25:0] 0x0008 4210 0x46 DRC control 4 Description shown in subsequent section 0x0000 0000 0x47–0x4F (2) 4 Reserved 0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000 0x51 Ch 1 output mixer 12 Ch 1 output mix1[2] 0x0080 0000 Ch 1 output mix1[1] 0x0000 0000 0x52 (2) (3) 0x0000 0000 u[31:26], a1[25:0] u[31:26], (1 – ae)[25:0] DRC2 (1 – aa) 0x3F u[31:26], b2[25:0] u[31:26], ae[25:0] DRC 2 (1 – ae) 0x3E 0x0000 0000 Reserved DRC1 (1 – ad) 0x3D 0x0080 0000 u[31:26], b1[25:0] 8 DRC1 (1 – aa) 0x3C u[31:26], b0[25:0] 4 DRC1 (1 – ae) 0x3B INITIALIZATION VALUE CONTENTS Ch 2 output mixer 12 Ch 1 output mix1[0] 0x0000 0000 Ch 2 output mix2[2] 0x0080 0000 Ch 2 output mix2[1] 0x0000 0000 Ch 2 output mix2[0] 0x0000 0000 Reserved registers should not be accessed. "ae" stands for µ of energy filter, "aa" stands for µ of attack filter and "ad" stands for µ of decay filter and 1- µ = ω. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 43 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x53 0x54 0x55 Ch 1 input mixer Ch 2 input mixer Channel 3 input mixer NO. OF BYTES 16 16 CONTENTS INITIALIZATION VALUE Ch 1 input mixer[3] 0x0080 0000 Ch 1 input mixer[2] 0x0000 0000 Ch 1 input mixer[1] 0x0000 0000 Ch 1 input mixer[0] 0x0080 0000 Ch 2 input mixer[3] 0x0080 0000 Ch 2 input mixer[2] 0x0000 0000 Ch 2 input mixer[1] 0x0000 0000 Ch 2 input mixer[0] 0x0080 0000 Channel 3 input mixer [2] 0x0080 0000 Channel 3 input mixer [1] 0x0000 0000 Channel 3 input mixer [0] 0x0000 0000 4 u[31:26], post[25:0] 0x0080 0000 12 0x56 Output post-scale 0x57 Output pre-scale 4 u[31:26], pre[25:0] (9.17 format) 0x0002 0000 0x58 ch1 BQ[7] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x59 0x5A 0x5B 0x5C 0x5D 44 REGISTER NAME ch1 BQ[8] Subchannel BQ[0] Subchannel BQ[1] ch2 BQ[7] ch2 BQ[8] 20 20 20 20 20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x5E REGISTER NAME pseudo_ch2 BQ[0] 0x5F NO. OF BYTES 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 (4) 4 Reserved Channel 4 (subchannel) output mixer 8 Ch 4 output mixer[1] 0x0000 0000 Ch 4 output mixer[0] 0x0080 0000 0x61 Channel 4 (subchannel) input mixer 8 Ch 4 input mixer[1] 0x0040 0000 Ch 4 input mixer[0] 0x0040 0000 0x62 IDF post scale 4 Post-IDF attenuation register 0x0000 0080 Reserved (4) 0x0000 0000 0x60 0x63–0xF7 0xF8 Device address enable register 4 Write F9 A5 A5 A5 in this register to enable write to device address update (0xF9) 0x0000 0000 0xF9 Device address Update Register 4 u[31:8], New Dev Id[7:1] , ZERO[0] (New Dev Id (7:1) defines the new device address 0X0000 0036 4 Reserved (4) 0x0000 0000 0xFB–0xFF (4) INITIALIZATION VALUE CONTENTS Reserved registers should not be accessed. All DAP coefficients are 3.23 format unless specified otherwise. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 45 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5711. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of 192 fS and 384 fS only. Table 5. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 – – – – – fS = 32-kHz sample rate 0 0 1 – – – – – Reserved (1) 0 1 0 – – – – – Reserved (1) 0 1 1 – – – – – fS = 44.1/48-kHz sample rate 1 0 0 – – – – – fs = 16-kHz sample rate 1 0 1 – – – – – fs = 22.05/24 -kHz sample rate 1 1 0 – – – – – fs = 8-kHz sample rate 1 1 1 – – – – – fs = 11.025/12 -kHz sample rate – – – 0 0 0 – – MCLK frequency = 64 × fS – – – 0 0 1 – – MCLK frequency = 128 × fS (3) – – – 0 1 0 – – MCLK frequency = 192 × fS (4) – – – 0 1 1 – – MCLK frequency = 256 × fS – – – 1 0 0 – – MCLK frequency = 384 × fS – – – 1 0 1 – – MCLK frequency = 512 × fS – – – 1 1 0 – – Reserved (1) – – – 1 1 1 – – Reserved (1) – – – – – – 0 – Reserved (1) – (1) (2) (3) (4) (5) – – – – – – 0 FUNCTION Reserved (2) (3) (2) (5) (2) (1) (2) Reserved registers should not be accessed. Default values are in bold. Only available for 44.1 kHz and 48 kHz rates. Rate only available for 32/44.1/48 KHz sample rates Not available at 8 kHz DEVICE ID REGISTER (0x01) The device ID register contains the ID code for the firmware revision. Table 6. General Status Register (0x01) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 46 FUNCTION Identification code Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error Definitions: • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK Error: The number of SCLKs per LRCLK is changing. • LRCLK Error: LRCLK frequency is changing. • Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync. Table 7. Error Status Register (0x02) D7 D6 D5 D4 D3 D2 D1 D0 1 - – – – – – – MCLK error – 1 – – – – – – PLL autolock error – – 1 – – – – – SCLK error – – – 1 – – – – LRCLK error – – – – 1 – – – Frame slip – – – – – 1 – – Clip indicator – – – – – – 1 – Overcurrent, overtemperature, overvoltage or undervoltage errors – – – – – – – 0 Reserved 0 0 0 0 0 0 0 – No errors (1) FUNCTION (1) Default values are in bold. SYSTEM CONTROL REGISTER 1 (0x03) The system control register 1 has several functions: Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default). Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes the same time as the volume ramp defined in register 0x0E. If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step volume ramp Bits D1–D0: Select de-emphasis Table 8. System Control Register 1 (0x03) D7 D6 D5 D4 D3 D2 D1 D0 0 – – – – – – – PWM high-pass (dc blocking) disabled 1 – – – – – – – PWM high-pass (dc blocking) enabled – 0 – – – – – – Reserved – – 0 – – – – – Soft unmute on recovery from clock error – – 1 – – – – – Hard unmute on recovery from clock error – – – 0 – – – – Reserved – – – – 0 – – – Reserved (1) FUNCTION (1) (1) (1) (1) (1) (1) – – – – – 0 – – Reserved – – – – – – 0 0 No de-emphasis – – – – – – 0 1 De-emphasis for fS = 32 kHz – – – – – – 1 0 De-emphasis for fS = 44.1 kHz – – – – – – 1 1 De-emphasis for fS = 48 kHz (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 47 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 9, the TAS5711 supports 9 serial data modes. The default is 24-bit, I2S mode, Table 9. Serial Data Interface Control Register (0x04) Format RECEIVE SERIAL DATA INTERFACE FORMAT WORD LENGTH D7–D4 D3 D2 D1 D0 Right-justified 16 0000 0 0 0 0 Right-justified 20 0000 0 0 0 1 Right-justified 24 0000 0 0 1 0 2 I S 16 000 0 0 1 1 I2S 20 0000 0 1 0 0 24 0000 0 1 0 1 Left-justified 16 0000 0 1 1 0 Left-justified 20 0000 0 1 1 1 Left-justified 24 0000 1 0 0 0 Reserved 0000 1 0 0 1 Reserved 0000 1 0 1 0 Reserved 0000 1 0 1 1 Reserved 0000 1 1 0 0 Reserved 0000 1 1 0 1 Reserved 0000 1 1 1 0 Reserved 0000 1 1 1 1 I2S (1) 48 (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down(hard mute). Table 10. System Control Register 2 (0x05) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 0 – – – – – – – Mid-Z ramp disabled 1 – – – – – – – Mid-Z ramp enabled – 0 – – – – – – Exit all-channel shutdown (normal operation) – 1 – – – – – – Enter all-channel shutdown (hard mute) (1) – – – – 0 – – – Subchannel in AD mode – – – – 1 – – – Subchannel in BD mode – – – – – 0 – – 2.0 mode [2.0 BTL] – – – – – 1 – – 2.1 mode [2 SE + 1 BTL] – 0 – – – – – – Exit all-channel shutdown (normal operation) – – – – – – 0 – A_SEL configured as input (1) – – – – – – 1 – A_SEL configured as FAULT output – – 0 0 – – – 0 Reserved (1) (1) (1) Default values are in bold. SOFT MUTE REGISTER (0x06) Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). Table 11. Soft Mute Register (0x06) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 – – – Reserved – – – – – 0 – – Soft unmute channel 3 – – – – – 1 – – Soft mute channel 3 – – – – – – 0 – Soft unmute channel 2 – – – – – – 1 – Soft mute channel 2 – – – – – – – 0 Soft unmute channel 1 – – – – – – – 1 Soft mute channel 1 (1) FUNCTION (1) (1) (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 49 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A) Step size is 0.5 dB. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Channel-3 volume – 0x0A (default is 0 dB) Table 12. Volume Registers (0x07, 0x08, 0x09, 0x0A) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 0 0 0 0 0 0 24 dB 0 0 1 1 0 0 0 0 0 dB (default for individual channel volume) 1 1 1 1 1 1 1 0 –103 dB 1 1 1 1 1 1 1 1 Soft mute (1) FUNCTION (1) Default values are in bold. VOLUME CONFIGURATION REGISTER (0x0E) Bits D2–D0: Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp.Volume steps occur at a rate that depends on the sample rate of the I2S data as follows Sample Rate (KHz) Approximate Ramp Rate 8/16/32 125 us/step 11.025/22.05/44.1 90.7 us/step 12/24/48 83.3 us/step Table 13. Volume Control Register (0x0E) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 1 – – 1 0 – – – Reserved – 0 – – – – – – Subchannel (ch4) volume = ch1 volume (2) (1) – 1 – – – – – – Subchannel volume = register 0x0A (2) – – 0 – – – – – Ch3 volume = ch2 volume (1) – – 1 – – – – – Ch3 volume = register 0x0A – – – – – 0 0 0 Volume slew 512 steps (43-ms volume ramp time at 48 kHz) – – – – – 0 0 1 Volume slew 1024 steps (85-ms volume ramp time at 48 kHz) – – – – – 0 1 0 Volume slew 2048 steps (171- ms volume ramp time at 48 kHz) – – – – – 0 1 1 Volume slew 256 steps (21-ms volume ramp time at 48 kHz) – – – – – 1 X X Reserved (1) (2) 50 (1) Default values are in bold. Bits 6:5 can be changed only when volume is in MUTE [master volume = MUTE (register 0x07 = 0xFF)]. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 MODULATION LIMIT REGISTER (0x10) The modulation limit is the maximum duty cycle of the PWM output waveform. Table 14. Modulation Limit Register (0x10) (1) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT – – – – – 0 0 0 99.2% – – – – – 0 0 1 – – – – – 0 1 0 – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.5% – – – – – 1 1 1 93.8% 0 0 0 0 0 – – – RESERVED 98.4% 97.7% (1) Default values are in bold. INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14) Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14. Table 15. Channel Interchannel Delay Register Format BITS DEFINITION (1) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 – – Minimum absolute delay, 0 DCLK cycles 0 1 1 1 1 1 – – Maximum positive delay, 31 × 4 DCLK cycles 1 0 0 0 0 0 – – Maximum negative delay, –32 × 4 DCLK cycles 0 0 RESERVED SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs 0x11 1 0 1 0 1 1 – – Default value for channel 1 0x12 0 1 0 1 0 1 – – Default value for channel 2 (1) (1) 0x13 1 0 1 0 1 1 – – Default value for channel 1 (1) 0x14 0 1 0 1 0 1 – – Default value for channel 2 (1) Default values are in bold. ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown. REGISTER AD MODE BD MODE 0x11 AC B8 0x12 54 60 0x13 AC A0 0x14 54 48 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 51 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register. This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is set to 0 in system control register 2, 0x05). Table 16. Shutdown Group Register D7 (1) 52 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 – – – – – – – Reserved (1) – 0 – – – – – – Reserved (1) – – 1 – – – – – Reserved (1) – – – 1 – – – – Reserved (1) – – – – 0 – – – PWM channel 4 does not belong to shutdown group. – – – – 1 – – – PWM channel 4 belongs to shutdown group. – – – – – 0 – – PWM channel 3 does not belong to shutdown group. – – – – – 1 – – PWM channel 3 belongs to shutdown group. – – – – – – 0 – PWM channel 2 does not belong to shutdown group. – – – – – – 1 – PWM channel 2 belongs to shutdown group. – – – – – – – 0 PWM channel 1 does not belong to shutdown group. – – – – – – – 1 PWM channel 1 belongs to shutdown group. (1) (1) (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are only approximate and vary depending on device activity level and I2S clock stability. Table 17. Start/Stop Period Register (0x1A) D7 D6 D5 D4 D3 D2 D1 D0 0 – – – – – – – SSTIMER enabled (1) 1 – – – – – – – SSTIMER disabled – 0 0 – – – – – Reserved – – – 0 0 – – – No 50% duty cycle start/stop period – – – 0 1 0 0 0 16.5-ms 50% duty cycle start/stop period – – – 0 1 0 0 1 23.9-ms 50% duty cycle start/stop period – – – 0 1 0 1 0 31.4-ms 50% duty cycle start/stop period – – – 0 1 0 1 1 40.4-ms 50% duty cycle start/stop period – – – 0 1 1 0 0 53.9-ms 50% duty cycle start/stop period – – – 0 1 1 0 1 70.3-ms 50% duty cycle start/stop period – – – 0 1 1 1 0 94.2-ms 50% duty cycle start/stop period – – – 0 1 1 1 1 125.7-ms 50% duty cycle start/stop period (1) – – – 1 0 0 0 0 164.6-ms 50% duty cycle start/stop period – – – 1 0 0 0 1 239.4-ms 50% duty cycle start/stop period – – – 1 0 0 1 0 314.2-ms 50% duty cycle start/stop period – – – 1 0 0 1 1 403.9-ms 50% duty cycle start/stop period – – – 1 0 1 0 0 538.6-ms 50% duty cycle start/stop period – – – 1 0 1 0 1 703.1-ms 50% duty cycle start/stop period – – – 1 0 1 1 0 942.5-ms 50% duty cycle start/stop period – – – 1 0 1 1 1 1256.6-ms 50% duty cycle start/stop period – – – 1 1 0 0 0 1728.1-ms 50% duty cycle start/stop period – – – 1 1 0 0 1 2513.6-ms 50% duty cycle start/stop period – – – 1 1 0 1 0 3299.1-ms 50% duty cycle start/stop period – – – 1 1 0 1 1 4241.7-ms 50% duty cycle start/stop period – – – 1 1 1 0 0 5655.6-ms 50% duty cycle start/stop period – – – 1 1 1 0 1 7383.7-ms 50% duty cycle start/stop period – – – 1 1 1 1 0 9897.3-ms 50% duty cycle start/stop period – – – 1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period (1) FUNCTION (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 53 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5711 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0x00 to register 0x1B enables the trim that was programmed at the factory. Note that trim must always be run following reset of the device. Table 18. Oscillator Trim Register (0x1B) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION (1) 1 – – – – – – – Reserved – 0 – – – – – – Oscillator trim not done (read-only) – 1 – – – – – – Oscillator trim done (read only) – – 0 0 0 0 – – Reserved – – – – – – 0 – Select factory trim (Write a 0 to select factory trim; default is 1.) – – – – – – 1 – Factory trim disabled – – – – – – – 0 Reserved (1) (1) (1) (1) (1) Default values are in bold. BKND_ERR REGISTER (0x1C) When a back-end error signal is received from the internal power stage, the power stage is reset stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting to re-start the power stage. Table 19. BKND_ERR Register (0x1C) (1) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 X Reserved – – – – 0 0 1 0 Set back-end reset period to 299 ms – – – – 0 0 1 1 Set back-end reset period to 449 ms – – – – 0 1 0 0 Set back-end reset period to 598 ms – – – – 0 1 0 1 Set back-end reset period to 748 ms – – – – 0 1 1 0 Set back-end reset period to 898 ms – – – – 0 1 1 1 Set back-end reset period to 1047 ms – – – – 1 0 0 0 Set back-end reset period to 1197 ms – – – – 1 0 0 1 Set back-end reset period to 1346 ms – – – – 1 0 1 X Set back-end reset period to 1496 ms – – – – 1 1 X X Set back-end reset period to 1496 ms (1) (2) 54 FUNCTION (2) This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset. Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 20. Input Multiplexer Register (0x20) (1) D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 0 0 0 FUNCTION D23 D22 D21 D20 D19 D18 D17 D16 0 – – – – – – – Channel-1 AD mode 1 – – – – – – – Channel-1 BD mode – 0 0 0 – – – – SDIN-L to channel 1 – 0 0 1 – – – – SDIN-R to channel 1 – 0 1 0 – – – – Reserved – 0 1 1 – – – – Reserved – 1 0 0 – – – – Reserved – 1 0 1 – – – – Reserved – 1 1 0 – – – – Ground (0) to channel 1 – 1 1 1 – – – – Reserved – – – – 0 – – – Channel 2 AD mode – – – – 1 – – – Channel 2 BD mode – – – – – 0 0 0 SDIN-L to channel 2 – – – – – 0 0 1 SDIN-R to channel 2 – – – – – 0 1 0 Reserved – – – – – 0 1 1 Reserved – – – – – 1 0 0 Reserved – – – – – 1 0 1 Reserved – – – – – 1 1 0 Ground (0) to channel 2 – – – – – 1 1 1 Reserved D15 D14 D13 D12 D11 D10 D9 D8 0 1 1 1 0 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 1 0 Reserved (1) FUNCTION (1) (1) (1) (1) FUNCTION Reserved (1) Reserved (1) FUNCTION Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 55 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 21. Subchannel Control Register (0x21) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 0 1 0 0 0 0 1 – – – – – – – 0 (L + R)/2 – – – – – – – 1 Left-channel post-BQ D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 (1) Reserved (1) FUNCTION Reserved (1) Reserved (1) FUNCTION (1) FUNCTION Reserved (1) Default values are in bold. PWM OUTPUT MUX REGISTER (0x25) This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin. Bits D21–D20: Selects which PWM channel is output to OUT_A Bits D17–D16: Selects which PWM channel is output to OUT_B Bits D13–D12: Selects which PWM channel is output to OUT_C Bits D09–D08: Selects which PWM channel is output to OUT_D Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03. See Figure 51 for details. Table 22. PWM Output Mux Register (0x25) D31 D30 D29 D28 D27 D26 D25 D24 0 0 0 0 0 0 0 1 D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION Reserved (1) FUNCTION (1) 0 0 – – – – – – Reserved – – 0 0 – – – – Multiplex PWM 1 to OUT_A – – 0 1 – – – – Multiplex PWM 2 to OUT_A – – 1 0 – – – – Multiplex PWM 3 to OUT_A – – 1 1 – – – – Multiplex PWM 4 to OUT_A – – – – 0 0 – – Reserved – – – – – – 0 0 Multiplex PWM 1 to OUT_B – – – – – – 0 1 Multiplex PWM 2 to OUT_B – – – – – – 1 0 Multiplex PWM 3 to OUT_B – – – – – – 1 1 Multiplex PWM 4 to OUT_B D15 D14 D13 D12 D11 D10 D9 D8 0 0 – – – – – – Reserved – – 0 0 – – – – Multiplex PWM 1 to OUT_C – – 0 1 – – – – Multiplex PWM 2 to OUT_C (1) (1) 56 (1) (1) (1) FUNCTION (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Table 22. PWM Output Mux Register (0x25) (continued) – – 1 0 – – – – Multiplex PWM 3 to OUT_C – – 1 1 – – – – Multiplex PWM 4 to OUT_C – – – – 0 0 – – Reserved – – – – – – 0 0 Multiplex PWM 1 to OUT_D – – – – – – 0 1 Multiplex PWM 2 to OUT_D – – – – – – 1 0 Multiplex PWM 3 to OUT_D – – – – – – 1 1 Multiplex PWM 4 to OUT_D D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 (1) (1) FUNCTION Reserved (1) DRC CONTROL (0x46) Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default. Table 23. DRC Control Register D31 D30 D29 D28 D27 D26 D25 D24 Reserved Reserved (1) Reserved (1) – Reserved (1) – – Disable complementary (1 - H) low-pass filter generation – – Enable complementary (1 - H) low-pass filter generation – – – – – – – 0 0 0 0 0 0 0 0 0 0 D23 D22 D21 D20 D19 D18 D17 D16 0 0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 – – – – – – – 0 – – – – – 1 – – – – – – 0 – – – – 1 (1) FUNCTION (1) FUNCTION FUNCTION FUNCTION Reserved (1) – – – – – – 0 – DRC2 turned OFF – – – – – – 1 – DRC2 turned ON – – – – – – – 0 DRC1 turned OFF – – – – – – – 1 DRC1 turned ON (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 57 TAS5711 SLOS600 – DECEMBER 2009 www.ti.com BANK SWITCH AND EQ CONTROL (0x50) Table 24. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 0 – – – – – – – 32 kHz, does not use bank 3 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved (1) – – 0 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 3 – – – 1 – – – – 44.1/48 kHz, uses bank 3 – – – – 0 – – – 16 kHz, does not use bank 3 – – – – 1 – – – 16 kHz, uses bank 3 – – – – – 0 – – 22.025/24 kHz, does not use bank 3 – – – – – 1 – – 22.025/24 kHz, uses bank 3 – – – – – – 0 – 8 kHz, does not use bank 3 – – – – – – 1 – 8 kHz, uses bank 3 – – – – – – – 0 11.025 kHz/12, does not use bank 3 – – – – – – – 1 11.025/12 kHz, uses bank 3 D23 D22 D21 D20 D19 D18 D17 D16 0 – – – – – – – 32 kHz, does not use bank 2 1 – – – – – – – 32 kHz, uses bank 2 – 1 – – – – – – Reserved (1) – – 1 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 2 – – – 1 – – – – 44.1/48 kHz, uses bank 2 – – – – 0 – – – 16 kHz, does not use bank 2 – – – – 1 – – – 16 kHz, uses bank 2 – – – – – 0 – – 22.025/24 kHz, does not use bank 2 – – – – – 1 – – 22.025/24 kHz, uses bank 2 – – – – – – 0 – 8 kHz, does not use bank 2 – – – – – – 1 – 8 kHz, uses bank 2 – – – – – – – 0 11.025/12 kHz, does not use bank 2 – – – – – – – 1 11.025/12 kHz, uses bank 2 D15 D14 D13 D12 D11 D10 D9 D8 0 – – – – – – – 32 kHz, does not use bank 1 1 – – – – – – – 32 kHz, uses bank 1 (1) 58 FUNCTION (1) (1) (1) (1) (1) (1) FUNCTION (1) (1) (1) (1) (1) (1) FUNCTION (1) (1) – 0 – – – – – – Reserved – – 0 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 1 – – – 1 – – – – 44.1/48 kHz, uses bank 1 – – – – 0 – – – 16 kHz, does not use bank 1 – – – – 1 – – – 16 kHz, uses bank 1 – – – – – 0 – – 22.025/24 kHz, does not use bank 1 – – – – – 1 – – 22.025/24 kHz, uses bank 1 – – – – – – 0 – 8 kHz, does not use bank 1 – – – – – – 1 – 8 kHz, uses bank 1 – – – – – – – 0 11.025/12 kHz, does not use bank 1 – – – – – – – 1 11.025/12 kHz, uses bank 1 (1) (1) (1) (1) (1) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 TAS5711 www.ti.com SLOS600 – DECEMBER 2009 Table 24. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 0 1 – – – – – – – EQ OFF (bypass BQ 0-7 of channels 1 and 2) – 0 – – – – – – Reserved – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. – – – 0 – – – – L and R can be written independently. – – – 1 – – – – L and R are ganged for EQ biquads; a write to left-channel BQ is also written to right-channel BQ. (0x29–0x2F is ganged to 0x30–0x36.Also 0x58–0x5B is ganged to 0x5C–0x5F) – – – – 0 – – – Reserved – – – – – 0 0 0 No bank switching. All updates to DAP – – – – – 0 0 1 Configure bank 1 (32 kHz by default) – – – – – 0 1 0 Configure bank 2 (44.1/48 kHz by default) – – – – – 0 1 1 Configure bank 3 (other sample rates by default) – – – – – 1 0 0 Automatic bank selection – – – – – 1 0 1 Reserved – – – – – 1 1 X Reserved 1 (2) FUNCTION EQ ON (2) (2) Use bank-mapping in bits D31–D8. (2) (2) (2) Default values are in bold. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): TAS5711 59 PACKAGE OPTION ADDENDUM www.ti.com 23-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TAS5711PHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TAS5711PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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