TI SN74HC166A-EP

SCLS559 − JANUARY 2004
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Synchronous Load
Direct Overriding Clear
Parallel-to-Serial Conversion
D OR PW PACKAGE
(TOP VIEW)
SER
A
B
C
D
CLK INH
CLK
GND
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
SH/LD
H
QH
G
F
E
CLR
description/ordering information
This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high,
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
ORDERING INFORMATION
−40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − D
Tape and reel
SN74HC166AIDREP
TSSOP − PW
Tape and reel
SN74HC166AIPWREP§
SHC166IEP
SHC166IEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
§ Product Preview
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
POST OFFICE BOX 655303
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1
SCLS559 − JANUARY 2004
FUNCTION TABLE
OUTPUTS
INPUTS
INTERNAL
CLR
SH/LD
CLK INH
CLK
SER
PARALLEL
A...H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
↑
X
a...h
a
b
h
H
H
L
↑
H
X
H
QAn
QGn
H
H
L
↑
L
X
L
QAn
QGn
H
X
H
↑
X
X
QA0
QB0
QH0
logic diagram (positive logic)
A
SH/LD
SER
15
B
2
C
D
3
4
1D
C1
R
1D
C1
R
E
F
G
H
5
10
11
12
14
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1
6
CLK INH
7
CLK
9
CLR
1D
C1
R
13
QH
2
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SCLS559 − JANUARY 2004
typical clear, shift, load, inhibit, and shift sequence
CLK
CLK INH
CLR
SER
SH/LD
Parallel
Inputs
A
H
B
L
C
H
D
L
E
H
F
L
G
H
H
H
QH
Serial Shift
Clear
H
Inhibit
H
L
H
L
H
L
H
Serial Shift
Load
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCLS559 − JANUARY 2004
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 4.5 V
High-level input voltage
2
5
6
3.15
V
V
0.5
1.35
V
1.8
0
Output voltage
VCC
VCC
0
VCC = 2 V
VCC = 4.5 V
Input transition rise/fall time
UNIT
4.2
Input voltage
∆t/∆v†
MAX
VCC = 4.5 V
VCC = 6 V
Low-level input voltage
VI
VO
NOM
1.5
VCC = 6 V
VCC = 2 V
VIL
MIN
V
V
1000
500
ns
VCC = 6 V
400
TA
Operating free-air temperature
−40
85
°C
† If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
II
ICC
TEST CONDITIONS
MIN
2V
1.9
1.998
1.9
IOH = −20 µA
4.4
4.499
4.4
6V
5.9
5.999
5.9
IOH = −4 mA
IOH = −5.2 mA
4.5 V
3.98
4.3
3.84
6V
5.48
VI = VIH or VIL
5.8
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
IOL = 20 µA
4.5 V
0.001
0.1
0.1
6V
0.001
0.1
0.1
IOL = 4 mA
IOL = 5.2 mA
4.5 V
0.17
0.26
0.33
6V
0.15
0.26
0.33
6V
±0.1
±100
±1000
nA
8
80
µA
10
10
pF
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
TA = 25°C
MIN
TYP
MAX
4.5 V
IO = 0
Ci
4
VCC
6V
2 V to 6 V
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3
V
SCLS559 − JANUARY 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CLR low
tw
SH/LD high before CLK↑
SER before CLK↑
tsu
Setup time
CLK INH low before CLK↑
Data before CLK↑
CLR inactive before CLK↑
SH/LD high after CLK↑
SER after CLK
CLK↑
th
Data after CLK
CLK↑
POST OFFICE BOX 655303
MAX
2V
6
5
31
25
6V
36
29
2V
100
125
4.5 V
20
25
6V
17
21
2V
80
100
4.5 V
16
20
6V
14
17
2V
145
180
4.5 V
29
36
6V
25
31
2V
80
100
4.5 V
16
20
6V
14
17
2V
100
125
4.5 V
20
25
6V
17
21
2V
80
100
4.5 V
16
20
6V
14
17
2V
40
50
4.5 V
8
10
6V
7
9
2V
0
0
4.5 V
0
0
6V
0
0
2V
5
5
4.5 V
5
5
6V
5
5
2V
0
0
4.5 V
0
0
6V
0
0
Hold time
CLK INH high after CLK↑
MIN
4.5 V
Pulse duration
CLK high or low
TA = 25°C
MIN
MAX
2V
5
5
4.5 V
5
5
6V
5
5
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
5
SCLS559 − JANUARY 2004
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tpd
CLR
QH
CLK
QH
tt
Any
VCC
MIN
TA = 25°C
TYP
MAX
MIN
2V
6
11
5
4.5 V
31
36
25
6V
36
45
29
MAX
UNIT
MHz
2V
62
120
150
4.5 V
18
24
30
6V
13
20
26
2V
75
150
190
4.5 V
15
30
38
6V
13
26
32
2V
38
75
95
4.5 V
8
15
19
6V
6
13
16
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance
No load
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TYP
50
UNIT
pF
SCLS559 − JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
50%
10%
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
90%
tr
th
90%
tPHL
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPLH
50%
10%
tf
tf
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HC166AIDREP
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/04690-01XE
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HC166A-EP :
• Automotive: SN74HC166A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74HC166AIDREP
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.5
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC166AIDREP
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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