SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 D Controlled Baseline D D D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Supports Unregulated Battery Operation Down to 2.7 V Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Ioff Supports Partial Power-Down-Mode Operation D D Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) PW OR NS PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK description/ordering information This octal D-type flip-flop is designed specifically for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE‡ TA ORDERABLE PART NUMBER TOP-SIDE MARKING −40°C to 85°C TSSOP − PW Tape and reel SN74LVTH273IPWREP −55°C to 125°C SOP − NS Tape and reel SN74LVTH273MNSREP LH273EP LVTH273EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2006, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"& *%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"# #"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*& "&#"/ !)) '!!&"&# POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 FUNCTION TABLE (each flip-flop) INPUTS CLR CLK OUTPUT Q D L X X L H ↑ H H H ↑ L L H H or L X Q0 logic diagram (positive logic) CLK 1D 2D 3D 4D 3 4 7 8 6D 13 7D 14 8D 17 18 11 CLK(I) 1D 1D C1 1 1D C1 R CLR 5D 1D C1 R 1D C1 R 1D C1 R 1D C1 R 1D C1 R C1 R R R 2 5 6 1Q 2Q 3Q 9 4Q 12 5Q 15 6Q 16 7Q 19 8Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94.4°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 V IOH IOL High-level output current −32 mA Low-level output current 64 mA ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature High-level input voltage 2 V V 0.8 SN74LVTH273I −40 85 SN74LVTH273M −55 125 V °C NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 2.7 V, II = −18 mA VCC = 2.7 V to 3.6 V, IOH = −100 µA VOH VCC = 2.7 V, IOH = −8 mA VCC = 3 V, IOH = −32 mA VCC = 2.7 V VOL VCC = 3 V Control inputs II Data inputs Ioff SN74LVTH273I TYP† MAX TEST CONDITIONS MIN −1.2 VCC−0.2 2.4 2 2 0.2 0.2 0.5 0.5 IOL = 16 mA IOL = 32 mA 0.4 0.4 0.5 0.5 IOL = 64 mA 0.55 0.55 10 12 ±1 ±2 1 1 VCC = 0, VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V II(hold) Data inputs 75 −75 Outputs high VCC = 3.6 V, IO = 0, VI = VCC or GND ∆ICC§ VCC = 3 V to 3.6 V, One input at VCC − 0.6 V, Other inputs at VCC or GND −5 ±100 75 VCC = 3.6 V‡, VI = 0 to 3.6 V ICC −5 ±100 −75 Outputs low UNIT V V IOL = 100 µA IOL = 24 mA VI = VCC VI = 0 VCC = 3 V −1.2 VCC−0.2 2.4 VCC = 0 or 3.6 V, VI = 5.5 V VCC = 3.6 V, VI = VCC or GND VCC = 3.6 V SN74LVTH273M TYP† MAX MIN 500 −750 500 −750 0.19 0.19 5 5 0.2 0.2 V µA A µA µA mA mA Ci VI = 3 V or 0 4 4 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN fclock tw VCC = 2.7 V MAX Clock frequency MIN 150 Pulse duration tsu Setup time th Hold time, data high or low after CLK↑ UNIT MAX MHz 3.3 3.3 Data high or low before CLK↑ 2.3 2.7 CLR high before CLK↑ 2.3 2.7 0 0 ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LVTH273I PARAMETER fmax tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) VCC = 2.7 V MIN MAX VCC = 2.7 V MIN MAX 150 CLK Any Q CLR Any Q † All typical values are at VCC = 3.3 V, TA = 25°C. 4 VCC = 3.3 V ±0.3 V MIN TYP† MAX SN74LVTH273M MHz 1.7 3.2 4.9 5.5 7 1.9 3.2 4.8 5.1 6.6 1.6 2.7 4.3 4.7 7 POST OFFICE BOX 655303 UNIT • DALLAS, TEXAS 75265 ns ns SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 2.7 V 1.5 V Input 1.5 V 0V VOH 1.5 V 1.5 V VOL Output tPLZ 3V 1.5 V tPZH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH Output 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CLVTH273MNSREPG4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH273IPWREP ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVTH273MNSREP ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04674-01XE ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/04674-02YE ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVTH273-EP : • Catalog: SN74LVTH273 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH273IPWREP TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 SN74LVTH273MNSREP SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH273IPWREP TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVTH273MNSREP SO NS 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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