HYNIX HYMD564726CP8J-D43

184pin Unbuffered DDR SDRAM DIMMs based on 512Mb C ver. (TSOP)
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 512Mb C ver. DDR SDRAMs in 400mil
TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb C ver. based unbuffered DIMM series provide
a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange
and addition.
FEATURES
•
JEDEC Standard 184-pin dual in-line memory module
(DIMM)
•
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
•
Two ranks 128M x 72, 128M x 64 and One rank 64M
x 72, 64M x 64, 32M x 64 organization
•
Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
•
2.6V ± 0.1V VDD and VDDQ Power supply for
DDR400, 2.5V ± 0.2V for DDR333 and below
•
Auto refresh and self refresh supported
•
8192 refresh cycles / 64ms
•
All inputs and outputs are compatible with SSTL_2
interface
•
Serial Presence Detect (SPD) with EEPROM
•
Fully differential clock operations (CK & /CK) with
133/166/200MHz
•
Built with 512Mb DDR SDRAMs in 400 mil TSOP II
packages
•
DLL aligns DQ and DQS transition with CK transition
•
All lead-free products (RoHS compliant)
•
Programmable CAS Latency: DDR266(2, 2.5 clock),
DDR333(2.5 clock), DDR400(3 clock)
ADDRESS TABLE
Organization
Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
256MB
32M x 64
1
32Mb x 16
4
13(A0~A12)/2(BA0,BA1)/10(A0~A9)
8K / 64ms
512MB
64M x 64
1
64Mb x 8
8
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
8K / 64ms
512MB
64M x 72
1
64Mb x 8
9
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
8K / 64ms
1GB
128M x 64
2
64Mb x 8
16
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
8K / 64ms
1GB
128M x 72
2
64Mb x 8
18
13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11)
8K / 64ms
PERFORMANCE RANGE
Part-Number Suffix
-D431
-J
-H
Unit
Speed Bin
DDR400B
DDR333
DDR266B
-
3-3-3
2.5-3-3
2.5-3-3
CK
CL=3
200
-
-
MHz
CL=2.5
166
166
133
MHz
CL=2
133
133
133
MHz
CL - tRCD- tRP
Max Clock
Frequency
Note:
1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 and below
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.3 / Feb. 2006
1
11
184pin Unbuffered DDR SDRAM DIMMs
ORDERING INFORMATION
Part Number
Density Organization
# of
DRAMs
Material
DIMM Dimension
ECC
Support
HYMD532646CP6-H
256MB
32Mb x 16
4
Lead-free1
133.35 x 31.75 x 3.18 [mm3]
None
HYMD532646CP6J-D43/J
256MB
32Mb x 16
4
↑
↑
None
HYMD564646CP8-H
512MB
64Mb x 8
8
↑
↑
None
HYMD564646CP8J-D43/J
512MB
64Mb x 8
8
↑
↑
None
HYMD564726CP8-H
512MB
64Mb x 8
9
↑
↑
ECC
HYMD564726CP8J-D43/J
512MB
64Mb x 8
9
↑
↑
ECC
HYMD512646CP8-H
1GB
64Mb x 8
16
↑
133.35 x 31.75 x 4 [mm3]
None
HYMD512646CP8J-D43/J
1GB
64Mb x 8
16
↑
↑
None
HYMD512726CP8-H
1GB
64Mb x 8
18
↑
↑
ECC
HYMD512726CP8J-D43/J
1GB
64Mb x 8
18
↑
↑
ECC
Note:
1. The “Lead-free” products contain Lead less than 0.1% by weight and satisfy RoHS - please contact Hynix for product availability.
* These products are built with HY5DU124(8,16)22CTP, the Hynix DDR SDRAM component.
Rev. 1.3 / Feb. 2006
2
11
184pin Unbuffered DDR SDRAM DIMMs
PIN DESCRIPTION
Pin
CK0, /CK0
CS0, CS1
CKE0, CKE1
/RAS, /CAS, /WE
Pin Description
Pin
Pin Description
Differential Clock Inputs
Chip Select Input
Clock Enable Input
Commend Sets Inputs
VDDQ
VSS
VREF
VDDSPD
DQs Power Supply
Ground
Reference Power Supply
Power Supply for SPD
A0 ~ A12
Address
SA0~SA2
E2PROM Address Inputs
BA0, BA1
Bank Address
SCL
E2PROM Clock
DQ0~DQ63
Data Inputs/Outputs
SDA
CB0~CB7
DQS0~DQS17
DM0~7
VDD
/RESET
Data Strobe Inputs/Outputs
Data Strobe Inputs/Outputs
Data-in Mask
Power Supply
Reset Enable
WP
VDDID
DU
NC
FETEN
E2PROM Data I/O
Write Protect Flag
VDD Identification Flag
Do not Use
No Connection
FET Enable
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
/RESET
VSS
DQ8
DQ9
DQS1
VDDQ
CK1*
/CK1*
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
Name
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0/NC
CB1/NC
VDD
DQS8
A0
CB2/NC
VSS
CB3/NC
BA1
Key
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Name
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
/CS2*
DQ48
DQ49
VSS
CK2*
/CK2*
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NU
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Name
VSS
DQ4
DQ5
VDDQ
DM0,DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1,DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
BA2*
DQ20
A12
VSS
DQ21
A11
DM2,DQS11
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Name
VSS
A6
DQ28
DQ29
VDDQ
DM3,DQS12
A3
DQ30
VSS
DQ31
CB4/NC
CB5/NC
VDDQ
CK0
/CK0
VSS
DM8,DQS17
A10
CB6/NC
VDDQ
CB7/NC
key
VSS
DQ36
DQ37
VDD
DM4,DQS13
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Name
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5,DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
A132, NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7,DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Note:
1. * : These pins are not used in this module.
2. Pin 167 is NC for 256MB, 512MB, and 1GB, or A13 for 2GB module.
Rev. 1.3 / Feb. 2006
3
11
184pin Unbuffered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB, 32M x 64 Unbuffered DIMM: HYMD532646CP6[J]
/CS0
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CS
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
/CS
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D1
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
I/O15
DQ23
SCL
W
P A0
SDA
A1 A2
SA0 SA1 SA2
*Clock Wiring
SDRAMs
Clock Input
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
NC
2 SDRAMs
2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
/CS
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
/CS
D2
D3
I/O15
DQ55
Serial PD
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VDD SPD
SPD
VDD /VDDQ
DO-D3
VREF
DO-D3
VSS
DO-D3
VDDID
Strap:see Note 4
BA0-BA1
A0-A13
/RAS
/CAS
CKE0
/WE
Rev. 1.3 / Feb. 2006
BA0-BA1 : SDRAMs D0-D3
A0-A13 : SDRAMs D0-D3
/RAS : SDRAMs D0-D3
/CAS : SDRAMs D0-D3
CKE : SDRAMs D0-D3
/WE : SDRAMs D0-D3
Notes :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms +- 5%
4
11
184pin Unbuffered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J]
/CS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DM
I/O7
I/O6
I/O1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O0
I/O5
/CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
I/O4
I/O3
I/O2
DQS1
DM1/DQS10
/CS
DQS
D4
I/O0
I/O5
I/O4
I/O3
I/O2
DQS5
DM5/DQS14
DM
I/O7
I/O6
I/O1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O0
I/O5
/CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
I/O4
I/O3
I/O2
DQS2
DM2/DQS11
DM
I/O7
I/O6
I/O1
/CS
DQS
D5
I/O0
I/O5
I/O4
I/O3
I/O2
DQS6
DM6/DQS15
DM
I/O7
I/O6
I/O1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O0
I/O5
/CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
I/O4
I/O3
I/O2
DQS3
DM3/DQS12
DM
I/O7
I/O6
I/O1
/CS
DQS
D6
I/O0
I/O5
I/O4
I/O3
I/O2
DQS7
DM7/DQS16
DM
I/O7
I/O6
I/O1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O0
I/O5
/CS
DQS
I/O4
I/O3
I/O2
VDD SPD
SDA
W
P
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
Serial PD
SCL
DM
I/O7
I/O6
I/O1
SPD
VDD /VDDQ
DO-D7
VREF
A0
A1
A2
SA0 SA1 SA2
DO-D7
DO-D7
VSS
VDDID
Strap:see Note 4
DM
I/O7
I/O6
I/O1
/CS
DQS
D7
I/O0
I/O5
I/O4
I/O3
I/O2
*Clock Wiring
Clock Input
SDRAMs
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
BA0-BA1
A0-A13
BA0-BA1 : SDRAMs D0-D7
A0-A13 : SDRAMs D0-D7
/RAS
/RAS : SDRAMs D0-D7
/CAS
/CAS : SDRAMs D0-D7
CKE0
/WE
Rev. 1.3 / Feb. 2006
CKE : SDRAMs D0-D7
/WE : SDRAMs D0-D7
1. DQ-to-I/O wiring is shown as recommended but
may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms +- 5%
5
11
184pin Unbuffered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB, 64M x 72 ECC Unbuffered DIMM : HYMD564726CP8[J]
/CS0
DQS4
DM4/DQS13
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O7
I/O6
I/O1
DM
/CS
DQS
D0
I/O0
I/O5
I/O4
I/O3
I/O2
I/O7
I/O6
I/O1
DM
/CS
DQS
D1
I/O0
I/O5
I/O4
I/O3
I/O2
I/O7
I/O6
I/O1
DM
/CS
DQS
BA0-BA1
A0-A13
I/O4
I/O3
I/O2
DM
/CS
I/O7
I/O6
I/O1
DQS
D3
I/O0
I/O5
I/O4
I/O3
I/O2
VDD SPD
/CS
DQS
D5
I/O4
I/O3
I/O2
DM
I/O7
I/O6
I/O1
I/O0
I/O5
/CS
DQS
D6
I/O4
I/O3
I/O2
DM
I/O7
I/O6
I/O1
I/O0
I/O5
/CS
DQS
D7
I/O4
I/O3
I/O2
SPD
*Clock Wiring
VDD /VDDQ
DM
I/O7
I/O6
I/O1
I/O0
I/O5
/CS
DQS
DO-D8
VREF
Clock Input
DO-D8
VSS
D8
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
DO-D8
VDDID
SCL
I/O2
BA0-BA1 : SDRAMs D0-D8
A0-A13 : SDRAMs D0-D8
/CAS : SDRAMs D0-D8
CKE : SDRAMs D0-D8
/WE : SDRAMs D0-D8
SDRAMs
3 SDRAMs
3 SDRAMs
3 SDRAMs
Strap:see Note 4
Serial PD
I/O4
I/O3
/CAS
Rev. 1.3 / Feb. 2006
I/O0
I/O5
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/RAS : SDRAMs D0-D8
/WE
DM
I/O7
I/O6
I/O1
DQS7
DM7/DQS16
/RAS
CKE0
I/O2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
I/O0
I/O5
DQS3
DM3/DQS12
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D4
DQS6
DM6/DQS15
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
I/O4
I/O3
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O0
I/O5
/CS
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O7
I/O6
I/O1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
*Wire per Clock Loading
Table/Wiring Diagrams
SDA
W
P
A0
A1
A2
SA0 SA1 SA2
Notes :
1. DQ-to-I/O wiring is shown as recommended but
may be changed.
2. DQ/DQS/DM/CKE/S relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms +- 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms +- 5%
6
11
184pin Unbuffered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB, 128M x 64 Unbuffered DIMM : HYMD512646CP8[J]
/S1
/S0
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D0
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D8
/S
DQS
D4
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
D12
D12
DQS5
DM5
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D1
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DQS2
DM2
/S
DQS
D5
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
D13
DQS6
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D2
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
DQS3
DM3
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D6
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
D14
DQS7
DM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDDSPD
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D3
DO-D15
VREF
DO-D15
VSS
DO-D15
VDDID
Strap:see Note 4
A0-A13
/S
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
Serial PD
SCL
BA0-BA1-> : SDRAMs D0-D15
A0-A13-> : SDRAMs D0-D15
CKE1
/RAS
CKE : SDRAMs D8-D15
/RAS : SDRAMs D0-D15
/CAS
/CAS : SDRAMs D0-D15
CKE0
CKE : SDRAMs D0-D7
/WE
/WE : SDRAMs D0-D15
Rev. 1.3 / Feb. 2006
DQS
DQS
D7
DQS
D15
SPD
VDD/VDDQ
BA0-BA1
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
SDA
WP
A0
A1
A2
SA0 SA1SA2
* Clock Wiring
Clock Input
SDRAMs
*CK0,/CK0
*CK1,/CK1
*CK2,/CK2
4 SDRAMs
6 SDRAMs
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Note :
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ,DQS,DM/DQS resistors : 22 Ohms ? 5%
4. VDDID strap connections (for memory device VDD, VDDQ) :
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD ≠ VDDQ
5. BAx, Ax, /RAS, /CAS, /WE resistors : 3 Ohms ? 5%
7
11
184pin Unbuffered DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB, 128M x 72 ECC Unbuffered DIMM : HYMD512726CP8[J]
/S1
/S0
DQS4
DM4
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D0
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D8
/S
DQS
D4
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
D12
D12
DQS5
DM5
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D1
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
/S
DQS
D5
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
D13
DQS6
DM6
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D2
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D6
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
D14
DQS7
DM7
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
/S
DQS
D3
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D11
DQS8
DM8
D7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0-BA1
A0-A13
CKE1
/RAS
/CAS
CKE0
/WE
Rev. 1.3 / Feb. 2006
/S
D8
DQS
DM
I/O0
I/O1
I/O6
I/O7
I/O2
I/O3
I/O4
I/O5
/S
D17
BA0-BA1-> : SDRAMs D0-D17
A0-A13-> : SDRAMs D0-D17
CKE : SDRAMs D8-D17
/RAS : SDRAMs D0-D17
/CAS : SDRAMs D0-D17
CKE : SDRAMs D0-D8
/WE : SDRAMs D0-D17
DQS
SCL
SDA
WP
A0
A1
A2
SA0 SA1 SA2
VDDSPD
VDD/
VDDQ
VREF
VSS
VDDID
DQS
D15
* Clock Wiring
Serial PD
DM
I/O7
I/O6
I/O1
I/O0
I/O5
I/O4
I/O3
I/O2
DQS
Clock Input
SDRAMs
*CK0,/CK0
6 SDRAMs
*CK1,/CK1
6 SDRAMs
*CK2,/CK2
6 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
Note :
1. DQ-to-I/O wiring is shown as
recommended
but may be changed.
SPD
2. DQ/DQS/DM/CKE/S relationships
must be maintained as shown.
DO-D17
3. DQ,DQS,DM/DQS resistors
: 22 Ohms ? 5%
DO-D17
4. VDDID strap connections
(for memory device VDD, VDDQ) :
DO-D17
STRAP OUT (OPEN) : VDD = VDDQ
Strap:see Note 4
STRAP IN (VSS) : VDD ≠ VDDQ
5. BAx, Ax, /RAS, /CAS, /WE
resistors : 3 Ohms ? 5%
8
11
184pin Unbuffered DDR SDRAM DIMMs
ABSOLUTE MAXIMUM RATINGS1
Parameter
Operating Temperature (Ambient)
Symbol
Rating
TA
0 ~ 70
Unit
o
C
Storage Temperature
TSTG
-55 ~ 150
o
Voltage on VDD relative to VSS
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ relative to VSS
VDDQ
-1.0 ~ 3.6
V
Voltage on inputs relative to Vss
VINPUT
-1.0 ~ 3.6
V
VIO
-0.5 ~3.6
V
Voltage on I/O pins relative to Vss
Output Short Circuit Current
Soldering Temperature ⋅ Time
IOS
50
TSOLDER
260 ⋅ 10
C
mA
o
C ⋅ Sec
Note:
1. Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage (DDR 200, 266, 333)
VDD
2.3
2.5
2.7
V
Power Supply Voltage (DDR 400)
VDD
2.5
2.6
2.7
V
Power Supply Voltage (DDR 200, 266, 333)
VDDQ
2.3
2.5
2.7
V
1
Power Supply Voltage (DDR 400)
VDDQ
2.5
2.6
2.7
V
1,2
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Reference Voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
VREF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
VIN(DC)
-0.3
-
VDDQ+0.3
V
Note
2
3
4
VID(DC)
0.36
-
VDDQ+0.6
V
VI(RATIO)
0.71
-
1.4
-
6
Input Leakage Current
ILI
-2
-
2
uA
7
Output Leakage Current
ILO
-5
-
5
uA
8
IOH
-16.8
-
-
mA
IOL
16.8
-
-
mA
IOH
-13.6
-
-
mA
IOL
13.6
-
-
mA
V-I Matching: Pullup to Pulldown Current Ratio
Output High Current
Normal Strength
(min VDDQ, min VREF, min VTT)
Output Driver
(VOUT=VTT ± 0.84) Output Low Current
(min VDDQ, max VREF, max VTT)
Half Strength Out- Output High Current
put Driver
(min VDDQ, min VREF, min VTT)
(VOUT=VTT ± 0.68) Output Low Current
(min VDDQ, max VREF, max VTT)
5
Note:
1. VDDQ must not exceed the level of VDD.
2. For DDR400, VDD=2.6V ± 0.1V, VDDQ=2.6V ± 0.1V
3. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to
peak noise on VREF may not exceed ± 2% of the DC value.
5. VID is the magnitude of the difference between the input level on CK and the input level on /CK.
6. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum
pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
7. VIN=0 to VDD, All other pins are not tested under VIN =0V.
8. DQs are disabled, VOUT=0 to VDDQ.
Rev. 1.3 / Feb. 2006
9
11
184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
256MB, 32M x 64 Unbuffered DIMM: HYMD532646CP6[J]
Symbol
Test Condition
Speed
Unit
DDR400B
DDR333
DDR266B
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
520
480
400
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control inputs
changing once per clock cycle
680
600
480
mA
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
40
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
140
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
180
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
240
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
840
760
680
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
920
840
720
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
1040
960
880
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Normal
20
mA
Low Power
12
mA
1440
1400
1360
Note
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
10
11
184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J]
Symbol
Speed
Test Condition
Unit
DDR400B
DDR333
DDR266B
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
1040
960
800
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control inputs
changing once per clock cycle
1360
1200
960
mA
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
80
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
280
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
360
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
480
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
1680
1520
1360
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
1840
1680
1440
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
2080
1920
1760
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Normal
40
mA
Low Power
24
mA
2880
2800
2720
Note
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
11
11
184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
512MB, 64M x 72 ECC Unbuffered DIMM: HYMD564726CP8[J]
Symbol
Speed
Test Condition
Unit
DDR400B
DDR333
DDR266B
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
1170
1080
900
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control inputs
changing once per clock cycle
1530
1350
1080
mA
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
90
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
315
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
405
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
540
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
1890
1710
1530
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
2070
1890
1620
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
2340
2160
1980
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Normal
45
mA
Low Power
27
mA
3240
3150
3060
Note
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
12
11
184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
1GB, 128M x 64 Unbuffered DIMM: HYMD512646CP8[J]
Symbol
Test Condition
Speed
Unit
DDR400B
DDR333
DDR266B
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice per
clock cycle; address and control inputs changing once per
clock cycle
1520
1440
1280
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control inputs
changing once per clock cycle
1840
1680
1440
mA
IDD2P
All banks idle; Power down mode; CKE=Low, tCK=tCK(min)
160
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
560
mA
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
720
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle
960
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); IOUT=0mA
2160
2000
1840
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs changing twice per
clock cycle
2320
2160
1920
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for
DDR266A & DDR266B at 133Mhz; distributed refresh
2560
2400
2240
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Normal
80
mA
Low Power
48
mA
3360
3280
3200
Note
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
13
11
184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
1GB, 128M x 72 ECC Unbuffered DIMM: HYMD512726CP8[J]
Symbol
Speed
Test Condition
Unit
DDR400B
DDR333
DDR266B
IDD0
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
1710
1620
1440
mA
IDD1
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
2070
1890
1620
mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
180
mA
IDD2F
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
630
mA
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
810
mA
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control inputs changing once per clock cycle
1080
mA
IDD4R
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
2430
2250
2070
mA
IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
2610
2430
2160
mA
IDD5
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
2880
2700
2520
mA
IDD6
CKE=<0.2V; External clock on; tCK
=tCK(min)
IDD7
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
Normal
90
mA
Low Power
54
mA
3780
3690
3600
Note
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 / Feb. 2006
14
11
184pin Unbuffered DDR SDRAM DIMMs
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Symbol
Min
Max
Unit
VIH(AC)
VREF + 0.31
-
V
Note
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
-
VREF - 0.31
V
Input Differential Voltage, CK and /CK inputs
VID(AC)
0.7
VDDQ + 0.6
V
1
Input Crossing Point Voltage, CK and /CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Note:
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Value
Unit
Reference Voltage
Parameter
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.31
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.31
V
Input Timing Measurement Reference Level Voltage
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
1
V/ns
Input minimum Signal Slew Rate
Termination Resistor (RT)
50
Ω
Series Resistor (RS)
25
Ω
Output Load Capacitance for Access Time Measurement (CL)
30
pF
OUTPUT LOAD CIRCUIT
VTT
RT=50Ω
Output
Zo=50Ω
VREF
CL=30pF
Rev. 1.3 / Feb. 2006
15
11
184pin Unbuffered DDR SDRAM DIMMs
CAPACITANCE (TA=25oC, f=100MHz)
256MB: HYMD532646CP6[J]
Input/Output Pins
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
CIN1
40
52
pF
/RAS, /CAS, /WE
CIN2
40
52
pF
CKE
CIN3
40
52
pF
/CS
CIN4
40
52
pF
CK0, /CK0, CK1, /CK1, CK2, /CK2
CIN5
22
32
pF
DM0 ~ DM7
CIN6
7
12
pF
DQ0 ~ DQ63, DQS0 ~ DQS7
CIO1
7
12
pF
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
CIN1
58
71
pF
/RAS, /CAS, /WE
CIN2
58
71
pF
CKE
CIN3
58
72
pF
/CS
CIN4
58
72
pF
CK0, /CK0, CK1, /CK1, CK2, /CK2
CIN5
25
40
pF
DM0 ~ DM7
CIN6
7
12
pF
DQ0 ~ DQ63, DQS0 ~ DQS7
CIO1
7
12
pF
512MB: HYMD564646CP8[J]
Input/Output Pins
512MB (with ECC): HYMD564726CP8[J]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/Output Pins
CIN1
60
75
pF
/RAS, /CAS, /WE
CIN2
60
75
pF
CKE
CIN3
60
75
pF
/CS
CIN4
60
75
pF
CK0, /CK0, CK1, /CK1, CK2, /CK2
CIN5
27
45
pF
DM0 ~ DM7
CIN6
7
12
pF
DQ0 ~ DQ63, DQS0 ~ DQS7
CIO1
7
12
pF
CB0 ~ CB7
CIO2
7
12
pF
1GB: HYMD512646CP8[J]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/Output Pins
CIN1
90
104
pF
/RAS, /CAS, /WE
CIN2
90
104
pF
CKE0, CKE1
CIN3
58
72
pF
/CS0, /CS1
CIN4
58
72
pF
CK0, /CK0, CK1, /CK1, CK2, /CK2
CIN5
30
45
pF
DM0 ~ DM7
CIN6
12
18
pF
DQ0 ~ DQ63, DQS0 ~ DQS7
CIO1
12
18
pF
Rev. 1.3 / Feb. 2006
16
11
184pin Unbuffered DDR SDRAM DIMMs
CAPACITANCE (TA=25oC, f=100MHz)
1GB (with ECC): HYMD512726CP8[J]
Symbol
Min
Max
Unit
A0 ~ A12, BA0, BA1
Input/Output Pins
CIN1
95
110
pF
/RAS, /CAS, /WE
CIN2
95
110
pF
CKE0, CKE1
CIN3
60
80
pF
/CS0,/CS1
CIN4
60
80
pF
CK0, /CK0, CK1, /CK1, CK2, /CK2
CIN5
32
45
pF
DM0 ~ DM7
CIN6
12
18
pF
DQ0 ~ DQ63, DQS0 ~ DQS7
CIO1
12
18
pF
CB0 ~ CB7
CIO2
12
18
pF
Rev. 1.3 / Feb. 2006
17
11
184pin Unbuffered DDR SDRAM DIMMs
AC CHARACTERISTICS (note: 1 - 9 / AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400B
DDR333
DDR266A
DDR266B
DDR200
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
UNIT
Row Cycle Time
tRC
55
-
60
-
65
-
65
-
70
-
ns
Auto Refresh Row
Cycle Time
tRFC
70
-
72
-
75
-
75
-
80
-
ns
Row Active Time
tRAS
40
70K
42
70K
45
120K
45
120K
50
120K
ns
tRAP
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
tRCD or
tRASmin
-
ns
Row Address to
Column Address Delay
tRCD
15
-
18
-
20
-
20
-
20
-
ns
Row Active to Row
Active Delay
tRRD
10
-
12
-
15
-
15
-
15
-
ns
Column Address to
Column Address Delay
tCCD
1
-
1
-
1
-
1
-
1
-
tCK
Row Precharge Time
tRP
15
-
18
-
20
-
20
-
20
-
ns
Write Recovery Time
tWR
15
-
15
-
15
-
15
-
15
-
ns
Internal Write to Read
Command Delay
tWTR
2
-
1
-
1
-
1
-
1
-
tCK
tDAL
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
(tWR/
tCK)
+
(tRP/tCK)
-
tCK
5
10
-
-
-
-
-
-
-
-
-
-
6
12
7.5
12
7.5
12
8.0
12
ns
-
-
7.5
12
7.5
12
10
12
10
12
ns
Active to Read with
Auto Precharge Delay
Auto Precharge Write
Recovery + Precharge
Time22
CL = 3
System
Clock Cycle CL = 2.5
Time24
CL = 2
tCK
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Data-Out edge to Clock
edge Skew
tAC
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
-0.55
0.55
-0.6
0.6
-0.75
0.75
-0.75
0.75
-0.75
0.75
ns
tDQSQ
-
0.4
-
0.45
-
0.5
-
0.5
-
0.6
ns
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
tQHS
-
0.5
-
0.55
-
0.75
-
0.75
-
0.75
ns
DQS-Out edge to Clock
tDQSCK
edge Skew
DQS-Out edge to DataOut edge Skew21
Data-Out hold time
from DQS20
Clock Half Period19,20
Data Hold Skew
Factor20
Valid Data Output
Window
Rev. 1.3 / Feb. 2006
tDV
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
ns
18
11
184pin Unbuffered DDR SDRAM DIMMs
- Continue
Parameter
Symbol
DDR400B
DDR333
DDR266A
DDR266B
DDR200
UNIT
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tHZ
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
tLZ
-0.7
0.7
-0.7
0.7
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
tIS
0.6
-
0.75
-
0.9
-
0.9
-
1.1
-
ns
tIH
0.6
-
0.75
-
0.9
-
0.9
-
1.1
-
ns
tIS
0.7
-
0.8
-
1.0
-
1.0
-
1.1
-
ns
tIH
0.7
-
0.8
-
1.0
-
1.0
-
1.1
-
ns
tIPW
2.2
-
2.2
-
2.2
-
2.2
-
2.5
-
ns
Write DQS High Level Width
tDQSH
0.35
-
0.35
-
0.35
-
0.35
-
0.35
-
tCK
Write DQS Low Level Width
tDQSL
0.35
-
0.35
-
0.35
-
0.35
-
0.35
-
tCK
Clock to First Rising edge of DQSIn
tDQSS
0.72
1.25
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
DQS falling edge hold time from
CK
tDSH
0.2
-
0.2
-
0.2
-
0.2
-
0.2
-
tCK
DQ & DM input setup time25
tDS
0.4
-
0.45
-
0.5
-
0.5
-
0.6
-
ns
DQ & DM input hold time25
tDH
0.4
-
0.45
-
0.5
-
0.5
-
0.6
-
ns
DQ & DM Input Pulse Width17
tDIPW
1.75
-
1.75
-
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
0
-
0
-
0
-
0
-
0
-
ns
-
0.25
-
0.25
-
0.25
-
0.25
-
tCK
Data-out high-impedance window
from CK,/CK10
Data-out low-impedance window
from CK, /CK10
Input Setup Time (fast slew
rate)14,16-18
Input Hold Time (fast slew
rate)14,16-18
Input Setup Time (slow slew
rate)15-18
Input Hold Time (slow slew
rate)15-18
Input Pulse Width17
Write DQS Preamble Setup Time12 tWPRES
Write DQS Preamble Hold Time
tWPREH 0.25
Write DQS Postamble Time11
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
2
-
2
-
tCK
tXSNR
75
-
75
-
75
-
75
-
80
-
ns
tXSRD
200
-
200
-
200
-
200
-
200
-
tCK
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
-
7.8
us
Exit Self Refresh to non-Read
command23
Exit Self Refresh to Read
command
Average Periodic Refresh
Interval13,25
Rev. 1.3 / Feb. 2006
19
11
184pin Unbuffered DDR SDRAM DIMMs
Note:
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to
be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
Output
(VOUT)
50 Ω
30 pF
Figure: Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIHswing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK, /CK), and parameter specifications are guaranteed for the specified ac input levels under
normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the
dc input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.2VDDQ is
recognized as LOW.
7. The CK, /CK input reference level (for timing referenced to CK, /CK) is the point at which CK and /CK cross; the input reference
level for signals other than CK, /CK is VREF.
8. The output timing reference voltage level is VTT.
9. Operation or timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
11. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
12. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
13. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
14. For command/address input slew rate ≥ 1.0 V/ns.
15. For command/address input slew rate ≥ 0.5 V/ns and ＜ 1.0 V/ns
16. For CK & /CK slew rate ≥ 1.0 V/ns (single-ended)
17. These parameters guarantee device timing, but they are not necessarily tested on each device.
They may be guaranteed by device design or tester correlation.
18. Slew Rate is measured between VOH(ac) and VOL(ac).
19. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half
period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
Rev. 1.3 / Feb. 2006
20
11
184pin Unbuffered DDR SDRAM DIMMs
20.tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push--out of DQS on one transition followed by the
worst case pull--in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects,
and p-channel to n-channel variation of the output drivers.
21. tDQSQ:
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
22. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For DDR266B at CL=2.5 and tCK=7.5 ns
tDAL = ((15 ns / 7.5 ns) + (20 ns / 7.5 ns)) clocks
= ((2) + (3)) clocks
= 5 clocks
23. In all circumstances, tXSNR can be satisfied using
tXSNR = tRFCmin + 1*tCK
24. The only time that the clock frequency is allowed to change is during self-refresh mode.
25. If refresh timing or tDS/tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid
READ can be executed.
Rev. 1.3 / Feb. 2006
21
11
184pin Unbuffered DDR SDRAM DIMMs
SYSTEM CHARACTERISTICS CONDITIONS for DDR SDRAMS
The following tables are described specification parameters that required in systems using DDR devices to ensure
proper performannce. These characteristics are for system simulation purposes and are guaranteed by design.
Input Slew Rate for DQ/DM/DQS
AC CHARACTERISTICS
(Table a.)
DDR400
DDR333
DDR266
DDR200
PARAMETER
Symbol
min
max
min
max
min
max
min
max
DQ/DM/DQS input slew rate
measured between VIH(DC),
VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
0.5
4.0
0.5
4.0
0.5
4.0
0.5
4.0
UNIT
Note
V/ns
1,12
Address & Control Input Setup & Hold Time Derating (Table b.)
Input Slew Rate
Delta tIS
Delta tIH
UNIT
Note
0.5 V/ns
0
0
ps
9
0.4 V/ns
+50
0
ps
9
0.3 V/ns
+100
0
ps
9
DQ & DM Input Setup & Hold Time Derating
(Table c.)
Input Slew Rate
Delta tDS
Delta tDH
UNIT
Note
0.5 V/ns
0
0
ps
11
0.4 V/ns
+75
0
ps
11
0.3 V/ns
+150
0
ps
11
DQ & DM Input Setup & Hold Time Derating for Rise/Fall Delta Slew Rate
(Table d.)
Input Slew Rate
Delta tDS
Delta tDH
UNIT
Note
± 0.0 ns/V
0
0
ps
10
± 0.25 ns/V
+50
+50
ps
10
± 0.5 ns/V
+100
+100
ps
10
Output Slew Rate Characteristics (for x4, x8 Devices)
(Table e.)
Slew Rate Characteristic
Typical Range (V/
ns)
Minimum (V/ns)
Maximum (V/ns)
Note
Pullup Slew Rate
1.2 - 2.5
1.0
4.5
1,3,4,6,7,8
Pulldown Slew Rate
1.2 - 2.5
1.0
4.5
2,3,4,6,7,8
Output Slew Rate Characteristics (for x16 Device) (Table f.)
Slew Rate Characteristic
Typical Range (V/
ns)
Minimum (V/ns)
Maximum (V/ns)
Note
Pullup Slew Rate
1.2 - 2.5
1.0
4.5
1,3,4,6,7,8
Pulldown Slew Rate
1.2 - 2.5
1.0
4.5
2,3,4,6,7,8
Output Slew Rate Matching Ratio Characteristics
Slew Rate Characteristic
Parameter
Output Slew Rate Matching Ratio
(Pullup to Pulldown)
Rev. 1.3 / Feb. 2006
DDR266A
(Table g.)
DDR266B
DDR200
min
max
min
max
min
max
-
-
-
-
0.71
1.4
Note
5,12
22
11
184pin Unbuffered DDR SDRAM DIMMs
Note:
1. Pullup slew rate is characterized under the test conditions as shown in below Figure.
Test Point
Output
(VOUT)
50
Ω
VSSQ
Figure: Pullup Slew rate
2. Pulldown slew rate is measured under the test conditions shown in below Figure.
VDDQ
Output
(VOUT)
50Ω
Test Point
Figure: Pulldown Slew rate
3. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250mV)
Pulldown slew rate is measured between (VDDQ/2 + 320mV ± 250mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example: For typical slew, DQ0 is switching
For minimum slew rate, all DQ bits are switching worst case pattern
For maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
4. Evaluation conditions
Typical: 25 oC (Ambient), VDDQ = nominal, typical process
Minimum: 70 oC (Ambient), VDDQ = minimum, slow-slow process
Maximum: 0 oC (Ambient), VDDQ = Maximum, fast-fast process
5. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature
and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process
variation.
6. Verified under typical conditions for qualification purposes.
7. TSOP-II package devices only.
8. Only intended for operation up to 256 Mbps per pin.
9. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns as shown in Table b.
The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
10. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables c
& d. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on
the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The
delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(slew Rate2)}
For example:
If Slew Rate 1 is 0.5 V/ns and Slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is -0.5 ns/V. Using the table given, this would
result in the need for an increase in tDS and tDH of 100ps.
11. Table c is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the
lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by
either VIH(ac) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions.
12. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
Rev. 1.3 / Feb. 2006
23
11
184pin Unbuffered DDR SDRAM DIMMs
SIMPLIFIED COMMAND TRUTH TABLE
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
Extended Mode Register Set
Command
H
X
L
L
L
L
OP code
1,2
Mode Register Set
H
X
L
L
L
L
OP code
1,2
H
X
X
1
H
X
Device Deselect
No Operation
Bank Active
Read
Read with Autoprecharge
Write
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Read Burst Stop
Auto Refresh
Entry
Self Refresh
Precharge Power
Down Mode
Active Power Down
Mode
H
X
H
X
X
X
L
H
H
H
L
L
H
H
L
H
L
H
ADDR
A10/AP
RA
CA
BA
V
L
H
L
V
1
1
1,3
1
H
X
L
H
L
L
CA
H
X
L
L
H
L
X
H
X
L
H
H
L
X
1
H
H
L
L
L
H
X
1
H
L
L
L
L
H
H
X
X
X
L
H
H
H
Exit
L
H
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
H
V
Note
H
X
L
V
1,4
1,5
1
1
X
1
H
X
X
X
1
L
H
H
H
1
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
1
1
1
X
1
X
1
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Note :
1. DM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time(tWR) is needed to guarantee that the last data has been
completely written.
5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
WRITE MASK TRUTH TABLE
CKEn-1
CKEn
/CS, /RAS, /CAS, /WE
DM
Data Write
Function
H
X
X
L
ADDR
A10/AP
X
BA
Note
1
Data-In Mask
H
X
X
H
X
1
Note:
1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data.
In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
Rev. 1.3 / Feb. 2006
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184pin Unbuffered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
256MB, 32M x 64 Unbuffered DIMM: HYMD532646CP6[J]
Front
133.35
131.35
(2X)4.00
128.95
64.77
B
49.53
17.80
A
ℵ2.50+/-0.10
2.30
10.0
31.75
Back
Side
3.18 Max
(Front)
4.00
min
1.27+/-0.10
Full-R
0.99+/-0.05
6.35
1.27
3.80
2.50+/-0.20
0.20+/-0.15
1.80+/-0.10
3.075
Detail A
Detail B
Note) All dimensions are typical millimeter scale and tolerance is +/-0.127 mm
unless otherwise stated
Rev. 1.3 / Feb. 2006
25
11
184pin Unbuffered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64M x 64 Unbuffered DIMM: HYMD564646CP8[J]
Front
133.35
131.35
(2X)4.00
128.95
64.77
B
49.53
17.80
A
8 2.50+/-0.10
2.30
10.0
31.75
Back
Side
3.18 Max
(Front)
4.00
min
1.27+/-0.10
Full-R
0.99+/-0.05
6.35
1.27
3.80
2.50+/-0.20
0.20+/-0.15
1.80+/-0.10
3.075
Detail A
Detail B
Note) All dimensions are typical millimeter scale and tolerance is +/-0.127 mm
unless otherwise stated
Rev. 1.3 / Feb. 2006
26
11
184pin Unbuffered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
512MB, 64M x 72 ECC Unbuffered DIMM: HYMD564726CP8[J]
Front
133.35
131.35
(2X)4.00
128.95
2.50+/-0.10
B
2.30
A
64.77
49.53
17.80
10.0
31.75
Back
Side
3.18 Max
(Front)
4.00
min
1.27+/-0.10
Full-R
0.99+/-0.05
6.35
1.27
3.80
2.50+/-0.20
0.20+/-0.15
1.80+/-0.10
3.075
Detail A
Detail B
Note) All dimensions are typical millimeter scale and tolerance is +/-0.127 mm
unless otherwise stated
Rev. 1.3 / Feb. 2006
27
11
184pin Unbuffered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
1GB, 128M x 64 Unbuffered DIMM : HYMD512646CP8[J]
Front
133.35
131.35
(2X)4.00
128.95
2.50+/-0.10
B
49.53
17.80
A
64.77
2.30
10.0
31.75
Back
Side
4.00
(Front)
4.00
min
1.27+/-0.10
Full-R
0.99+/-0.05
6.35
1.27
3.80
2.50+/-0.20
0.20+/-0.15
1.80+/-0.10
3.075
Detail A
Detail B
Note) All dimensions are typical millimeter scale and tolerance is +/-0.127 mm
unless otherwise stated
Rev. 1.3 / Feb. 2006
28
11
184pin Unbuffered DDR SDRAM DIMMs
PACKAGE DIMENSIONS
1GB, 128M x 72 ECC Unbuffered DIMM: HYMD512726CP8[J]
Front
133.35
131.35
(2X)4.00
128.95
π 2.50+/-0.10
B
49.53
17.80
A
64.77
2.30
10.0
31.75
Back
Side
4.00
(Front)
4.00
min
1.27+/-0.10
Full-R
0.99+/-0.05
6.35
1.27
3.80
2.50+/-0.20
0.20+/-0.15
1.80+/-0.10
3.075
Detail A
Detail B
Note) All dimensions are typical millimeter scale and tolerance is +/-0.127 mm
unless otherwise stated
Rev. 1.3 / Feb. 2006
29
11
184pin Unbuffered DDR SDRAM DIMMs
REVISION HISTORY
Revision
History
Date
1.0
First Version Release
Mar. 2005
1.1
Leaded products removed
IDD specification revised
July 2005
1.2
1.3
Correct editorial errors on Functional Block Diagram
Add more description on Package Dimensions
Aug. 2005
Correct editorial errors on SDRAM organization at page 1,2
Nov. 2005
IDD6 specification revised
Feb. 2006
Rev. 1.3 / Feb. 2006
Remark
30