HYMD116M6458-H/L 16Mx64 Unbuffered DDR SO-DIMM PRELIMINARY DESCRIPTION Hynix HYMD116M6458-H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual InLine Memory Modules (SO-DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD116M6458-H/L series consists of eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate. Hynix HYMD116M6458-H/L series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD116M6458-H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD116M6458-H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • 128MB (16M x 64) Unbuffered DDR SO-DIMM based on 16Mx8 DDR SDRAM • Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock • JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) • Data inputs on DQS centers when write (centered DQ) • 2.5V +/- 0.2V VDD and VDDQ Power supply • • All inputs and outputs are compatible with SSTL_2 interface Data strobes synchronized with output data for read and input data for write • Programmable CAS Latency 2 / 2.5 supported • Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • 4096 refresh cycles / 64ms ORDERING INFORMATION Part No. HYMD116M6458-H HYMD116M6458-L Power Suppy Clock Frequency Organization Interface Package VDD=2.5V VDDQ=2.5V 133MHz (*DDR266B) 4Banks x 2Mbit x 16 SSTL_2 400mil 66pin TSOP II 100MHz (*DDR200) * JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.0.1 / Apr.01 HYMD116M6458-H/L PIN DESCRIPTION Pin Pin Description Pin Pin Description CK0, /CK0, CK1, /CK1 Differential Clock Inputs VDDQ DQs Power Supply CS0, CS1 Chip Select Input VSS Ground CKE0, CKE1 Clock Enable Input VREF Reference Power Supply /RAS, /CAS, /WE Commend Sets Inputs VDDSPD Power Supply for SPD A0 ~ A11 Address SA0~SA2 E2PROM Address Inputs BA0, BA1 Bank Address SCL E2PROM Clock DQ0~DQ63 Data Inputs/Outputs SDA E2PROM Data I/O DQS0~DQS7 Data Strobe Inputs/Outputs VDDID VDD Identification Flag DM0~DM7 Data-in Mask DU Do not Use VDD Power Supply NC No Connection PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 2 VREF 51 VSS 52 VSS 101 A9 102 A8 151 DQ42 152 DQ46 3 VSS 4 VSS 53 DQ19 54 DQ23 103 VSS 104 VSS 153 DQ43 154 DQ47 5 DQ0 6 DQ4 55 DQ24 56 DQ28 105 A7 106 A6 155 VDD 156 VDD 7 DQ1 8 DQ5 57 VDD 58 VDD 107 A5 108 A4 157 VDD 158 /CK1 CK1 9 VDD 10 VDD 59 DQ25 60 DQ29 109 A3 110 A2 159 VSS 160 11 DQS0 12 DM0 61 DQS3 62 DM3 111 A1 112 A0 161 VSS 162 VSS 13 DQ2 14 DQ6 63 VSS 64 VSS 113 VDD 114 VDD 163 DQ48 164 DQ52 15 VSS 16 VSS 65 DQ26 66 DQ30 115 A10/AP 116 BA1 165 DQ49 166 DQ53 17 DQ3 18 DQ7 67 DQ27 68 DQ31 117 BA0 118 /RAS 167 VDD 168 VDD 19 DQ8 20 DQ12 69 VDD 70 VDD 119 /WE 120 /CAS 169 DQS6 170 DM6 21 VDD 22 VDD 71 NC 72 NC 121 /CS0 122 /CS1 171 DQ50 172 DQ54 23 DQ9 24 DQ13 73 NC 74 NC 123 DU 124 DU 173 VSS 174 VSS 25 DQS1 26 DM1 75 VSS 76 VSS 125 VSS 126 VSS 175 DQ51 176 DQ55 27 VSS 28 VSS 77 NC 78 NC 127 DQ32 128 DQ36 177 DQ56 178 DQ60 29 DQ10 30 DQ14 79 NC 80 NC 129 DQ33 130 DQ37 179 VDD 180 VDD 31 DQ11 32 DQ15 81 VDD 82 VDD 131 VDD 132 VDD 181 DQ57 182 DQ61 33 VDD 34 VDD 83 NC 84 NC 133 DQS4 134 DM4 183 DQS7 184 DM7 35 CK0 36 VDD 85 DU 86 DU 135 DQ34 136 DQ38 185 VSS 186 VSS 37 /CK0 38 VSS 87 VSS 88 VSS 137 VSS 138 VSS 187 DQ58 188 DQ62 39 VSS 40 VSS 89 NC 90 VSS 139 DQ35 140 DQ39 189 DQ59 190 DQ63 41 DQ16 42 DQ20 91 NC 92 VDD 141 DQ40 142 DQ44 191 VDD 192 VDD 43 DQ17 44 DQ21 93 VDD 94 VDD 143 VDD 144 VDD 193 SDA 194 SA0 45 VDD 46 VDD 95 CKE1 96 CKE0 145 DQ41 146 DQ45 195 SCL 196 SA1 47 DQS2 48 DM2 97 NC 98 DU 147 DQS5 148 DM5 197 VDDSPD 198 SA2 49 DQ18 50 DQ22 99 NC 100 A11 149 VSS 150 VSS 199 VDDID 200 DU Rev.0.1 / Apr.01 2 HYMD116M6458-H/L FUNCTIONAL BLOCK DIAGRAM . /CS0 DQS0 DM0 DQS4 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS /CS D0 DQS1 DM1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D4 DQS5 DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS /CS D1 DQS2 DM2 /CS DQS D5 DQS6 DM6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS /CS D2 DQS3 DM3 /CS DQS D6 DQS7 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /CS DQS D3 Serial PD VDDSPD SCL SDA WP A0 A1 SA0 SA1 A2 SA2 VDD/VDDQ VREF VSS VDDID BA0-BA1 A0 - A11 /RAS /CAS Rev.0.1 / Apr.01 CS BA0-BA1 : SDRAMs D0 - D7 A0 - A11 : SDRAMs D0 - D7 /RAS : SDRAMs D0 - D7 /CAS : SDRAMs D0 - D7 CKE0 CKE : SDRAMs D0 - D7 /WE /WE : SDRAMs D0 - D7 . /CS DQS D7 . = = . . . . =. .. SPD D0 - D7 D0 - D7 D0 - D7 Strap:see Note 4 Notes: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VDDID strap connections (for memory device VDD, VDDQ) : Strap out :(open) : VDD=VDDQ Strap In (Vss) : VDD= VDDQ 3 HYMD116M6458-H/L ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 oC Storage Temperature TSTG -55 ~ 125 o Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V Output Short Circuit Current IOS 50 mA Power Dissipation PD 8 W Soldering Temperature / Time TSOLDER 260 / 10 o C C / Sec Note : Operation at above absolute maximum rating can adversely affect device reliability DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS=0V) Parameter Symbol Min Typ. Max Unit Power Supply Voltage VDD 2.3 2.5 2.7 V Power Supply Voltage VDDQ 2.3 2.5 2.7 V Input High Voltage VIH VREF + 0.15 - VDDQ + 0.3 V Input Low Voltage VIL -0.3 - VREF - 0.15 V Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V Reference Voltage VREF 1.15 1.25 1.35 V Note 1 2 3 Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. The value of VREF is approximately equal to 0.5VDDQ. AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS=0V) Parameter Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) Input Differential Voltage, CK and /CK inputs VID(AC) Input Crossing Point Voltage, CK and /CK inputs VIX(AC) Max Unit Note V VREF - 0.31 V 0.7 VDDQ + 0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. Rev.0.1 / Apr.01 4 HYMD116M6458-H/L AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS=0V) Parameter Value Unit Reference Voltage VDDQ x 0.5 V Termination Voltage VDDQ x 0.5 V AC Input High Level Voltage (VIH, min) VREF + 0.31 V AC Input Low Level Voltage (VIL, max) VREF - 0.31 V Input Timing Measurement Reference Level Voltage VREF V Output Timing Measurement Reference Level Voltage VTT V Input Signal maximum peak swing 1.5 V Input minimum Signal Slew Rate 1 V/ns Termination Resistor (RT) 50 Ω Series Resistor (RS) 25 Ω Output Load Capacitance for Access Time Measurement (CL) 30 pF Rev.0.1 / Apr.01 5 HYMD116M6458-H/L CAPACITANCE (TA=25oC, f=100MHz ) Parameter Pin Symbol Min Max Unit Input Capacitance A0 ~ A11, BA0, BA1 CIN1 TBD TBD pF Input Capacitance RAS, CAS, WE CIN2 TBD TBD pF Input Capacitance CKE0, CKE1 CIN3 TBD TBD pF Input Capacitance /CS0, /CS1 CIN4 TBD TBD pF Input Capacitance CK0, CK0, CK1, CK1 CIN5 TBD TBD pF Input Capacitance DM0 ~ DM7 CIN6 TBD TBD pF Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS7 CIO1 TBD TBD pF Note : 1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT VTT VTT RT=50Ω RT=50Ω Output RS=25Ω Zo=50Ω VREF CL=30pF Rev.0.1 / Apr.01 6 HYMD116M6458-H/L DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS=0V) Parameter Symbol Min. Max Unit Note Input Leakage Current ILI -5 5 uA 1 Output Leakage Current ILO -5 5 uA 2 Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA Output Low Voltage VOL - VTT - 0.76 V IOL = +15.2mA Note : 1. VIN=0 to 3.6V, All other pins are not tested under VIN=0V 2. DOUT is disabled, VOUT=0 to 2.7V 3. These values are device characteristics. DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS=0V) Parameter Symbol Test Condition Operating Current Speed Unit -H -L IDD0 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle TBD TBD mA Operating Current IDD1 One bank; Active - Read - Precharge; Burst Length=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle TBD TBD mA Precharge Power Down Standby Current IDD2P All banks idle; Power down - mode ; CKE=Low, tCK=tCK(min) Idle Standby Current IDD2F CS=High, All banks idle; tCK=tCK(min); CKE=High ; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM Active Power Down Standby Current IDD3P One bank active; Power down mode; CKE=Low, tCK=tCK(min) 200 mA IDD3N /CS=HIGH; CKE=HIGH; One bank; Active-Precharge; tRC=tRAS(max); tCK=tCK(mic); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle 400 mA Active Standby Current Rev.0.1 / Apr.01 160 320 Note mA 280 mA 7 HYMD116M6458-H/L DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS=0V) Parameter Symbol Test Condition Operating Current IDD4R Operating Current -Continued Speed -H -L Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA TBD TBD IDD4W Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle TBD TBD Auto Refresh Current IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh TBD TBD Self Refresh Current IDD6 CKE =< 0.2V; External clock on; tCK=tCK(min) Operating Current - Four Bank Operation IDD7 Four bank interleaving with BL=4 -Refer to the following page for detailed test condition Rev.0.1 / Apr.01 Unit Note mA Normal 16 mA Low Power 8 mA TBD mA 8 HYMD116M6458-H/L AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol -H(DDR266B) -L(DDR200) Min Max Min Max Unit Row Cycle Time tRC 65 - 70 - ns Auto Refresh Row Cycle Time tRFC 75 - 80 - ns Row Active Time tRAS 45 120K 50 120K ns Active to Read with Auto Precharge Delay tRAP tRASBL/2 x tCK - tRASBL/2 x tck - ns Row Address to Column Address Delay tRCD 20 - 20 - ns Row Active to Row Active Delay tRRD 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - CK tRP 20 - 20 - ns Last Data-In to Precharge Time (Write Recovery Time) tDPL 15 - 20 - ns Last Data-In to Read Command tDRL 1 - 1 - CK Auto Precharge Write Recovery + Precharge Time tDAL 5 - 4 - CK 7.5 15 10 15 ns 10 15 10 15 ns Row Precharge Time System Clock Cycle Time CL = 2.5 CL = 2 tCK Note 16 15 Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Data-Out edge Skew tDQSQ - 0.5 - 0.6 ns Data-Out hold time from DQS tQH tHPmin -tQHS - tHPmin -tQHS - ns 1, 10 Clock Half Period tHP tCH/L min - tCH/L min - ns 1,9 Data Hold Skew Factor tQHS - 0.75 - 1 ns 10 Valid Data Output Window tDV Data-out high-impedance window from CK, /CK tHZ -1.2 0.8 ns Data-out low-impedance window from CK, /CK tLZ -1.2 0.8 ns Input Setup Time (fast slew rate) tIS 0.9 - 1.2 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.9 - 1.2 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 1.0 - 1.2 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 1.0 - 1.2 - ns 2,4,5,6 tIPW 2.2 ns 6 Input Pulse Width Rev.0.1 / Apr.01 tQH-tDQSQ tQH-tDQSQ - ns 9 HYMD116M6458-H/L AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol -H(DDR266B) - continued -L(DDR200) Min Max Min Max Unit Note Write DQS High Level Width tDQSH 0.35 - 0.35 - CK Write DQS Low Level Width tDQSL 0.35 - 0.35 - CK Clock to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 CK Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 - 0.6 - ns 6,7, 11~13 Data-in Hold Time to DQS-In (DQ & DM) tDH 0.5 - 0.6 - ns 6,7, 11~13 DQ & DM Input Pulse Width tDIPW 1.75 - 2 - ns Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 CK Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 CK Write DQS Preamble Setup Time tWPRES 0 - 0 - CK Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - CK Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 CK Mode Register Set Delay tMRD 2 - 2 - CK Exit Self Refresh to Any Execute Command tXSC 200 - 200 - CK Average Periodic Refresh Interval tREFI - 15.6 - 15.6 us 8 Note : 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE. 3. For command/address input slew rate >=1.0V/ns 4. For command/address input slew rate >=0.5V/ns and <1.0V/ns This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate Delta tIS Delta tIH V/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 5. CK, /CK slew rates are >=1.0V/ns 6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. 7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. 9. Min(tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. Rev.0.1 / Apr.01 10 HYMD116M6458-H/L 11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate Delta tDS Delta tDH V/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level Delta tDS Delta tDH mV ps ps +280 +50 +50 13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate1=0.5V/ns and Slew Rate2=0.4V/n then the Delta Inverse Slew Rate=-0.5ns/V. (1/SlewRate1)-(1/SlewRate2) Delta tDS Delta tDH ns/V ps ps 0 0 0 +/-0.25 +50 +50 +/- 0.5 +100 +100 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. 15. tDAL=(tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK=7.5 ns, tDAL=(15 ns / 7.5 ns) + (20 ns / 7.5 ns)=(2.00) + (2.67) Round up each non-integer to the next highest integer:=(2) + (3), tDAL=5 clock 16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS BL/2 x tCK. Rev.0.1 / Apr.01 11 HYMD116M6458-H/L SIMPLIFIED COMMAND TRUTH TABLE A10/ AP Command CKEn-1 CKEn CS RAS CAS WE Extended Mode Register Set H X L L L L OP code 1,2 Mode Register Set H X L L L L OP code 1,2 H X H X X X L H H H X 1 H X L L H H H X L H L H CA H X L H L L CA H X L L H L X Read Burst Stop H X L H H L X 1 Auto Refresh H H L L L H X 1 Entry H L L L L H Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H 1 H X X X 1 L V V V Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh Precharge Power Down Mode Active Power Down Mode (Clock Suspend) Exit L H Entry H L Exit L H X ADDR RA BA V L H L H V V Note 1 1 1,3 1 1,4 H X 1,5 L V 1 1 X 1 1 X X 1 1 1 1 ( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev.0.1 / Apr.01 12 HYMD116M6458-H/L MODULE DIMENSIONS Front 67.60 mm 31.75 mm 20.00 mm 1 39 41 199 Back 2.0 mm Side 2.0 mm 1 39 41 199 3.8mm MAX. (Front) Rev.0.1 / Apr.01 13