AS4C1M16F5 ® 5V 1M×16 CMOS DRAM (fast-page mode) Features • Organization: 1,048,576 words × 16 bits • High speed - 50/60 ns RAS access time - 20/25 ns fast page cycle time - 13/17 ns CAS access time • Low power consumption - Active: 880 mW max (AS4C1M16E0-60) - Standby: 11 mW max, CMOS DQ • Fast page mode • 1024 refresh cycles, 16 ms refresh interval - RAS-only or CAS-before-RAS refresh • Read-modify-write • TTL-compatible, three-state DQ • JEDEC standard package and pinout - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP II • 5V power supply • Industrial and commercial temperature available Pin arrangement Pin designation TSOP II SOJ Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC NC NC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC WE RAS NC NC A0 A1 A2 A3 VCC LCAS UCAS OE Pin(s) Description A0 to A9 Address inputs RAS Row address strobe DQ1 to DQ16 Input/output OE Output enable WE Write enable UCAS Column address strobe, upper byte LCAS Column address strobe, lower byte VCC Power VSS Ground A9 A8 A7 A6 A5 A4 VSS Selection guide Symbol AS4C1M16F5-50 AS4C1M16F5-60 Unit Maximum RAS access time tRAC 50 60 ns Maximum column address access time tAA 25 30 ns Maximum CAS access time tCAC 13 17 ns Maximum output enable (OE) access time tOEA 13 15 ns Minimum read or write cycle time tRC 84 104 ns Minimum fast page mode cycle time tPC 20 25 ns Maximum operating current ICC1 170 160 mA Maximum CMOS standby current ICC5 2.0 2.0 mA 4/11/01; v.0.9.1 Alliance Semiconductor P. 1 of 21 Copyright © Alliance Semiconductor. All rights reserved. AS4C1M16F5 ® Functional description The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia and router switch applications. The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access. Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using: • RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence. • Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data. • CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). • Normal read or write cycles refresh the row being accessed. The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates with a single power supply of 5V ± 0.5V. The device provides TTL compatible inputs and outputs. Refresh controller Logic block diagram GND UCAS RAS clock generator CAS clock generator LCAS WE WE clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 Address buffers RAS Column decoder Sense amp Data DQ buffers DQ1 to DQ16 OE Row decoder VCC 1024 × 1024 × 16 Array (16,777,216) Substrate bias generator Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature AS4C1M16F5 AS4C1M16F5 Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V VIH 2.4 – VCC V –0.5 – 0.8 V 0 – 70 -40 – 85 VIL Commercial Industrial TA † °C † VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. 4/11/01; v.0.9.1 Alliance Semiconductor P. 2 of 21 AS4C1M16F5 ® Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage Vin -1.0 +7.0 V Input voltage (DQs) VDQ -1.0 VCC + 0.5 V Power supply voltage VCC -1.0 +7.0 V Storage temperature (plastic) TSTG -55 +150 °C Soldering temperature × time TSOLDER – 260 × 10 o Power dissipation PD – 1 W Short circuit output current Iout – 50 mA C × sec DC electrical characteristics -50 Parameter Symbol Test conditions Input leakage current IIL Output leakage current -60 Min Max Min Max Unit 0V ≤ Vin ≤ +5.5V, Pins not under test = 0V -5 +5 -5 +5 µA IOL DOUT disabled, 0V ≤ Vout ≤ +5.5V -5 +5 -5 +5 µA Operating power supply current ICC1 RAS, UCAS, LCAS, Address cycling; tRC=min – 170 – 160 mA TTL standby power supply current ICC2 RAS = UCAS = LCAS ≥ VIH – 2.5 – 2.5 mA Average power supply current, RAS refresh mode ICC3 or CBR RAS cycling, UCAS = LCAS ≥ VIH, tRC = min of RAS low after XCAS low. – 170 – 160 mA 1 Fast page mode average power supply current ICC4 RAS = VIL, UCAS or LCAS, address cycling: tPC = min – 120 – 110 mA 1, 2 CMOS standby power supply current ICC5 RAS = UCAS = LCAS = VCC - 0.2V – 2.0 – 2.0 mA VOH IOUT = -5.0 mA 2.4 – 2.4 – V VOL IOUT = 4.2 mA – 0.4 – 0.4 V ICC6 RAS, UCAS or LCAS cycling, tRC = min – 170 – 160 mA Output voltage CAS before RAS refresh current 4/11/01; v.0.9.1 Alliance Semiconductor Notes 1,2 P. 3 of 21 AS4C1M16F5 ® AC parameters common to all waveforms -50 -60 Symbol Parameter Min Max Min Max Unit Notes tRC Random read or write cycle time 84 – 104 – ns tRP RAS precharge time 30 – 40 – ns tRAS RAS pulse width 50 10K 60 10K ns tCAS CAS pulse width 8 10K 10 10K ns tRCD RAS to CAS delay time 15 35 15 43 ns 6 tRAD RAS to column address delay time 12 25 12 30 ns 7 tRSH CAS to RAS hold time 10 – 10 – ns tCSH RAS to CAS hold time 40 – 50 – ns tCRP CAS to RAS precharge time 5 – 5 – ns tASR Row address setup time 0 – 0 – ns tRAH Row address hold time 8 – 10 – ns tT Transition time (rise and fall) 1 50 1 50 ns 4,5 tREF Refresh period – 16 – 16 ms 3 tCP CAS precharge time 8 – 10 – ns tRAL Column address to RAS lead time 25 – 30 – ns tASC Column address setup time 0 – 0 – ns tCAH Column address hold time 8 10 – ns Read cycle -50 Symbol Parameter tRAC -60 Min Max Min Max Access time from RAS – 50 – 60 ns 6 tCAC Access time from CAS – 13 – 17 ns 6,13 tAA Access time from address – 25 – 30 ns 7,13 tRCS Read command setup time 0 – 0 – ns tRCH Read command hold time to CAS 0 – 0 – ns 9 tRRH Read command hold time to RAS 0 – 0 – ns 9 4/11/01; v.0.9.1 Alliance Semiconductor Unit Notes P. 4 of 21 AS4C1M16F5 ® Write cycle -50 Symbol Parameter tWCS -60 Min Max Min Max Unit Notes Write command setup time 0 – 0 – ns 11 tWCH Write command hold time 10 – 10 – ns 11 tWP Write command pulse width 10 – 10 – ns tRWL Write command to RAS lead time 10 – 10 – ns tCWL Write command to CAS lead time 8 – 10 – ns tDS Data-in setup time 0 – 0 – ns 12 tDH Data-in hold time 8 – 10 – ns 12 Read-modify-write cycle -50 -60 Symbol Parameter Min Max Min Max Unit Notes tRWC Read-write cycle time 113 – 135 – ns tRWD RAS to WE delay time 67 – 77 – ns 11 tCWD CAS to WE delay time 32 – 35 – ns 11 tAWD Column address to WE delay time 42 – 47 – ns 11 Notes Refresh cycle -50 Symbol Parameter tCSR -60 Min Max Min Max Unit CAS setup time (CAS-before-RAS) 5 – 5 – ns 3 tCHR CAS hold time (CAS-before-RAS) 8 – 10 – ns 3 tRPC RAS precharge to CAS hold time 0 – 0 – ns 10 – ns tCPT CAS precharge time (CBR counter test) 4/11/01; v.0.9.1 10 Alliance Semiconductor P. 5 of 21 AS4C1M16F5 ® Fast page mode cycle -50 Symbol Parameter tCPA Access time from CAS precharge tRASP -60 Min Max Min Max Unit – 28 – 35 ns RAS pulse width 50 100K 60 100K ns tPC Read-write cycle time 30 – 35 – ns tCP CAS precharge time (fast page) 10 – 10 – ns tPCM Fast page mode RMW cycle 80 – 85 – ns tCRW Page mode CAS pulse width (RMW) 54 – 60 – ns Notes 13 Output enable -50 Symbol Parameter tCLZ -60 Min Max Min Max Unit CAS to output in Low Z 0 – 0 – ns tROH RAS hold time referenced to OE 8 – 10 – ns tOEA OE access time – 13 – 15 ns tOED OE to data delay 13 – 15 – ns tOEZ Output buffer turnoff delay from OE 0 13 0 15 ns tOEH OE command hold time 10 – 10 – ns tOLZ OE to output in Low Z 0 – 0 – ns tOFF Output buffer turn-off time 0 13 0 15 ns 4/11/01; v.0.9.1 Alliance Semiconductor Notes 8 8 8,10 P. 6 of 21 AS4C1M16F5 ® Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ICC1, ICC3, and ICC4 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC ≥ tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. These characteristics apply to AS4C1M16F5 5V devices. AC test conditions - Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.4V and VIL = 0.8V - Input rise and fall times: 2 ns Dout 100 pF* +5V R1 = 828Ω R2 = 295Ω *including scope and jig capacitance GND Figure A: Equivalent output load Key to switching waveforms Rising input 4/11/01; v.0.9.1 Falling input Alliance Semiconductor Undefined output/don’t care P. 7 of 21 AS4C1M16F5 ® Read waveform tRC tRAS tRCD tRSH tRP RAS tCSH tCRP tCAH tCAS tASC tRCS UCAS, LCAS tRAD Address tRAL tRAH tASR Row address Column address tRRH tRCH WE tROH tWEZ tROH OE tOEZ tRAC tAA tOFF (see note 11) tOEA tCAC tREZ tCLZ DQ Data out tOLZ Upper byte read waveform tRC tRAS tRP RAS tRCD tRSH tCSH tCRP tCRP tCAS UCAS tRPC tCRP LCAS tRAH tRAL tRAD tASC tASR Address Row tCAH Column tRCH tRRH tRCS WE tROH tWEZ OE tOLZ tRAC tOEA tREZ tOEZ tAA tCAC tCLZ Upper DQ tOFF Data out Lower DQ 4/11/01; v.0.9.1 Alliance Semiconductor P. 8 of 21 AS4C1M16F5 ® Lower byte read waveform tRC tRAS tRP RAS tRCD tRSH tCSH tCRP tCRP tCAS LCAS tCRP tRPC UCAS tASC tRAH tRAL tRAD tASR tCAH Address Row Column tRCH tRRH tRCS WE tROH tWEZ OE Upper DQ tRAC tREZ tOEA tOLZ tOEZ tAA tCAC tOFF tCLZ Lower DQ Data out Early write waveform tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tCAS UCAS, tRAD LCAS tRAL tASC tASR Address tRAH tCAH Row address Column address tCWL tRWL tWP tWCS tWCH WE OE tDS DQ 4/11/01; v.0.9.1 tDH Data in Alliance Semiconductor P. 9 of 21 AS4C1M16F5 ® Upper byte early write waveform tRC tRAS tRP RAS tASR tRAD tRAL tRAH Address Row address Column address tCAH tRSH tASC tRCD tCSH tCAS tCRP tCRP UCAS tCRP tRPC LCAS tCWL tWCH tWCS tRWL tWP WE OE tDS tDH Upper DQ Data in Lower DQ Lower byte early write waveform tRC tRAS tRP RAS tRAD tASR Address tRAL tRAH Row address Column address tCRP tRPC UCAS tASC tRCD tCAH tCAS tCSH tRSH tCRP tCRP LCAS tRWL tCWL tWCH tWP tWCS WE OE Upper DQ tDS Lower DQ 4/11/01; v.0.9.1 tDH Data in Alliance Semiconductor P. 10 of 21 AS4C1M16F5 ® Write waveform OE controlled tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tCAS UCAS, LCAS tRAL tRAD tRAH tASR tASC tCAH Row address Address Column address tRWL tCWL tWP WE tOEH OE tDS tOED tDH Data in DQ Upper byte write waveform OE controlled tRC tRAS tRP RAS tRAD tASR tRAL tRAH Row address Address Column address tCSH tRSH tRCD tCAH tCRP tASC tCAS tCRP UCAS tCRP tRPC LCAS tCWL tRWL tWP WE tOEH OE tDS Upper DQ tDH Data in tOED Lower DQ 4/11/01; v.0.9.1 Alliance Semiconductor P. 11 of 21 AS4C1M16F5 ® Lower byte write waveform OE controlled tRC tRAS tRP RAS tRAD tASR tRAL tRAH Address Row address Column address tCAH tCAS tRCD tCSH tCRP tRSH tACS tCRP LCAS tCRP tRPC UCAS tCWL tRWL tWP WE tOEH OE Upper DQ tDH tDS Lower DQ Data in Read-modify-write waveform tRWC tRAS tRP RAS tCAS tCRP tRCD tRSH tCSH UCAS, LCAS tAR tRAL tRAD tRAH tASR Address tASC tCAH Row address Column address tRWD tRWL tAWD tRCS WE tCWL tCWD tOEA tOEZ tWP tOED OE tRAC tAA tCAC tCLZ DQ Data out tDS tDH Data in tOLZ 4/11/01; v.0.9.1 Alliance Semiconductor P. 12 of 21 AS4C1M16F5 ® Upper byte read-modify-write waveform tRWC tRAS tRP RAS tCSH tRCD tCAS tRSH tCRP UCAS tCRP tCRP tRPC LCAS tASR tRAD tACS tRAL tCAH tRAH Address Column address tRWD Row tCWL tRWL tAWD tCWD tRCS WE tWP tOEA OE Upper input tDS tOED tOLZ tCLZ tCAC tAA tDH Data in tOEZ tRAC Upper output Data out tOED Lower input Lower output Lower byte read-modify-write waveform tRWC tRAS tRP RAS tCRP tRPC UCAS tCSH tCAS tRSH tRCD tCRP tCRP LCAS tRAD tRAL tACS tASR tCAH tRAH Address Row Column address tCWL tRWD tRWL tWP tAWD tRCS tCWD WE tOEA OE Upper input Upper output tOLZ tOED tDH tDS tOED Lower input tRAC tAA tCAC tCLZ Data in tOEZ Lower output Data out 4/11/01; v.0.9.1 Alliance Semiconductor P. 13 of 21 AS4C1M16F5 ® Fast page mode read waveform tRASP tRP RAS tCSH tCRP tRSH tRCD tCAS tCP tPC CAS tAR tRAD tASR tRAL tASC tRAH Row Address Column tRCS tCAH Column Column tRCS tRCH tRRH tRCH WE tOEA tOEA OE tRAC tOEZ tCLZ tCAP tOFF tAA tCAC Data out I/O Data out Data out Fast page mode byte write waveform tRASP tRP RAS tPCM tCSH tRCD CAS tCAS tCP tCRP tRAD tASR tRAL tRAH tCAH Address Row tCAH Column Column tRWD tRCS tCAH Column tCWL tCWD tRWL tCWD tCWD tAWD tCWL tAWD tWP WE tOEA tOEZ tOED tOEA OE tAA tDH tRAC tCLZ tCAC Data in I/O Data out 4/11/01; v.0.9.1 tDS tDS tCAP tCLZ tCLZ tCAC tCAC Data in Data out Alliance Semiconductor Data in Data out P. 14 of 21 AS4C1M16F5 ® Fast page mode early write waveform tRASP tRAH tRWL RAS tCRP tRCD tPC tCSH tCAH tASC tCAS tCP tWCS tRSH CAS tRAL tAR tASR Address tRAD Row Column Column Column tCWL tWP tWCH tOEH WE OE tHDR tOED tDH tDS I/O Data In Data in Data in CAS before RAS refresh waveform WE = VIH tRC tRP tRAS RAS tRPC tCHR tCP tCSR UCAS, LCAS OPEN DQ RAS only refresh waveform WE = OE = VIH or VIL tRC tRAS tRP RAS tCRP tRPC UCAS, LCAS Address 4/11/01; v.0.9.1 tASR tRAH Row address Alliance Semiconductor P. 15 of 21 AS4C1M16F5 ® Hidden refresh waveform (read) tRC tRC tRAS tRP tRAS tRP RAS tCRP tCHR tRCD tRSH tCRP CAS tAR tRAD tCAH tRAH tASC tASR Row Address Col address tRCS tRRH WE tOEA OE tRAC tOFF tAA tCAC tCLZ tOEZ Data out DQ Hidden refresh waveform (write) tRC tRAS tRP RAS tCRP tRCD tRSH tCHR UCAS, tAR LCAS tRAD tRAL tRAH tASR Address tASC tCAH Row address Col address tRWL tWCR tWP tWCS tWCH WE tDS tDH tDHR DQ Data in OE 4/11/01; v.0.9.1 Alliance Semiconductor P. 16 of 21 AS4C1M16F5 ® CAS before RAS refresh counter test waveform tRAS tRSH tRP RAS tCSR UCAS, tCPT tCAS tCHR LCAS tRAL tASC tCAH Address Col address tAA tCAC tCLZ Read cycle DQ tOFF tOEZ Data out tRRH tRCH tRCS WE tROH tOEA OE tRWL tCWL tWP tWCH Write cycle tWCS WE tDH tDS DQ Data in OE tRWL tWP tRCS tCWD tAWD tCWL Read-Write cycle WE tOEA tOED OE t AA tCLZ tCAC DQ 4/11/01; v.0.9.1 tDH tOEZ tDS Data out Alliance Semiconductor Data in P. 17 of 21 AS4C1M16F5 ® Package dimensions 42-pin SOJ 400 mil Min Max D e A A1 A2 B b c D E E1 E2 e c E1 E2 SOJ Pin 1 E B A2 A A1 Seating Plane b c 36 35 34 33 32 31 30 29 28 27 26 50 49 48 47 46 45 44 43 42 41 40 TSOP II E He 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 0.128 0.148 0.025 0.105 0.115 0.026 0.032 0.015 0.020 0.007 0.013 1.070 1.080 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM d l A A1 A2 b c d E He e l 50-pin TSOP II Min Max (mm) (mm) 1.2 0.05 0.95 1.05 0.30 0.45 0.12 0.21 20.85 21.05 10.03 10.29 11.56 11.96 0.80 (typical) 0.40 0.60 A2 A A1 b 4/11/01; v.0.9.1 e 0–5° Alliance Semiconductor P. 18 of 21 AS4C1M16F5 ® Typical DC and AC characteristics 1.5 1.1 1.0 0.9 0.8 4.0 170 4.5 5.0 5.5 Supply voltage (V) Typical supply current ICC vs. supply voltage VCC Supply current (mA) Supply current (mA) -50 140 -60 130 120 110 4.5 5.0 5.5 Supply voltage (V) 0.9 Typical refresh current ICC3 vs. supply voltage VCC 50 Typical supply current ICC vs. ambient temperature Ta 80 60 -60 120 4.5 5.0 5.5 Supply voltage (V) 4/11/01; v.0.9.1 6.0 25 20 15 10 5 0.0 2 3.5 -50 -60 100 80 60 20 0.0 250 Typical power-on current IPO vs. cycle rate 1/tRC 35 –10 35 80 125 Ambient temperature (°C) 40 40 100 150 200 Load capacitance (pF) 30 -50 130 120 -50 50 30 160 -60 -60 60 Typical refresh current ICC3 vs. Ambient temperature Ta -50 100 -70 70 –10 35 80 125 Ambient temperature (°C) 140 140 120 80 40 150 100 –55 6.0 Refresh current (mA) Refresh current (mA) 1.0 110 140 20 4.0 1.1 160 150 160 1.2 170 160 100 4.0 1.3 0.8 –55 6.0 Typical access time 1.2 90 Power-on current (mA) 1.3 Ta = 25°C Typical access time tRAC vs. load capacitance CL 100 1.4 Normalized access time Normalized access time 1.4 Normalized access time tRAC vs. ambient temperature Ta 4 6 8 Cycle rate (MHz) 10 Typical TTL stand-by current ICC2 vs. supply voltage VCC 3.0 Stand-by current (mA) 1.5 Normalized access time tRAC vs. supply voltage VCC 2.5 2.0 1.5 1.0 0.5 0 20 40 60 80 Ambient temperature (°C) Alliance Semiconductor 4.0 4.5 5.0 5.5 Supply voltage (V) 6.0 P. 19 of 21 AS4C1M16F5 ® 70 Output sink current (mA) Stand-by current (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Hyper page mode current (mA) Typical hyper page mode current ICC4 vs. ambient temperature Ta 140 120 100 -50 80 -60 60 40 20 0.0 0 20 40 60 80 Ambient temperature (°C) 50 40 30 20 10 Input capacitance DQ capacitance Typical output source current IOH vs. output voltage VOH 60 50 40 30 20 10 0.0 0.5 1.0 1.5 Output voltage (V) 2.0 0.0 1.0 2.0 3.0 Output voltage (V) 4.0 Typical hyper page mode current ICC4 vs. supply voltage VCC 140 120 -50 100 -60 80 60 40 20 0.0 4.0 4.5 5.0 5.5 Supply voltage (V) Capacitance 15 Parameter 70 60 0.0 0.0 20 40 60 80 Ambient temperature (°C) Hyper page mode current (mA) 0 Typical output sink current IOL vs. output voltage VOL Output source current (mA) 3.5 Typical TTL stand-by current ICC2 vs. ambient temperature Ta 6.0 Symbol Signals ƒ = 1 MHz, Ta = Room temperature Test conditions Max Unit CIN1 A0 to A9 Vin = 0V 5 pF CIN2 RAS, UCAS, LCAS, WE, OE Vin = 0V 7 pF CDQ DQ0 to DQ15 Vin = Vout = 0V 7 pF AS4C1M16F5 ordering information Package \ RAS access time 50 ns 60 ns Plastic SOJ, 400 mil, 42-pin 5V AS4C1M16F5-50JC AS4C1M16F5-50JI AS4C1M16F5-60JC AS4C1M16F5-60JI TSOP II, 400 mil, 44/50-pin 5V AS4C1M16F5-50TC AS4C1M16F5-50TI AS4C1M16F5-60TC AS4C1M16F5-60TI 4/11/01; v.0.9.1 Alliance Semiconductor P. 20 of 21 AS4C1M16F5 ® AS4C1M16F5 part numbering system AS4 DRAM prefix C C = 5V CMOS 4/11/01; v.0.9.1 1M16E0 –XX Device number RAS access time X X Package: Temperature range C=Commercial, 0°C to 70°C J = 42-pin SOJ 400 mil T=44/50-pin TSOP II 400 mil I=Industrial, -40°C to 85°C Alliance Semiconductor P. 21 of 21