Si5013 OC-12/3, STM-4/1 SONET/SDH CDR IC WITH L IMITING A MPLIFIER Features High-speed clock and data recovery device with integrated limiting amplifier: Supports OC-12/3, STM-4/1 DSPLL™ technology Small footprint: 5 x 5 mm Reference and reference-less operation supported Loss-of-signal level alarm Data slicing level control 10 mVPP differential sensitivity Jitter generation 2.3 mUIrms (typ) 3.3 V supply Ordering Information: See page 21. Applications SONET/SDH test equipment Optical transceiver modules SONET/SDH regenerators Pin Assignments 21 VDD GND 2 20 REXT LOS_LVL 3 SLICE_LVL 4 REFCLK+ 5 REFCLK– 6 LOL 7 Retimer DIN+ DIN– 2 19 RESET/CAL GND Pad 18 VDD 17 DOUT+ 16 DOUT– VDD DSQLCH DIN– 10 11 12 13 14 DIN+ 9 LTR 15 TDI 8 DSQLCH Signal Detect LOS CLKOUT– 1 Functional Block Diagram LOS_LVL CLKOUT+ 28 27 26 25 24 23 22 RATESEL LOS The Si5013 is a fully-integrated, high-performance limiting amplifier (LA) and clock and data recovery (CDR) IC for high-speed serial communication systems. It derives timing information and data from a serial input at OC-12/3 and STM-4/1 rates. Use of an external reference clock is optional. Silicon Laboratories® DSPLL™ technology eliminates sensitive noise entry points, thus making the PLL less susceptible to board-level interaction and helping to ensure optimal jitter performance. The Si5013 represents a new standard in low jitter, low power, small size, and integration for high-speed LA/CDRs. It operates from a 3.3 V supply over the industrial temperature range (–40 to 85 °C). CLKDSBL NC Description VDD Si5013 BER_LVL SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Board level serial links VDD BER_ALM Limiting Amp BUF 2 DOUT+ DOUT– DSPLL BUF BER Monitor 2 CLKOUT+ CLKOUT– CLK_DSBL REFCLK+ REFCLK– (Optional) 2 Lock Detection Bias Gen. Reset/ Calibration BER_ALM REXT SLICE_LVL Rev. 1.4 5/05 LTR BER_LVL LOL RESET/CAL RATESEL Copyright © 2005 by Silicon Laboratories Si5013 Si5013 2 Rev. 1.4 Si5013 TA B L E OF C O N T E N TS Section Page 1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.4. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.6. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.7. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.8. Loss-of-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.9. Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.11. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.12. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.14. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Pin Descriptions: Si5013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Rev. 1.4 3 Si5013 1. Detailed Block Diagram LOS LOS_LVL BER_LVL LTR BER_ALM RATESEL DSQLCH BER Monitor Signal Detect Retime DOUT+ DOUT– DIN+ Limiting Amp Phase Detector A/D DSP VCO CLK Dividers CLKOUT+ CLKOUT– DIN– n SLICE_LVL Lock Detection REFCLK± (optional) REXT 4 CLKDSBL Slicing Control LOL Bias Generation Calibration Rev. 1.4 RESET/CAL Si5013 2. Electrical Specifications Table 1. Recommended Operating Conditions Symbol Parameter Ambient Temperature Si5013 Supply Voltage2 Test Condition Min1 Typ Max1 Unit TA –40 25 85 °C VDD 3.135 3.3 3.465 V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5013 specifications are guaranteed when using the recommended application circuit (including component tolerance) of "3.Typical Application Schematic" on page 11. V SIG NAL+ SIG NAL– V IS t A. Operation with Single-Ended Inputs V SIGNAL+ 0.5 V ID SIGNAL– (SIGNAL+) – (SIG NAL–) V ID t B. O peration with Differential Inputs and Outputs Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT) t Cf-D t C r-D DOUT CLK OUT Rev. 1.4 5 Si5013 Figure 2. Clock to Data Timing 80% DOUT, CLKOUT 20% tF tR Figure 3. DOUT and CLKOUT Rise/Fall Times taq RESET/Cal LOL DATAIN LOL taq Figure 4. PLL Acquisition Time DATAIN LOS Threshold Level LOS tLOS Figure 5. LOS Response 6 Rev. 1.4 Si5013 Table 2. DC Characteristics (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Supply Current1 OC-12 OC-3 IDD Power Dissipation OC-12 OC-3 PD Common Mode Input Voltage (DIN)2 Min Typ Max Unit — — 180 190 190 197 mA — — 594 627 657 682 mW VICM See Figure 11 — 1.50 — V VICM See Figure 10 1.90 2.10 2.30 V VIS See Figure 1A 10 — 500 mV VID See Figure 1B 10 — 1000 mV VIS See Figure 1A 200 — 750 mV REFCLK Differential Input Voltage Swing2 VID See Figure 1B 200 — 1500 mV Input Impedance (DIN) RIN Line-to-Line 84 100 116 : Differential Output Voltage Swing (DOUT) VOD 100 : Load Line-to-Line 700 800 1150 mVPP Differential Output Voltage Swing (CLKOUT) VOD 100 : Load Line-to-Line 700 800 1150 mVPP Output Common Mode Voltage (DOUT, CLKOUT) VOCM 100 : Load Line-to-Line 1.6 1.95 2.35 V Output Impedance (DOUT,CLKOUT) ROUT Single-ended 84 100 116 : Common Mode Input Voltage (REFCLK) DIN Single-ended Input Voltage 2 Swing2 DIN Differential Input Voltage Swing 2 REFCLK Single-ended Input Voltage Swing 2 Input Voltage Low (LVTTL Inputs) VIL — — .8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — — 10 µA Input High Current (LVTTL Inputs) IIH — — 10 µA Input Impedance (LVTTL Inputs) RIN 10 — — k: LOS_LVL, BER_LVL, SLICE_LVL Input Impedance RIN 75 100 125 k: Output Voltage Low (LVTTL Outputs) VOL IO = 2 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = 2 mA 2.0 — — V Notes: 1. No Load on LVTTL outputs. 2. These inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input must be ac coupled to ground. Rev. 1.4 7 Si5013 Table 3. AC Characteristics (Clock and Data) (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit fCLK Rate Sel = 1 Rate Sel = 0 616 154 — — 675 158 MHz Output Rise Time—OC-12 tR Figure 3 — 125 155 ps Output Fall Time—OC-12 tF Figure 3 — 125 155 ps 47 50 53 % of UI 800 4000 840 4100 900 4200 ps 10 800 35 850 60 1000 ps 100 kHz–622 MHz –15 — — dB SLICE_LVL = 750 mV to 2.25 V –15 — 15 mV SLICE_LVL = 750 mV to 2.25 V — ±5 — mV Output Clock Rate Output Clock Duty Cycle— OC-12/3 Clock to Data Delay OC-12 OC-3 tCr-D Clock to Data Delay OC-12 OC-3 tCf-D Input Return Loss 1 Slicing Level Offset (relative to the internally set input common mode voltage) VSLICE Slicing Level Accuracy Range2 Figure 2 Figure 2 Loss-of-Signal (peak-to-peak differential) VLOS LOS_LVL = 1.50 to 2.50 V 0 — 40 mV Loss-of-Signal Response Time tLOS Figure 5 on page 6 8 20 25 µs Notes: 1. Adjustment voltage (relative to the internally set input common mode voltage) is calculated as follows: VSLICE = (SLICE_LVL – 1.50)/50. 2. Adjustment voltage is calculated as follows: VLOS = (LOS_LVL – 1.50)/25. 8 Rev. 1.4 Si5013 Table 4. AC Characteristics (PLL Characteristics) (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Tolerance (OC-12 Mode)* JTOL(PP) f = 30 Hz 60 — — UIPP f = 300 Hz 6 — — UIPP f = 25 kHz 4 — — UIPP f = 250 kHz 0.4 — — UIPP f = 30 Hz 60 — — UIPP f = 300 Hz 6 — — UIPP f = 6.5 kHz 4 — — UIPP f = 65 kHz 0.4 — — UIPP JGEN(rms) with no jitter on serial data — 2.3 4.0 mUI JGEN(PP) with no jitter on serial data — 20 45 mUI JBW OC-12 Mode — — 500 kHz OC-3 Mode — — 130 kHz — 0.03 0.1 dB After falling edge of PWRDN/CAL — 1.5 2 ms From the return of valid data — 60 — µs After falling edge of PWRDN/CAL — 4.0 12 ms From the return of valid data — 13 — ms Jitter Tolerance (OC-3 Mode)* RMS Jitter JTOL(PP) Generation* Peak-to-Peak Jitter Generation* Jitter Transfer Bandwidth* Jitter Transfer Peaking* Acquisition Time—OC-12 (Reference clock applied) Acquisition Time—OC-12 (Reference-less operation) JP TAQ TAQ Reference Clock Range Input Reference Clock Frequency Tolerance See "4.4.Operation Without an External Reference" on page 12. CTOL Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) MHz 155.5 77.76 19.44 –500 — 500 ppm — ±650 — ppm *Note: As defined in Bellcore specifications: GR-253-CORE, Issue 3, September 2000. Using PRBS 223 – 1 data pattern. Rev. 1.4 9 Si5013 Table 5. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 3.5 V LVTTL Input Voltage VDIG –0.3 to 3.6 V Differential Input Voltages VDIF –0.3 to (VDD+ 0.3) V ±50 mA Maximum Current any output PIN Operating Junction Temperature TJCT –55 to 150 °C Storage Temperature Range TSTG –55 to 150 °C 1 kV ESD HBM Tolerance (100 pf, 1.5 k:) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient 10 Symbol Test Condition Value Unit MJA Still Air 38 °C/W Rev. 1.4 Si5013 3. Typical Application Schematic LOS LOL BER_ALM DSQLCH RATESEL RESET/CAL DOUT+ DIN– DOUT– Si5013 REFCLK+ CLKOUT+ VDD REXT Recovered Data Recovered Clock GND CLKOUT– SLICE_LVL REFCLK– BER_LVL System Reference Clock (Optional) DIN+ LOS_LVL High-Speed Serial Input CLKDSBL LTR BER Alarm LVTTL Loss-of-Signal Control Inputs Indicator Indicator Loss-of-Lock Indicator 100 pF x 4 10 k: VDD 0.1 PF Loss-of-Signal Data Slice Level Set Level Set Bit Error Rate Level Set Rev. 1.4 11 Si5013 4. Functional Description The Si5013 integrates a high-speed limiting amplifier with a multi-rate CDR unit. No external reference clock is required for clock and data recovery. The limiting amplifier magnifies very low-level input data signals so that accurate clock and data recovery can be performed. The CDR uses Silicon Laboratories® DSPLL technology to recover a clock synchronous to the input data stream. The recovered clock retimes the incoming data, and both are output synchronously via current-mode logic (CML) drivers. Silicon Laboratories’ DSPLL technology ensures superior jitter performance while eliminating the need for external loop filter components found in traditional phase-locked loop (PLL) implementations. traditional methods, and it eliminates performance degradation caused by external component aging. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources and making SONET/SDH jitter compliance easier to attain in the application. 4.3. Multi-Rate Operation The Si5013 supports clock and data recovery for OC12/3 and STM-4/1 data streams. Multi-rate operation is achieved by configuring the device to divide down the output of the VCO to the desired data rate. The divide factor is configured by the RATESEL pin. The RATESEL configuration and associated data rates are given in Table 7. The limiting amplifier includes a control input for adjusting the data slicing level and provides a loss-ofsignal level alarm output. The CDR includes a bit error rate performance monitor which signals a high bit error rate condition (associated with excessive incoming jitter) relative to an externally adjustable bit error rate threshold. The optional reference clock minimizes the CDR acquisition time and provides a stable reference for maintaining the output clock when locking to a reference is desired. 4.1. Limiting Amplifier The limiting amplifier accepts the low-level signal output from a transimpedance amplifier (TIA). The low-level signal is amplified to a usable level for the CDR unit. The minimum input swing requirement is specified in Table 2 on page 7. Larger input amplitudes (up to the maximum input swing specified in Table 2) are accommodated without degradation of performance. The limiting amplifier ensures optimal data slicing by using a digital dc offset cancellation technique to remove any dc bias introduced by the amplification stage. 4.2. DSPLL™ The Si5013 PLL structure (shown in the "1.Detailed Block Diagram" on page 4) utilizes Silicon Laboratories' DSPLL technology to maintain superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage-controlled oscillator (VCO). This technology enables CDR with far less jitter than is generated using 12 Table 7. Multi-Rate Configuration RATESEL SONET/SDH 1 622.08 Mbps 0 155.52 Mbps 4.4. Operation Without an External Reference The Si5013 can perform clock and data recovery without an external reference clock. Tying the REFCLK+ input to VDD and the REFCLK– input to GND configures the device to operate without an external reference clock. Clock recovery is achieved by monitoring the timing quality of the incoming data relative to the VCO frequency. Lock is maintained by continuously monitoring the incoming data timing quality and adjusting the VCO accordingly. Details of the lock detection and the lock-to-reference functions while in this mode are described in their respective sections below. Note: Without an external reference the acquisition of data is dependent solely on the data itself and typically requires more time to acquire lock than when a reference is applied. 4.5. Operation With an External Reference The Si5013 can also perform clock and data recovery with an external reference. The device’s optional external reference clock centers the DSPLL, minimizes the acquisition time, and maintains a stable output clock (CLKOUT) when lock-to-reference (LTR) is asserted. When the reference clock is present, the Si5013 uses the reference clock to center the VCO output frequency so that clock and data is recovered from the input data stream. The device self configures for operation with one of three reference clock frequencies. This Rev. 1.4 Si5013 When an external reference clock is provided, the circuit compares the frequency of a divided-down version of the recovered clock with the frequency of the applied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 9, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. In this state, the PLL will periodically try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (CLKOUT) drifts over a ±600 ppm range relative to the applied reference clock and the LOL output alarm may toggle until the PLL has reacquired frequency lock. Due to the low noise and stability of the DSPLL, there is the possibility that the PLL will not drift enough to render an out-of-lock condition, even if the data is removed from inputs. 40 mV 40 mV/V 0V 1.00 V 1.50 V 2.25 V 1.875 V 2.5 V LOS_LVL (V) Figure 6. LOS_LVL Mapping R1 In the absence of an external reference, the lock detect circuitry uses a data quality measure to determine when frequency lock has been lost with the incoming data stream. During reacquisition, CLKOUT may vary by approximately ±10% from the nominal data rate. 3 LOS_LVL Set LOS Level R2 4.7. Lock-to-Reference When an external reference clock is present, assertion of LTR forces the DSPLL to lock CLKOUT to the provided reference. If no external reference clock is used, LTR forces the DSPLL to hold the digital frequency control input to the VCO at the last value. This produces a stable output clock as long as supply and temperature are constant. 15 mV 0 mV In applications requiring a more stable output clock during out-of-lock conditions, the lock-to-reference (LTR) input can be used to force the PLL to lock to the externally supplied reference. The LTR input can be used to force a stable output clock when an alarm condition, like LOS, exists. In typical applications, the LOS output is tied to the LTR input to force a stable output clock when the input data signal is lost. When LTR is asserted, the DSPLL is prevented from acquiring the data signal present on DIN. The operation of the LTR control input depends on which reference clocking mode is used. 30 mV LOS Undefined The Si5013 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. The operation of the lock-detector depends on the reference clock option used. The Si5013 indicates a loss-of-signal condition on the LOS output pin when the input peak-to-peak signal level on DIN falls below an externally controlled threshold. The LOS threshold range is specified in Table 3 on page 8 and is set by applying a voltage on the LOS_LVL pin. The graph in Figure 6 illustrates the LOS_LVL mapping to the LOS threshold. The LOS output is asserted when the input signal drops below the programmed peak-to-peak value. If desired, the LOS function may be disabled by grounding LOS_LVL or by adjusting LOS_LVL to be less than 1 V. LOS Disabled 4.6. Lock Detect 4.8. Loss-of-Signal LOS Threshold (mVPP) eliminates the need to externally configure the device to operate with a particular reference clock. The REFCLK frequency should be 19.44, 77.76, or 155.52 MHz with a frequency accuracy of ±100 ppm. 10k Si5013 CDR LOS 9 LOS Alarm Figure 7. LOS Signal Hysteresis In many applications it is desirable to produce a fixed amount of signal hysteresis for an alarm indicator such as LOS, since a marginal data input signal could cause intermittent toggling, leading to false alarm status. When it is anticipated that very low-level DIN signals will be encountered, the introduction of an adequate amount of LOS hysteresis is recommended to minimize any undesirable LOS signal toggling. Figure 7 illustrates a simple circuit that may be used to set a fixed level of LOS signal hysteresis for the Si5013 CDR. The value of Rev. 1.4 13 Si5013 R1 may be chosen to provide a range of hysteresis from 3 to 8 dB where a nominal value of 800 : adjusts the hysteresis level to approximately 6 dB. Use a value of 500 : or 1000 : for R1 to provide 3 dB or 8 dB of hysteresis, respectively. Hysteresis is defined as the ratio of the LOS deassert level (LOSD) and the LOS assert level (LOSA). The hysteresis in decibels is calculated as 20log(LOSD/ LOSA). 4.9. Bit Error Rate (BER) Detection 4.11.1. Jitter Tolerance The Si5013’s tolerance to input jitter exceeds that of the Bellcore/ITU mask shown in Figure 8. This mask defines the level of peak-to-peak sinusoid jitter that must be tolerated when applied to the differential data input of the device. Sinusoidal Input Jitter (UIPP) Slope = 20 dB/Decade 15 The Si5013 uses a proprietary Silicon Laboratories® algorithm to generate a bit error rate (BER) alarm on the BER_ALM pin if the observed BER is greater than a user programmable threshold. Bit error detection relies on the input data edge timing; edges occurring outside of the expected event window are counted as bit errors. The BER threshold is programmed by applying a voltage to the BER_LVL pin between 500 mV and 2.25 V corresponding to a BER of approximately 10–10 and 10–6, respectively. The voltage present on BER_LVL maps to the BER as follows: log10(BER) = (4 x BER_LVL) –13. (BER_LVL is in volts; BER is in bits per second.) 1.5 0.15 f0 SONET Data Rate OC-12 OC-3 f1 F0 (Hz) 10 10 f2 f3 Frequency F1 (Hz) 30 30 ft F2 F3 Ft (kHz) (kHz) (kHz) 300 25 250 300 6.5 65 Figure 8. Jitter Tolerance Specification 4.10. Data Slicing Level The Si5013 provides the ability to externally adjust the slicing level for applications that require bit error rate (BER) optimization. Adjustments in slicing level of ±15 mV (relative to the internally set input common mode voltage) are supported. The slicing level is set by applying a voltage between 0.75 and 2.25 V to the SLICE_LVL input. The voltage present on SLICE_LVL maps to the slicing level as follows: 4.11.2. Jitter Transfer The Si5013 exceeds all relevant Bellcore/ITU specifications related to SONET/SDH jitter transfer. Jitter transfer is defined as the ratio of output signal jitter to input signal jitter as a function of jitter frequency. These measurements are made with an input test signal that is degraded with sinusoidal jitter whose magnitude is defined by the mask in Figure 9. V SLICE_LVL – 1.5 V V SLICE = ------------------------------------------------------50 Jitter Transfer where VSLICE is the slicing level, and VSLICE_LVL is the voltage applied to the SLICE_LVL pin. When SLICE_LVL is driven below 500 mV, the slicing level adjustment is disabled, and the slicing level is set to the cross-point of the differential input signal. 4.11. PLL Performance The PLL implementation used in the Si5013 is fully compliant with the jitter specifications proposed for SONET/SDH equipment by Bellcore GR-253-CORE, Issue 3, September 2000 and ITU-T G.958. 0.1 dB 20 dB/Decade Slope Acceptable Range Fc Frequency SONET Data Rate OC-12 OC-3 Fc (kHz) 500 130 Figure 9. Jitter Transfer Specification 14 Rev. 1.4 Si5013 4.11.3. Jitter Generation 4.15. Device Grounding The Si5013 exceeds all relevant specifications for jitter generation proposed for SONET/SDH equipment. The jitter generation specification defines the amount of jitter that may be present on the recovered clock and data outputs when a jitter free input signal is provided. The Si5013 typically generates less than 3.0 mUIrms of jitter when presented with jitter-free input data. The Si5013 uses the GND pad on the bottom of the 28pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figure 15 on page 18 and Figure 16 on page 22 for the ground (GND) pad location. 4.12. RESET/DSPLL Calibration The Si5013 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k: (1%) resistor connected between REXT and GND. The Si5013 achieves optimal jitter performance by automatically calibrating the loop gain parameters within the DSPLL on powerup. Calibration may also be initiated by a high-to-low transition on the RESET/CAL pin. The RESET/CAL pin must be held high for at least 1 µs. When RESET/CAL is released (set to low) the digital logic resets to a known initial condition, recalibrates the DSPLL, and begins to lock to the incoming data stream. For a valid reset to occur when using Reference mode, a proper, external reference clock frequency must be applied. 4.13. Clock Disable The Si5013 provides a clock disable pin (CLK_DSBL) that is used to disable the recovered clock output (CLKOUT). When the CLK_DSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to VDD through 100 :on-chip resistors. 4.14. Data Squelch The Si5013 provides a data squelching pin (DSQLCH) that is used to set the recovered data output (DOUT) to binary zero. When the DSQLCH pin is asserted, the DOUT+ signal is held low and the DOUT– signal is held high. This pin can be is used to squelch corrupt data during LOS and LOL situations. Care must be taken when ac coupling these outputs; a long string of zeros or ones will not be held through ac coupling capacitors. 4.16. Bias Generation Circuitry 4.17. Voltage Regulator The Si5013 operates from a 3.3 V external supply voltage. Internally the device operates from a 2.5 V supply. The Si5013 regulates 2.5 V internally down from the external 3.3 V supply. In addition to supporting 3.3 V systems, the on-chip linear regulator offers better power supply noise rejection versus a direct 2.5 V supply. 4.18. Differential Input Circuitry The Si5013 provides differential inputs for both the highspeed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figures 10 and 11, respectively. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. (LOS operation is only guaranteed when ac coupled.) The data input limiting amplifier requires an input signal with a differential peak-to-peak voltage as specified in Table 2 on page 7 to ensure a BER of at least 10–12. The REFCLK input differential peak-to-peak voltage requirement is also specified in Table 2. Rev. 1.4 15 Si5013 Si5013 Clock source 2.5 V (±5%) 2.5 k: 0.1 PF Zo = 50 : RFCLK+ 100 : 0.1 PF Zo = 50 : 10 k: 2.5 k: RFCLK– 10 k: GND Figure 10. Input Termination for REFCLK (ac coupled) Si5013 TIA 2.5 V (±5%) 0.1 PF Zo = 50 : DIN+ 50 : 0.1 PF 5 k: 50 : Zo = 50 : 7.5 k: DIN– GND Figure 11. Input Termination for DIN (ac coupled) Si5013 Clock source 2.5 V (±5%) 2.5 k: 0.1 PF Zo = 50 : RFCLK + 10 k: 2.5 k: 50 : RFCLK – 10 k: 0.1 PF GND Figure 12. Single-Ended Input Termination for REFCLK (ac coupled) 16 Rev. 1.4 Si5013 Si5013 Signal source 0.1 PF 2.5 V (±5%) Zo = 50 : DIN+ 50 : 5 k: 100 : 50 : 7.5 k: DIN– 0.1 PF GND Figure 13. Single-Ended Input Termination for DIN (ac coupled) 4.19. Differential Output Circuitry The Si5013 utilizes a current-mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 14. In applications in which direct dc coupling is possible, the 0.1 PF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is specified in Table 2 on page 7. Si5013 VDD 50 : 2.5 V (±5%) 100 : DOUT+, CLKOUT+ 0.1 PF Zo = 50 : DOUT–, CLKOUT– 0.1 PF Zo = 50 : 100 : 2.5 V (±5%) 50 : VDD Figure 14. Output Termination for DOUT and CLKOUT (ac coupled) Rev. 1.4 17 Si5013 CLKOUT– CLKOUT+ CLKDSBL VDD BER_LVL BER_ALM NC 5. Pin Descriptions: Si5013 28 27 26 25 24 23 22 RATESEL 1 21 VDD GND 2 20 REXT LOS_LVL 3 SLICE_LVL 4 REFCLK+ 5 REFCLK– 6 LOL 7 19 RESET/CAL GND Pad 18 VDD 17 DOUT+ 16 DOUT– VDD DIN– DIN+ VDD 10 11 12 13 14 DSQLCH LTR 9 LOS 15 TDI 8 Figure 15. Si5013 Pin Configuration Table 8. Si5013 Pin Descriptions Pin # Pin Name I/O Signal Level 1 RATESEL I LVTTL Description Data Rate Select. This pin configures the onboard PLL for clock and data recovery at one of two user selectable data rates. See Table 7 for configuration settings. Note: This input has a weak internal pullup. 3 LOS_LVL I LOS Level Control. The LOS threshold is set by the input voltage level applied to this pin. Figure 6 on page 13 shows the input setting to output threshold mapping. LOS is disabled when the voltage applied is less than 1 V. 4 SLICE_LVL I Slicing Level Control. The slicing threshold level is set by applying a voltage to this pin as described in the Slicing Level section of the data sheet. If this pin is tied to GND, slicing level adjustment is disabled, and the slicing level is set to the midpoint of the differential input signal on DIN. Slicing level becomes active when the voltage applied to the pin is greater than 500 mV. 5 6 18 REFCLK+ REFCLK– I See Table 2 Differential Reference Clock (Optional). When present, the reference clock sets the center operating frequency of the DSPLL for clock and data recovery. Tie REFCLK+ to VDD and REFCLK– to GND to operate without an external reference clock. See Table 7 on page 12 for typical reference clock frequencies. Rev. 1.4 Si5013 Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 7 LOL O LVTTL Description Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4 on page 9. If no external reference is supplied, this signal will be active when the internal PLL is no longer locked to the incoming data. 8 LTR I LVTTL Lock-to-Reference. When this pin is low, the DSPLL disregards the data inputs. If an external reference is supplied, the output clock locks to the supplied reference. If no external reference is used, the DSPLL locks the control loop until LTR is released. Note: This input has a weak internal pullup. 9 LOS O LVTTL Loss-of-Signal. This output pin is driven low when the input signal is below the threshold set via LOS_LVL. (LOS operation is guaranteed only when ac coupling is used on the DIN inputs.) 10 DSQLCH LVTTL Data Squelch. When driven high, this pin forces the data present on DOUT+ to zero and DOUT– to one. For normal operation, this pin should be low. DSQLCH may be used during LOS/LOL conditions to prevent random data from being presented to the system. Note: This input has a weak internal pulldown. 11,14,18,21, 25 VDD 12 13 DIN+ DIN– 15 GND 3.3 V Supply Voltage. Nominally 3.3 V. I See Table 2 Differential Data Input. Clock and data are recovered from the differential signal present on these pins. AC coupling is recommended. GND Production Test Input. This pin is used during production testing and must be tied to GND for normal operation. 16 17 DOUT– DOUT+ O 19 RESET/CAL I CML Differential Data Output. The data output signal is a retimed version of the data recovered from the signal present on DIN. It is phase aligned with CLKOUT and is updated on the rising edge of CLKOUT. LVTTL Reset/Calibrate. Driving this input high for at least 1 Ps will reset internal device circuitry. A high to low transition on this pin will force a DSPLL calibration. For normal operation, drive this pin low. Note: This input has a weak internal pulldown. Rev. 1.4 19 Si5013 Table 8. Si5013 Pin Descriptions (Continued) Pin # Pin Name 20 REXT I/O Signal Level Description External Bias Resistor. This resistor is used to establish internal bias currents within the device. This pin must be connected to GND through a 10 k:1resistor. 22 23 CLKOUT– CLKOUT+ O 24 CLKDSBL I CML Differential Clock Output. The output clock is recovered from the data signal present on DIN except when LTR is asserted or the LOL state has been entered. LVTTL Clock Disable. When this input is high, the CLKOUT output drivers are disabled. For normal operation, this pin should be low. Note: This input has a weak internal pulldown. 26 BER_LVL I Bit Error Rate Level Control. The BER threshold level is set by applying a voltage to this pin. When the BER exceeds the programmed threshold, BER_ALM is driven low. If this pin is tied to GND, BER_ALM is disabled. There is no hysteresis. 27 BER_ALM O LVTTL Bit Error Rate Alarm. This pin will be driven low to indicate that the BER threshold set by BER_LVL has been exceeded. The alarm will clear after the BER rate has improved by approximately a factor of 2. 28 NC No Connect. Leave this pin disconnected. GND Pad, 2 GND GND Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 28-lead MLP (see Figure 16 on page 22) must be connected directly to supply ground. Minimize the ground path inductance for optimal performance. 20 Rev. 1.4 Si5013 6. Ordering Guide Part Number Package Voltage Lead-Free Temperature Si5013-X-GM 28-lead MLP 3.3 Yes –40 to 85 °C Notes: 1. “X” denotes product revision. 2. Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. Rev. 1.4 21 Si5013 7. Package Outline Figure 16 illustrates the package details for the Si5013. Table 9 lists the values for the dimensions shown in the illustration. 2X 0.10 C A A D D/2 0.05 C A D1 b D1/2 M C A B D2 2X N 0.10 C B 1 2 3 0.10 A1 E1/2 N 1 2 3 E/2 E1 E (Ne–1) Xe REF. E2 L B TOP VIEW T C SEATING PLANE e (Nd–1) Xe REF. C CL C b A1 BOTTOM VIEW SECTION "C–C" e SCALE: NONE Approximate device weight is 62.2 mg. Figure 16. 28-Lead Micro Leaded Package (MLP) Table 9. Package Diagram Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom A — 0.85 A1 0.00 0.01 b 0.18 0.23 D 5.00 BSC D1 4.75 BSC D2 2.95 3.10 E 5.00 BSC E1 4.75 BSC E2 2.95 3.10 N 28 Nd 7 Ne 7 e 0.50 BSC L 0.50 0.60 T 22 Rev. 1.4 Max 0.90 0.05 0.30 3.25 3.25 0.75 12° Si5013 DOCUMENT CHANGE LIST Revision 1.1 to Revision 1.2 Revision 0.2 to Revision 1.0 Added Figure 4, “PLL Acquisition Time,” on page 6. Table 2 on page 7 values: Supply Current values: Power Dissipation zUpdated values: Common Mode Input Voltage (REFCLK) zUpdated values: Output Common Mode Voltage Added Figure 5, “LOS Response,” on page 6. Updated Table 2 on page 7. zAdded “Output Common Mode Voltage (DOUT)” with updated values. zAdded “Output Common Mode Voltage (CLKOUT)” with updated values. zUpdated zUpdated zAdded zAdded Table 3 on page 8 values: Output Clock Rise Time zUpdated values: Output Clock Fall Time zUpdated values: Clock to Data Delay tCf-D zChanged zUpdated values: Jitter Tolerance (OC-12) values: RMS Jitter Generation zUpdated values: Peak-to-Peak Jitter Generation zUpdated values: Acquisition Time (reference clock applied) zUpdated values: Acquisition Time (reference-less operation) zUpdated values: Freq Difference at which Receive PLL goes out of Lock zUpdated values: Freq Difference at which Receive PLL goes into Lock zUpdated Removed “Hysteresis Dependency” Figure. Added Figure 7, “LOS Signal Hysteresis,” on page 13. Corrected error: Table 8 on page 18—changed description for LOS_LVL from “LOS is disabled when the voltage applied is less than 500 mV” to “LOS is disabled when the voltage applied is less than 1.0 V.” Revision 1.0 to Revision 1.1 zUpdated “clock input” to “DIN inputs” for Loss Of Signal Updated Figure 16, “28-Lead Micro Leaded Package (MLP),” on page 22. Updated Table 9, “Package Diagram Dimensions,” on page 22. zChanged zChanged dimension A. dimension E2. Revision 1.2 to Revision 1.3 Updated Figure 16, “28-Lead Micro Leaded Package (MLP),” on page 22. Updated Table 9, “Package Diagram Dimensions,” on page 22. Revision 1.3 to Revision 1.4 Updated "Features" on page 1. Table 2 on page 7. zUpdated supply current values. power dissipation values. zUpdated differential output voltage swing (DOUT and CLKOUT). zUpdated Table 3 on page 8. zAdded output clock rate values. duty cycle values. zUpdated slice accuracy values. Corrected “Revision 0.2 to Revision 1.0” Change List. Table 4 on page 9 Updated Table 8 on page 18. Table 4 on page 9 “Output Clock Duty Cycle—OC-12/3.” “Loss-of-Signal Response Time” with updated values. zUpdated Updated Table 3 on page 8. zUpdated Table 4 on page 9. zUpdated jitter tolerance values (OC-12 mode). acquisition time values. zUpdated reference clocks range. zUpdated reference clocks tolerance. values: Jitter Tolerance (OC-3) zUpdated "3.Typical Application Schematic" on page 11. zAdded 1% to Rext. "4.11.PLL Performance" on page 14. zRemoved zAdded no-hysteresis text to BER_LVL. Updated "6.Ordering Guide" on page 21. zAdded Rev. 1.4 OC-24 note. Table 8 on page 18. “X” to part number. 23 Si5013 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 24 Rev. 1.4