XRT7295AT
DS3/Sonet STS-1
Integrated Line Receiver
December 2000-2
FEATURES
APPLICATIONS
D Fully Integrated Receive Interface for DS3 and
STS-1 Rate Signals
D Interface to DS-3 Networks
D Digital Cross-Connect Systems
D Integrated Equalization (Optional) and Timing
Recovery
D CSU/DSU Equipment
D Loss-of-Signal and Loss-of-Lock Alarms
D PCM Test Equipment
D Variable Input Sensitivity Control
D Fiber Optic Terminals
D 5V Power Supply
D Pin Compatible with XRT7295AE and XRT7295AC
D Companion Device to T7296 Transmitter
GENERAL DESCRIPTION
The XRT7295AT DS3/SONET STS-1 integrated line
receiver is a fully integrated receive interface that
terminates a bipolar DS3 (44.736Mbps) or Sonet STS-1
(51.84Mbps) signal transmitted over coaxial cable. (See
Figure 13).
The device also provides the functions of receive
equalization (optional), automatic-gain control (AGC),
clock-recovery and data retiming, loss-of-signal and
loss-of-frequency-lock detection. The digital system
interface is dual-rail, with received positive and negative
1s appearing as unipolar digital signals on separate
output leads. The on-chip equalizer is designed for cable
distances of 0 to 450ft. from the cross-connect frame to
the device. The receive input has a variable input
sensitivity control, providing three different sensitivity
settings, to adapt longer cables. High input sensitivity
allows for significant amounts of flat loss within the
system. Figure 1 shows the block diagram of the device.
The XRT7295AT device is manufactured using linear
CMOS technology. The XRT7295AT is available in a
20-pin plastic SOJ package for surface mounting.
Two versions of the chip are available, one is for either
DS3 or STS-1 operation (the XRT7295AT, this data
sheet), and the other is for E3 operation (the XRT7295AE,
refer to the XRT7295AE data sheet). Both versions are
pin compatible.
For either DS3 or STS-1, an input reference clock at
44.736MHz or 51.84MHz provides the frequency
reference for the device.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XRT7295ATIW
20 Lead 300 Mil JEDEC SOJ
-40°C to + 85°C
Rev. 1.20
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
XRT7295AT
BLOCK DIAGRAM
LPF1 LPF2 VDDA GNDA VDDD GNDD VDDC GNDC
REQB
4
18
2
Attenuator
Gain &
Equalizer
Loop
Filter
Phase
Detector
Slicers
RIN
5
20
1
11
9
12
14 RCLK
VCO
16 RPDATA
Retimer
15 RNDATA
Peak
Detector
19
Analog
LOS
Digital
LOS
Detector
Frequency Phase
Aquisition Circuit
AGC
LOSTHR
Analog
LOS
Equalizer
Tuning Ckt.
17
3
6
13
ICT
TMC1
TMC2
EXCLK
8
RLOL
Figure 1. Block Diagram
Rev.1.20
2
10
7
RLOS
XRT7295AT
PIN CONFIGURATION
GNDA
RIN
TMC1
LPF1
LPF2
TMC2
RLOS
RLOL
GNDD
GNDC
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VDDA
LOSTHR
REQB
ICT
RPDATA
RNDATA
RCLK
EXCLK
VDDC
VDDD
20 Lead SOJ (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
Type
1
2
GNDA
RIN
I
3,6
TMC1-TMC2
I
4,5
7
LPF1-LPF2
RLOS
I
O
8
9
RLOL
GNDD
O
10
GNDC
11
VDDD
12
VDDC
13
EXCLK
I
14
15
RCLK
RNDATA
O
O
16
RPDATA
O
17
ICT
I
18
REQB
I
19
LOSTHR
I
20
VDDA
Description
Analog Ground.
Receive Input. Analog receive input. This pin is internally biased at about 1.5V in series
with 50 kW.
Test Mode Control 1 and 2. Internal test modes are enabled within the device by using
TMC1 and TMC2. Users must tie these pins to the ground plane.
PLL Filter 1 and 2. An external capacitor (0.1mF ±20%) is connected between these pins.
Receive Loss-of-signal. This pin is set high on loss of the data signal at the receive input.
(See Table 6)
Receive PLL Loss-of-lock. This pin is set high on loss of PLL frequency lock.
Digital Ground for PLL Clock. Ground lead for all circuitry running synchronously with
PLL clock.
Digital Ground for EXCLK. Ground lead for all circuitry running synchronously with
EXCLK.
5V Digital Supply (±10%) for PLL Clock. Power for all circuitry running synchronously
with PLL clock.
5V Digital Supply (±10%) for EXCLK. Power for all circuitry running synchronously with
EXCLK.
External Reference Clock. A valid DS3 (44.736MHz ±100ppm) or STS-1 (51.84MHz +
100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD
/2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns.
Receive Clock. Recovered clock signal to the terminal equipment.
Receive Negative Data. Negative pulse data output to the terminal equipment. (See
Figure 11.)
Receive Positive Data. Positive pulse data output to the terminal equipment. (See
Figure 11)
In-circuit Test Control (Active-low). If ICT is forced low, all digital output pins (RCLK,
RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-circuit testing. There is an internal pull-up on this pin.
Receive Equalization Bypass. A high on this pin bypasses the internal equalizer. A low
places the equalizer in the data path.
Loss-of-signal Threshold Control. The voltage forced on this pin controls the input lossof-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD. This pin
must be set to the desired level upon power-up and should not be changed during operation.
5V Analog Supply (±10%).
Rev.1.20
3
XRT7295AT
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = -40°C to +85°C, VDD = 5V + 10%
Typical Values are for VDD = 5.0 V, 25°C, and Random Data. Maximum Values are for VDD = 5.5V all 1s Data.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
82
106
mA
REQB=0
79
103
mA
REQB=1
87
111
mA
REQB=0
83
108
mA
REQB=1
Electrical Characteristics
IDD
Power Supply Current
DS3
STS--1
Logic Interface Characteristics
Input Voltage
VIL
Low
GNDD
0.5
V
VIH
High
VDDD-0.5
VDDD
V
Output Voltage
VOL
Low
GNDD
0.4
V
-5.0mA
VOH
High
VDDD-0.5
VDDD
V
5.0mA
10
pF
CI
Input Capacitance
CL
Load Capacitance
IL
Input Leakage
10
pF
-10
10
mA
-0.5 to VDD + 0.5V
(all input pins except 2, 3, 4, 5, 6,
17, 18, & 19)
20
500
mA
0 V (pin 17)
10
100
mA
VDD (pin 2)
-50
-5
mA
GNDD (pin 2)
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V
Storage Temperature . . . . . . . . . . . . -40°C to +125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 700 mW
Rev.1.20
4
XRT7295AT
System A
0-450 ft.
0-450 ft.
System B
Cross
Connect
XR-T7296
Transmitter
XRT7295AT
Frame
Receiver
DSX-3
or STSX-1
Type 728A
Coaxial Cable
Figure 2. Application Diagram
SYSTEM DESCRIPTION
Receive Path Configurations
In the receive signal path (see Figure 1), the internal
equalizer can be included by setting REQB = 0 or
bypassed by setting REQB = 1. The equalizer bypass
option allows easy interfacing of the XRT7295AT device
into systems already containing external equalizers.
Figure 3 illustrates the receive path options.
In Case 2 of Figure 3, external line build-out (LBO) and
equalizer networks precede the XRT7295AT device. In
this mode, the signal at RIN is already equalized, and the
on-chip filters should be bypassed by setting REQB=1.
In applications where the XRT7295AT device is used to
monitor DS3 transmitter outputs directly, the receive
equalizer should be bypassed.
Maximum input amplitude under all conditions is 850mV
pk.
In Case 1 of Figure 3, the signal from the DSX-3
cross-connect feeds directly into RIN. In this mode, the
user should set REQB = 0, engaging the equalizer in the
data path.
Rev.1.20
5
XRT7295AT
0-450 ft.
CASE 1:
D
0
REQB
0.01mF
RIN
S
75
X
CASE 2:
LPF1
0.1mF
LPF2
XRT7295AT
Existing
Off-chip
Networks
0-450 ft.
D
1
REQB
0.01mF
Fixed
Equalizer
225 ft.
LBO
S
RIN
75
X
Closed For
225-450 ft.
Of Cable
Figure 3. Receiver Configurations
Rev.1.20
6
LPF1
LPF2
XRT7295AT
0.1mF
XRT7295AT
DS3 SIGNAL REQUIREMENTS AT THE DSX
Pulse characteristics are specified at the DSX-3, which is
an interconnection and test point referred to as the
cross-connect (see Figure 2.) The cross-connect exists
at the point where the transmitted signal reaches the
distribution frame jack. Table 1 lists the signal
requirements. Currently, two isolated pulse template
Parameter
requirements exist: the ACCUNET T45 pulse template
(see Table 2 and Figure 4)and the G.703 pulse template
(see Table 3 and Figure 5). Table 2 and Table 3 give the
associated boundary equations for the templates. The
XRT7295AT correctly decodes any transmitted signal
that meets one of these templates at the cross-connect.
Specification
Line Rate
44.736 Mbps ¦20 ppm
Line Code
Bipolar with three-0 substitution (B3ZS)
Test Load
75 W ¦5%
Pulse Shape
An isolated pulse must fit the template in NO TAG or Figure 5.1 The pulse amplitude may be scaled by
a constant factor to fit the template. The pulse amplitude must be between 0.36vpk and 0.85vpk,
measured at the center of the pulse.
Power Levels
For and all 1s transmitted pattern, the power at 22.368 ± 0.002MHz must be -1.8 to +5.7dBm, and
the power at 44.736 ±0.002MHz must be -21.8dBm to -14.3dBm.2, 3
Notes
1 The pulse template proposed by G.703 standards is shown in Figure 5 and specified in Table 3. The proposed G.703 standards
further state that the voltage in a time slot containing a 0 must not exceed ± 5% of the peak pulse amplitude, except for the residue
of preceding pulses.
2 The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands.
3 The all 1s pattern must be a pure all 1s signal, without framing or other control bits.
Table 1. DSX-3 Interconnection Specification
Lower Curve
Upper Curve
Time
Equation
Time
Equation
T ± -0.36
0
T±-0.68
0
-0.36 ± T ± +0.28
0.5 (1+sin {p/2}[1+T/0.18])
-0.68 ± T± +0.36
0.5 (1+sin {p/2} [1+T/0.34])
0.28 ± T
0.11e-3.42(T-0.3)
0.36 ± T
0.05 + 0.407e-1.84(T-0.36)
Table 2. DSX-3 Pulse Template Boundaries for ACCUNET T45 Standards (See Figure 4.)
Rev.1.20
7
XRT7295AT
Normalized Amplitude
1.0
0.8
0.6
0.4
0.2
0
-1.0
-0.5
0
0.5
1.0
1.5
2.0
Time Slots - Normalized To Peak Location
Figure 4. DSX-3 Isolated Pulse Template for ACCUNET T45 Standards
Lower Curve
Upper Curve
Time
Function
Time
Function
T± -0.36
0
T ± -0.65
0
-0.36 ± T±+0.28
0.5 (1+sin {p/2} [1+T/0.18])
-0.65 ± T± 0
1.05 1-e-4.6(T+0.65)
0.28 ± T
0.11e-3.42(T-0.3)
0 ± T ± 0.36
0.5 (1+sin {p/2} [1+T/0.34])
0.36 ± T
0.05+0.407e-1.84(T-0.36)
Table 3. DSX-3 Pulse Template Boundaries for G.703 Standards (See Figure 5)
Normalized Amplitude
1.0
0.8
0.6
0.4
0.2
0
-1.0
-0.5
0
0.5
1.0
1.5
Time Slots - Normalized To Peak Location
2.0
Figure 5. DSX-3 Isolated Pulse Template for G.703 Standards
Rev.1.20
8
XRT7295AT
STS-1 SIGNAL REQUIREMENTS AT THE STSX
Specification
Parameter
For STS-1 operation, the cross-connect is referred at the
STSX-1. Table 4 lists the signal requirements at the
STSX-1. Instead of the DS3 isolated pulse template, an
eye diagram mask is specified for STS-1 operation
(TA-TSY-000253). The XRT7295AT correctly decodes
any transmitted signal that meets the mask shown in
Figure 6 at the STSX-1.
Line Rate
51.84 Mbps
Line Code
Bipolar with three-0 substitution (B3ZS)
Test Load
75W±5%
Power Levels
A wide-band power level measurement
at the STSX-1 interface using a low-pass
filter with a 3dB cutoff frequency of at
least 200MHz is within -2.7 dBm and 4.7
dBm.
Table 4. STSX-1 Interconnection Specification
Normalized Amplitude
1.0
0.8
0.6
0.4
0.2
0
-1.0
-0.5
0
0.5
1.0
1.5
2.0
Time Slots - Normalized To Peak Location
Figure 6. STSX-1 Isolated Pulse Template for Bellcore TA-TSY-000253
The distribution frame jack may introduce 0.6 ±0.55 dB
of loss. This loss may be any combination of flat or
shaped (cable) loss.
LINE TERMINATION AND INPUT CAPACITANCE
The recommended receive termination is shown in
Figure 3 The 75 W resistor terminates the coaxial cable
with its characteristic impedance. The 0.01mF capacitor
to RIN couples the signal into the receive input without
disturbing the internally generated DC bias level present
on RIN. The input capacitance at the RIN pin is 2.8pF
typical.
The maximum cable distance between the point where
the transmitted signal exits the distribution frame jack and
the XRT7295AT device is 450 ft. (see Figure 2.) The
coaxial cable (Type 728A) used for specifying this
distance limitation has the loss and phase characteristics
shown in Figure 7 and Figure 8. Other cable types also
may be acceptable if distances are scaled to maintain
cable loss equivalent to Type 728A cable loss.
LOSS LIMITS FROM THE DSX-3 TO THE RECEIVE
INPUT
TIMING RECOVERY
External Loop Filter Capacitor
The signal at the cross-connect may travel through a
distribution frame, coaxial cable, connector, splitters, and
back planes before reaching the XRT7295AT device.
This section defines the maximum distribution frame and
cable loss from the cross-connect to the XRT7295AT
input.
Figure 3 shows the connection to an external 0.1mF
capacitor at the LPF1/LPF2 pins. This capacitor is part of
the PLL filter. A non-polarized, low-leakage capacitor
should be used. A ceramic capacitor with the value 0.1mF
± 20% is acceptable.
Rev.1.20
9
XRT7295AT
data pattern dependent jitter due to misequalization of the
input signal, all create jitter on RCLK. The magnitude of
this internally generated jitter is a function of the PLL
bandwidth, which in turn is a function of the input 1s
density. For higher 1s density, the amount of generated
jitter decreases. Generated jitter also depends on the
quality of the power supply bypassing networks used.
Figure 12 shows the suggested bypassing network, and
Table 5 lists the typical generated jitter performance.
OUTPUT JITTER
The total jitter appearing on the RCLK output during
normal operation consists of two components. First,
some jitter appears on RCLK because of jitter on the
incoming signal. (The next section discusses the jitter
transfer characteristic, which describes the relationship
between input and output jitter.) Second, noise sources
within the XRT7295AT device and noise sources that are
coupled into the device through the power supplies and
12
100
80
8
Phase (Degree)
Loss (dB)
10
6
4
40
20
2
0
60
1.0
2.0
5.0 10
20
Frequency (MHz)
50
0
100
Figure 7. Loss Characteristic of 728A
Coaxial Cable (450 ft.)
1.0
2.0
5.0 10 20
Frequency (MHz)
50 100
Figure 8. Phase Characteristic of 728A
Coaxial Cable (450 ft.)
JITTER TRANSFER CHARACTERISTIC
Parameter
Typ
Max
Unit
Generated Jitter1
The jitter transfer characteristic indicates the fraction of
input jitter that reaches the RCLK output as a function of
input jitter frequency. Table 5 shows Important jitter
transfer characteristic parameters. Figure 9 also shows a
typical characteristic, with the operating conditions as
described in Table 5. Although existing standards do not
specify jitter transfer characteristic requirements, the
XRT7295AT information is provided here to assist in
evaluation of the device.
All 1s pattern
1.0
ns peak-to-peak
Repetitive “100”
pattern
1.5
ns peak-to-peak
0.05
dB
205
kHz
Jitter Transfer
Characteristic2
Peaking
f 3dB
Notes
1 Repetitive input data pattern at nominal DSX-3 level with V
DD
= 5V TA = 25°C.
2 Repetitive “100 ” input at nominal DSX-3 level with V
DD = 5V,
TA = 25°C.
Table 5. Generated Jitter and Jitter Transfer
Characteristics
Rev.1.20
10
XRT7295AT
JITTER ACCOMMODATION
LOSS-OF-LOCK DETECTION
Under all allowable operating conditions, the jitter
accommodation of the XRT7295AT device exceeds all
system
requirements
for
error-free
operation
(BER<1E-9). The typical (VDD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XRT7295AT is shown in Figure 10.
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately ±0.5%.
FALSE-LOCK IMMUNITY
This will not occur until at least 250 bit periods after loss of
input data.
Magnitude Response (dB)
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XRT7295AT
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately ±0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
Peak-Peak Sinewave Jitter (U.I.)
If a valid input signal is assumed to be already present at
RIN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
1
PEAK = 0.05dB
0
-1
-2
f3dB = 205kHz
-3
-4
-5
100
500 1K
5K 10K
50K100K 500K
Frequency (Hz)
Figure 9. Typical PLL Jitter Transfer
Characteristic
TR-TSY-000499
Category 2
40
XRT7295AT Typical
TR-TSY-000499
Category 1
10
XRT7295AT Typical
G.824
PUB 54014
1.0
0.1
1
10
100
1K
10K
100K
1000K
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Rev.1.20
11
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)
5k
10k
60k
300k
1M
10
5
1
0.5
0.4
XRT7295AT
A high RLOL output indicates that the acquisition circuit is
working to bring the PLL into proper frequency lock.
RLOL remains high until frequency lock has occurred;
however, the minimum RLOL pulse width is 32 clock
cycles.
To allow for varying levels of noise and crosstalk in
different applications, three loss-of-signal threshold
settings are available using the LOSTHR pin. Setting
LOSTHR = VDD provides the lowest loss-of-signal
threshold; LOSTHR = VDD/2 (can be produced using two
50 kW ±10% resistors as a voltage divider between
VDDD and GNDD) provides an intermediate threshold;
and LOSTHR = GND provides the highest threshold. The
LOSTHR pin must be set to its desired value at power-up
and must not be changed during operation.
PHASE HITS
In response to a phase hit in the input data, the
XRT7295AT returns to error free operation in less than
2ms. During the requisition time, RLOS may temporarily
be indicated.
DIGITAL DETECTION
LOSS-OF-SIGNAL DETECTION
In addition to the signal amplitude monitoring of the
analog LOS detector, the digital LOS detector monitors
the recovered data 1s density. The RLOS alarm goes
high if 160 ±32 or more consecutive 0s occur in the
receive data stream. The alarm goes low when at least
ten 1s occur in a string of 32 consecutive bits. This
hysteresis prevents RLOS chattering and guarantees a
minimum RLOS pulse width of 32 clock cycles. Note,
however, that RLOS chatter can still occur. When
REQB=1, input signal levels above the analog RLOS
threshold can still be low enough to result in a high bit error
rate. The resultant data stream (containing) errors can
temporarily activate the digital LOS detector, and RLOS
chatter can occur. Therefore, RLOS should not be used
as a bit error rate monitor.
Figure 1 shows that analog and digital methods of
loss-of-signal (LOS) detection are combined to create the
RLOS alarm output. RLOS is set if either the analog or
digital detection circuitry indicates LOS has occurred.
ANALOG DETECTION
The analog LOS detector monitors the peak input signal
amplitude. RLOS makes a high-to-low transition (input
signal regained) when the input signal amplitude exceeds
the loss-of signal threshold defined in Table 6. The RLOS
low-to-high transition (input signal loss) occurs at a level
typically 1.0 dB below the high-to-low transition level. The
hysteresis prevents RLOS chattering. Once set, the
RLOS alarm remains high for at least 32 clock cycles,
allowing for system detection of a LOS condition without
the use of an external latch.
RLOS chatter can also occur when RLOL is activated
(high).
Rev.1.20
12
XRT7295AT
Data
Rate
REQB
LOSTHR
Min.
Threshold
Max.
Threshold
Unit
DS3
0
0
60
220
mV pk
VDD/2
40
145
mV pk
VDD
25
90
mV pk
1
STS-1
0
1
0
45
175
mV pk
VDD/2
30
115
mV pk
VDD
20
70
mV pk
0
75
275
mV pk
VDD/2
50
185
mV pk
VDD
30
115
mV pk
0
55
220
mV pk
VDD/2
35
145
mV pk
VDD
25
90
mV pk
Notes
- Lower threshold is 1.5 dB below upper threshold.
- The RLOS alarm is an indication of the absence of an input signal, not a bit error rate indication (independent of the RLOS state). The
device will attempt to recover correct timing data. The RLOS low-to-high transition typically occurs 1dB below the high to low transition.
Table 6. Analog Loss-of-Signal Thresholds
RECOVERED CLOCK AND DATA TIMING
IN-CIRCUIT TEST CAPABILITY
Table 7 and Figure 11 summarize the timing relationships
between the logic signals RCLK, RPDATA, and RNDATA.
The duty cycle is referenced to VDD/2 threshold level.
RPDATA and RNDATA change on the rising edge of
RCLK and are valid during the falling edge of RCLK. A
positive pulse at RIN creates a high level on RPDATA and
a low level on RNDATA. A negative pulse at the input
creates a high level on RNDATA and a low level on
RPDATA, and a received zero produces low levels on
both RPDATA and RNDATA.
When pulled low, the ICT pin forces all digital output
buffers (RCLK, RPDATA, RNDATA, RLOS, RLOL pins) to
be placed in a high output impedance state. This feature
allows in-circuit testing to be done on neighboring devices
without concern for XRT7295AT device buffer damage.
An internal pull-up device (nominally 50kW) is provided on
this pin therefore, users can leave this pin unconnected
for normal operation. Test equipment can pull ICT low
during in-circuit testing without damaging the device.
This is the only pin for which internal pull-up/pull-down is
provided.
Rev.1.20
13
XRT7295AT
TIMING CHARACTERISTICS
Test Conditions: All Timing Characteristics are Measrured with 10pF Loading, -40°C ± TA ± +85°C, VDD =
5V ±10%
Symbol
Parameter
Min
Typ
Max
Unit
tRCH1RCH2
Clock Rise Time (10% - 90%)
4
ns
tRCL2RCL1
Clock Fall Time (10% - 90%)
4
ns
3.7
ns
55
%
tRCHRDV
Receive Propagation
Delay1
0.6
Clock Duty Cycle
45
50
Table 7. System Interface Timing Characteristics
tRCHRDV
RCLK
(RC)
tRCL2RCL1
tRCH1RCH2
tRDVRCL
RPDATA
OR
RNDATA
(RD)
tRCLRDX
Figure 11. Timing Diagram for System Interface
input pin. Any noise coupled into the XRT7295AT input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.
BOARD LAYOUT CONSIDERATIONS
Power Supply Bypassing
PLL Filter Capacitor
Figure 12 illustrates the recommended power supply
bypassing network. A 0.1mF capacitor bypasses the
digital supplies. The analog supply VDDA is bypassed by
using a 0.1mF capacitor and a shield bead that removes
significant amounts of high-frequency noise generated by
the system and by the device logic. Good quality,
high-frequency (low lead inductance) capacitors should
be used. Finally, it is most important that all ground
connections be made to a low-impedance ground plane.
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible. The LPF1
and LPF2 pins are adjacent, allowing for short lead
lengths with no crossovers to the external capacitor.
Noise-coupling into the LPF1 and LPF2 pins may
degrade PLL performance.
Handling Precautions
Receive Input
Although protection circuitry has been designed into this
device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during
handling and mounting.
The connections to the receive input pin, RIN, must be
carefully considered. Noise-coupling must be minimized
along the path from the signal entering the board to the
Rev.1.20
14
XRT7295AT
COMPLIANCE SPECIFICATIONS
C4
0.1mF
GNDA
VDDA
XRT7295AT
GNDD
D Compliance with AT&T Publication 54014, “ACCUNET R T45 Service Description and Interface Specifications,” June 1987.
Sensitive Node
D Compliance with ANSI Standard T1.102-1989,
“Digital Hierarchy - Electrical Interfaces, ” 1989.
Shield Bead1
D Compliance with Compatibility Bulletin 119,
“Interconnection Specification for Digital
Cross-Connects,” October 1979.
VDDC
GNDC
VDDD
0.1mF
+5V
D Compliance with CCITT Recommendations G.703
and G.824, 1988.
C6
Notes
1 Recommended shield beads are the Fair-Rite
2643000101 or the Fair-Rite 2743019446 (surface
mount).
D Compliance with TR-TSY-000499, “Transport Systems Generic Requirements (TSGR): Common Requirements,” December 1988.
D Compliance with TA-TSY-000253, “Synchronous
Optical Network (SONET) Transport System Generic Criteria,” February 1990.
Figure 12. Recommended Power Supply
Bypassing Network
Rev.1.20
15
XRT7295AT
VCC
OUTPUTS
RECEIVER
MONITOR
RLOS
R I
E C
Q T
B
5 6 7 8
S1
SW DIP-4
RLOL
TP
4 3 2 1
U1
XRT7295AT
8
B1
C2
7
2
LOSTHR
REQB
ICT/
RCLK
RNDATA
RPDATA
RLOL
RLOS
RIN
R2
2 1 3 4 5 6 7 8
R21
22K
3
13
R7
R8
R10
39
39
39
1
28
27
RCLK
RNDATA
RPDATA
4
R6
75
5
R5
50
V
D
D
C
20
BT1
FERRITE BEAD
1
2
B5
9
TCLK
RPOS
TCLK
RNEG
RNRZ
8
TNDATA
V
D
D
D
TRING
C6
7
TPDATA
0.1mF
MRING
MTIP
GNDD
P1
18
DMO
13
BPV
VCC RX
C7
0.1mF
9
DECODIS
17
RCLKO
16
RPOS
15
RNEG
14
RECEIVER
OUTPUTS
RNRZ
+ E1
22mF
TRANSMITER
MONITOR
OUTPUTS
R4
22
36
B6
T1
DMO
GNDA
BPV
V
D
D
A
24
V
D
D
D
R3
23
R15
270
R16
270
PE65966
19
20
TRING
36
10
21
TRANSFORMER # PULSE ENGINEERING
PE 65966
PE 65967 IN SURFACE MOUNT
BT2
6
C8
0.1mF
P3
VCC TX
C9
FERRITE BEAD # FAIR RITE 2643000101
FERRITE BEAD
0.1mF
Figure 13. Typical Application Schematic
Rev.1.20
16
TTIP
TPDATA
TTIP
C4
0.1mF
7
8
LLOOP
RLOOP
T3/E3
TAOS
TXLEV
ICT
ENCODIS
TNDATA
B3
1
1
16
15
14
13
12
11
10
B4
LPF2
V
D
D
A
S2
1
2
3
4
5
6
SW DIP-8
RCLKO
9
GNDD
3
2
4
5
26
25
11
12
GND
10
GNDC
C3
0.1mF
50
1
GNDA
LPF1
R1
P2
RLOOP
DS3,STS-1/E3/
TAOS
ICT/
TXLEV
ENCODIS
DECODIS
6
TMC2
EXCLK
1 1 1 1 1 1 1 9
5 64 3 2 1 0
LLOOP
0.01mF
TMC1
R22
22K
U2
XRT7296
24 6 8
19
18
17
14
15
16
75
EXTERNAL
CLOCK
B2
VCC
1 3 5 7
TP
INPUT
SIGNAL
L
O
S
T
H
R
+E2
22mF
C5
0.1mF
XRT7295AT
20 LEAD SMALL OUTLINE J LEAD
(300 MIL JEDEC SOJ)
Rev. 1.00
D
20
11
E
H
1
10
A2
Seating
Plane
e
B
A1
INCHES
SYMBOL
A
A
C
R
E1
MILLIMETERS
MIN
MAX
MIN
0.145
0.200
3.60
MAX
5.08
A1
0.025
---
0.64
---
A2
0.120
0.140
3.05
3.56
B
0.014
0.020
0.36
0.51
C
0.008
0.013
0.20
0.30
D
0.496
0.512
12.60
13.00
E
0.292
0.300
7.42
7.62
E1
0.262
0.272
6.65
6.91
e
0.050 BSC
1.27 BSC
H
0.335
0.347
8.51
8.81
R
0.030
0.040
0.76
1.02
Note: The control dimension is the inch column
Rev.1.20
17
XRT7295AT
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2000 EXAR Corporation
Datasheete December 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev.1.20
18