VP-1608F Digital Voice Pr ocessor Processor FEA TURES FEATURES ! Plays messages stored in external EPROM chips ! CVSD technique with adjustable sampling rate from 16K to 128K bps for different voice quality ! Dual-channel audio output ! Up to 64 segments per channel ! Built-in RC oscillator or use external clock GENERAL DESCRIPTIONS The VP-1608F is a CMOS voice processor chip based on the CVSD (Continuously Variable Slope Delta) modulation technique. The VP-1608F is exactly the same as the (now obsolete) VP-1608 except that it is packaged in 64-pin QFP instead of 68-pin PLCC. Note that although the dual channel output provided by the VP-1608F can be used as a stereo output, it will be hard to do so since the VP-880 Voice Development System does not allow voice digitization in stereo mode. VP-1608F (QFP44) Pin Assignment ! ! ! ! Direct EPROM addressing up to 8M bits Low power, single voltage operation Microprocessor interface Low-cost VP-880 system available for quick and easy voice development Therefore the dual channel output is usually used in applications where sound synchronization is not critical. For example, in a game equipment, channel A can be playing a continuous background sound while channel B plays short sound effects based on the player’s action. The dual channel output is available on two separate output pins. They can be used independently, or mixed together externally. Each channel may control up to 64 sound segments stored in 4 different EPROM banks, with up to 16 segments in each bank. Each segment stored in the EPROM is represented by a unique binary code: 2 bits for the bank code and 4 bits for the segment code. A valid code plus a strobe signal are all it takes to activate a certain segment. The VP-1608F can operate in a wide range of sampling rates (from 16 to 128 Kbps). A higher sampling rate usually produces better sound quality at the expense of higher memory cost. As a rule of thumb, start with 32 Kbps. A 1M EPROM can store 32 seconds of sound at this rate. Thanks to the chip’s high internal integration, very little external components are required to build a VP-1608F based design. The VP-880 Voice Development System is available for quick and easy in-house voice development. APPLICATIONS ! Dual channel, multiple message playback ! Sound effects generator ! Digital announcer for consumer, industrial, security and telecommunication products Eletech Enterprise Co., Ltd. 531-3F Chung-Cheng Road Hsin Tien, Taipei Hsien, Taiwan Tel:+886 2-2218-0068 Fax:+886 2-2218-0254 www.eletech.com Eletech Electronics, Inc. 16025 Kaplan Avenue Industry, CA 91744, U.S.A. Tel: (626) 333-6394 Fax: (626) 333-6494 ABSOLUTE MAXIMUM RATINGS* Supply Voltage, VCC - VDS .................................. 0 to 5.5V Input Volotage, VIN ........................................... VDS to VCC Operating Temperature, TOP ...................... -10oC to 60oC Storage Temperature, TST .......................... -20oC to 80oC * Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ELECTRICAL CHARACTERISTICS Symbol Parameter VCC IDD Supply Voltage Standby Current IDRIVE ISINK Output Current VOH=2.4V Output Current VOL=0.4V Min. Typ. Max. Units 4.5 5 50 5.5 V uA 4 4 mA mA VIH VIL Input Voltage (High) Input Voltage (Low) 3.5 1.5 V V FC FS Internal Scan Clock Sampling Clock 8 32 MHz KHz 20 128 TRESET TSI Reset Pulse Width Strobe Input Pulse Width TSIE TDSP Strobe Inhibit Time After EOS (1) Delay Time From Strobe To Play TRP TDS Edge-Triggered Reset Interval Data Setup Time For INA ~ INF 1 TDH TDL Data Hold Time For INA ~ INF Internal Load Pulse For INA ~ INF 1 65 us ns Address Valid Time For Ch. B EPROM Internal Latch Pulse For Ch. B EPROM Data 250 65 ns ns TECS TREAD TAH Address Stable Time For Ch. B 1 1 us us 1.5 150 ms ms 350 us ns (2) 125 ns Note: (1) EOS = End-Of-Speech (2) Based on 1M EPROM scanning. VOICE VP-1608..........................................................................................2 TIMING DIAGRAM STROBE SPEECH ACTIVE TSI TDSP TSIE TDSP BUSY TRP RESET FC INTERNAL TIMING CLOCK STROBE INA ~ INF INTERNAL LATCH CLOCK TDS INTERNAL LOAD CLOCK TDH TDL FC ADDRESS TECS ECS LATCH CLOCK FOR CHB DATA (INTERNAL) TREAD TAH TEST CIRCUIT FOR I/O PIN STROBE BUSY I/O VP-1608 VOICE VP-1608..........................................................................................3 PIN DESCRIPTIONS A0 ~ A19: Address output to EPROM. Both channels share the same address lines in a 50-50 time sharing fashion. Pin ECS (described below) must be examined to tell who's address is valid at any particular moment. ANG1 & ANG1\: Differential audio output for channel A, connect to LM324 or LM358. ANG2 & ANG2\: Differential audio output for channel B, connect to LM324 or LM358. ANGD1: Audio feedback input for channel A. D0 ~ D7: Data input from EPROM. ECS: EPROM Channel Select output. This signal is used to indicate who's address is on the address lines. When the ECS is low, the address is for channel A. When the ECS is high, the address is for channel B. If both channels share one EPROM, this signal is usually connected to the highest address line so that each channel uses exactly half the EPROM space. If more than one EPROM are used, this signal is usually used by the address decoder to select the proper EPROM. ENV1: Envelop input for channel A, to be connected to INT1 with a feedback resistor. ANGD2: Audio feedback input for channel B. Block Diagram I/O1 RESET1 INA ~ IND INE, INF SE, SF CHA SEGMENT CONTROL BANK CONTROL CHB SEGMENT CONTROL I/O2 RESET2 VCC VDS VAS CHA & CHB TIME SHARING CIRCUIT CHA CVSD DEMODULATOR ANGD1 ANG1 ANG1 ENV1 INT1 CHA FLAG RECEIVER CHB FLAG RECEIVER CHB CVSD DEMODULATOR D0 ~ D7 ANGD2 ANG2 ANG2 ENV2 INT2 ECS OSC1 & OSC2 CHA CLOCK & ADDRESS GENERATOR HIGH SPEED SPINNER ADDRESS MULTIPLEXER A0 ~ A19 CHB CLOCK & ADDRESS GENERATOR VOICE VP-1608..........................................................................................4 ENV2: Envelop input for channel B, to be connected to INT2 with a feedback resistor. INT1: Integrator output for channel A, to be connected to an external RC integration circuitry. INT2: Integrator output for channel B, to be connected to an external RC integration circuitry. I/O1: Strobe input/Busy output for channel A, active low. To play a message on channel A, place the segment/bank code on INA to INE and strobe this pin with a low pulse. During the playback this pin becomes an active-low "busy" output. If this pin is held low at the end of playback, the message will be re-triggered. I/O2: Same as I/O1 except that this pin is for channel B. INA ~ IND: Input for segment code in binary format. INA is the LSB and IND is the MSB. INE, INF: Input for bank code in binary format, max. 4 banks. INE is the LSB and INF is the MSB. OSC1, OSC2: Internal oscillator pins for external RC components. It external clock source is to be used, feed it through the OSC2 pin. Note that both channels share the same clock, so their sampling rate must be the same. RESET1: Reset input for channel A, active low. On the falling edge of this reset signal, channel A playback is stopped and all internal counters for channel A are cleared. RESET2: Reset input for channel B, active low. On the falling edge of this reset signal, channel B playback is stopped and all internal counters for channel B are cleared. SCK, TEST: For factory use only, do not make any connection. SE, SF: Output for EPROM bank select. These two pins are actually latched outputs for INE and INF. VDD: Input, supply voltage. VDS & VAS: VDS is digital ground and VAS is analog ground. Connect the two grounds together close to the power source to minimize noise. APPLICATION NOTES 1. EOM (End Of Message) Flag The EOM flag consists of six consecutive bytes of "AA", or "10101010" in binary format. After a trigger signal is received, the VP-1608 uses the internal 8MHz system clock to scan through memory space and finds the correct message by counting the number of EOM flags. For example, to find the 5th message, it must scan through each and every memory location until it finds 4 EOM flags. The first byte following the 4th EOM flag is the first byte of the 5th message. 2. Creating Master EPROM File on the VP-880 System Follow these steps to create the master EPROM file: 1. To maximize the EPROM usage, arrange your sound segments in banks of 16 or less, so that the total combined length for each bank is about the same. Do not mix channel A and channel B together. 2. Based on the total combined length of the largest bank, select a highest sampling rate that will fully utilize the EPROM. Use the following equation: Sampling Rate (Kbps) = EPROM Size (K-bits) / Total Length (Second) 3. Digitize and edit each segment as a separate file. Use the "ROM Data Management" function to combine up to 16 messages into a "bank file". The first filename entered in the "ROM Data Management" is the first segment in that bank, and etc. 4. Depending on the hardware design, each EPROM chip may contain one or more sound banks. It is also possible to use just one EPROM to store all sound segments of both channel A and channel B. If you need to combine several bank files into one for programming into one EPROM chip, use the following DOS command: COPY /b file_1+file_2+..+file_n destination_file Do not use the "ROM Data Management" function to combine bank files, otherwise each bank file will be considered as a single message file. VOICE VP-1608..........................................................................................5 5 4 3 2 1 D D +5V +5V VP1608F RESET1 36 RESET2 13 INT1 15 ENV1 3K + 1uF 14 34 30 28 26 24 25 27 29 21 20 19 18 17 15 14 13 D7 D6 D5 D4 D3 D2 D1 D0 SE SF ECS 55 56 57 30 31 1 A17 A18 A19 INT2 ANG1 1uF 16 CE 24 CS 22 GND 16 LM324 240 ENV2 12 ANG1 9 2 33K 3 472 20 OSC2 ANGD1 21 ANG2 10 6 240 5 VAS ANG2 11 61 VDS ANGD2 23 9 33K 33K 7 10 472 472 220uF 1 U19 LM324 104 6 LS1 VC VR 50K +5V LM324 22 472 + OSC1 - VR 500K 19 33K 14 390K B +5V 8 13 + C 11 3K D7 D6 D5 D4 D3 D2 D1 D0 32 3 IN- 7 BP OUT 5 GAIN 8 LM324 472 10uF 2 4 104 B SPEAKER + 8 + 7 VCC 4 I/O2 C A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 + 60 1N4148 2 3 29 28 4 25 23 26 27 5 6 7 8 9 10 11 12 - I/O1 52 50 49 47 48 41 38 43 45 46 44 42 40 39 37 35 33 + 59 1N4148 TO EXTERNAL CONTROLLER A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 - INA INB INC IND INE INF + VCC 1 2 3 4 5 6 - 58 27C080 10 IN+ GND GAIN 1 LM386-3 A A 5 4 3 2 1