DS1075 DS1075 EconOscillator/Divider FEATURES PIN ASSIGNMENT • Dual Fixed frequency outputs (200 KHz – 100 MHz) • User–programmable on–chip dividers (from 1 – 513) • User–programmable on–chip prescaler (1, 2, 4) • No external components I/O 1 8 OSCIN OUT0 2 7 XTAL VCC 3 6 OE GND 4 5 PDN/SELX DS1075Z 150–MIL SOIC DS1075M 300–MIL DIP • ±0.5% Initial tolerance • ±1% variation over temperature and voltage • Internal clock, External clock or crystal reference options • Single 5V supply • Power–down mode • Synchronous output gating FREQUENCY OPTIONS Part No. DS1075–100 DS1075–80 DS1075–66 DS1075–60 Max O/P freq. 100 MHz 80 MHz 66 MHz 60 MHz DESCRIPTION The DS1075 is a fixed frequency oscillator requiring no external components for operation. Numerous operating frequencies are possible in the range 0.2 to 100 MHz through the use of an on–chip programmable prescaler and divider. grammed devices can be ordered on a custom basis as DS1075C–xxx. As alternatives to the on–board oscillator an external clock signal or a crystal may be used as a reference. The choice of reference source (internal or external) is user–selectable at the time of programming (or on the fly if the SEL mode is chosen). The DS1075 features a master oscillator followed by a prescaler and then a programmable divider. The prescaler and programmable divider are user–programmable with the desired values being stored in non–volatile memory. This allows the user to buy an off the shelf component and program it on site prior to board production. Design changes can be readily accommodated by programming, or reprogramming, the desired values into the on–chip non–volatile registers. An evaluation board, DS1075K is available to simplify this task. The DS1075 features a dual–purpose Input/Output pin. If the device is powered up in Program mode this pin can be used to input serial data to the on chip registers. After a Write command this data is stored in non–volatile memory. When the chip is subsequently powered up in operating mode these values are automatically restored to the on–chip registers and the Input/Output pin becomes the oscillator output. The DS1075 is shipped from the factory configured for half the maximum operating frequency. Pre–pro- The DS1075 is available in 8–pin DIP or SOIC packages, allowing the generation of a clock signal easily, economically and using minimal board area. Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 101697 1/16 DS1075 BLOCK DIAGRAM Figure 1 PART NO. SUFFIX INTOSC FREQUENCY 100 MHz 80 MHz 66 MHz 60 MHz –100 –80 –66 –60 en INTERNAL OSCILLATOR OSCIN en INTOSC XTAL ÷M M rst sel MSEL INTCLK sel EN0 9 CONTROL LOGIC EEPROM E/I EXTCLK en OUT0 en en MCLK 9 PROGRAMMABLE DIVIDER ÷N N rst DIV1 sel en PDN pden OUTPUT ENABLE ENABLING SEQUENCER PDN/SELX POWER ON RESET IN/OUT en I/O CONT. SIGNAL PATH 101697 2/16 CONTROL PATH BUS DS1075 PIN DESCRIPTIONS Input/Output Pin (IN/OUT): This pin is the main oscillator output, with a frequency determined by clock reference, M and N dividers. Except in programming mode this pin is always an output and will be referred to as “OUT”. In programming mode this pin will be referred to as “IN”. External Oscillator Input (OSCIN): This pin can be used to supply an external reference frequency to the device. Crystal Oscillator Connection (XTAL): A crystal can be connected between this pin and OSCIN to provide an alternative frequency reference. If a crystal is not used this pin should be left open. Output Enable Function (OE pin): The DS1075 also features a “synchronous” output enable. When OE is at a high logic level the oscillator free runs. When this pin is taken low OUT is held low, immediately if OUT is already low, or at it’s next high–to–low transition if OUT is high. This prevents any possible truncation of the output pulse width when the enable is used. While the output is disabled the master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internal counters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level and the resulting OUT signal. When the enable is released OUT will make its first transition within one to two clock periods of the master clock. Power–Down/Select Function (PDN/SELX pin): The Power–Down/Select (PDN/SELX) pin has a user–selectable function determined by one bit (PDN bit) of the user–programmable memory. According to which function is selected, this pin will be referred to as PDN or SELX. If the Power–Down function is selected (PDN bit = 1) a low logic level on this pin can be used to make the device stop oscillating (active low) and go into a reduced power consumption state. The “Enabling Sequencer” circuitry will first disable OUT in the same way as when OE is used. Next OUT0 will be disabled in a similar fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs will go into a high impedance state. The power consumption in the power–down state is much less than if OE is used because the internal oscillator (if used) is completely powered down. Even if an external reference or a crystal is used all of the on–chip buffers are powered down to minimize current drain. Consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a power–down condition than if the OE is used. If the Select function is chosen (PDN bit = 0) this pin can be used to switch between the internal oscillator and an external reference (or crystal) on the fly. When this mode is chosen the E/I select bit is overridden, a high logic level on SELX will select the internal oscillator, a low logic level will select the external reference (or crystal oscillator). Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the reference select mux. This output is especially useful as a buffered output of a crystal defined master frequency. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is powered down. If this output is not required it can be permanently disabled by setting the EN0 bit to one, and there will be a corresponding reduction in overall power consumption. USER–PROGRAMMABLE REGISTERS The following registers can be programmed by the user to determine operating frequency and mode of operation. Details of how these registers are programmed can be found in a later section, in this section the function of the registers are described. The register settings are non–volatile, the values being stored automatically in EEPROM when the registers are programmed. Note: The register bits cannot be used to make mode or frequency changes on the fly. Changes can only be made by powering the device up in “Programming” mode. For them to be become effective the device must then be powered down and powered up again in “Operation” mode. For programming purposes the register bits are divided into two 9–bit words, the “MUX” word determines mode of operation and prescaler values. The “DIV” word sets the value of the programmable divider. 101697 3/16 DS1075 MUX WORD Figure 2 (MSB) (LSB) 0* 0* 0* EN0 PDN M MSEL DIV1 E/I * These bits must be set to zero 0=Internal Oscillator E/I This bit selects either the internal oscillator or the exterhowever, if the PDN bit is set to zero the E/I bit will be nal/crystal reference. overridden by the logic level on the PDN/SELX pin. 1=External/Crystal Table 1 PDN BIT E/I PDN/SELX PIN OSCILLATOR MODE 0 X 0 EXTERNAL/CRYSTAL 0 X 1 INTERNAL 1 X 0 POWER–DOWN 1 0 1 INTERNAL 1 1 1 EXTERNAL/CRYSTAL DIV1 MSEL This bit allows the master clock to be routed directly to the output (DIV1=1). The N programmable divider is bypassed so the programmed value of N is ignored. The frequency of the output (fOUT) will be INTCLK or EXTCLK depending on which reference has been selected. If the Internal clock is selected the M prescaler is also bypassed (the bit values of MSEL and M are ignored) so in this case fOUT=INTOSC (which also equals MCLK and INTCLK). If DIV1=0 the prescaler and programmable divider function normally. This bit determines whether or not the M prescaler is bypassed. MSEL=1 will bypass the prescaler. MSEL=0 will switch in the prescaler (unless overridden by DIV1=1), with a divide–by number determined by the M bit. M This bit sets the divide–by number for the prescaler. M=0 results in divide–by–4, M=1 results in divide–by–2. The setting of this bit is irrelevant if either DIV1=1 or MSEL=1. Table 2 DIV1 BIT E/I BIT* MSEL BIT M BIT 0 0 0 0 INTERNAL OSCILLATOR DIVIDED BY 4*N 0 0 0 1 INTERNAL OSCILLATOR DIVIDED BY 2*N 0 0 1 X INTERNAL OSCILLATOR DIVIDED BY N 0 1 X X EXTERNAL OSCILLATOR DIVIDED BY N 1 0 X X INTERNAL OSCILLATOR DIVIDED BY 1 1 1 X X EXTERNAL OSCILLATOR DIVIDED BY 1 OPERATION *Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN/SELX pin. DIV WORD Figure 3 (MSB) (LSB) N (9–BITS) 101697 4/16 DS1075 PDN This bit is used to determine the function of the PDN/ SELX pin. If PDN=0, the PDN/SELX pin can be used to determine the timing reference (either the internal oscillator or an external reference/crystal). If PDN=1, the PDN/SELX pin is used to put the device into power– down mode. INTOSC/(M*N) must be greater than fOUTmin; if the external clock is selected, EXTCLK/N must be greater than fOUTmin. (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed fOUTmin). OPERATION OF OUTPUT ENABLE This bit is used to determine whether the OUT0 pin is active or not. If EN0 =1, OUT0 is disabled (High–impedance). If EN0=0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no effect on OUT0, but OUT0 is disabled as part of the power–down sequence. Since the output enable, internal master oscillator and/or external master oscillator are likely all asynchronous there is the possibility of timing difficulties in the application. To minimize these difficulties the DS1075 features an “enabling sequencer” to produce predictable results when the device is enabled and disabled. In particular the output gating is configured so that truncated output pulses can never be produced. N Enable timing These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to 513, and is equal to the programmed value of N plus 2: The output enable function is produced by sampling the OE input with the output from the prescaler mux (MCLK) and gating this with the output from the programmable divider. The exact behavior of the device is therefore dependent on the setup time (tSU) from a transition on the OE input to the rising edge of MCLK. If the actual setup time is less than tSUEM then one more complete cycle of MCLK will be required to complete the enable or disable operation (see diagrams). This is unlikely to be of any consequence in most applications, and then only if the value for N is small. In general, the output will make its first positive transition between approximately one and two clock periods of MCLK after the rising edge of OE. EN0 Table 3 BIT VALUES DIVISOR (N) VALUE 000000000 000000001 . . . . . 111111111 2 3 . . . . . 513 NOTE: The maximum value of N is constrained by the minimum output frequency. If the internal clock is selected, FIGURE 4 tM MCLK tM = PERIOD OF MCLK td = PROP DELAY FROM MCLK ↑ TO OUT ↑ OE MAX VALUE OF ten = tSUEM + 2 tM + td MIN VALUE OF ten = tSUEM + tM + td tSU td OUT ten 101697 5/16 DS1075 Disable Timing If OE goes low while OUT is high, the output will be disabled on the completion of the output pulse. If OUT is low, the disabling behavior will be dependent on the setup time between the falling edge of OE and the rising edge of MCLK. If tSU < tSUEM the result will be one additional pulse appearing on the output before disabling occurs. If the device is in divide–by–one mode, the disabling occurs slightly differently. In this case if tSU > tSUEM one additional output pulse will appear, if tSU < tSUEM then two additional output pulses will appear. The following diagrams illustrate the timing in each of these cases. Figure 5 N≥2 tM MCLK OE tM = PERIOD OF MCLK td = PROP DELAY FROM MCLK ↑ TO OUT ↑ tOUTH = WIDTH OF OUTPUT PULSE tSU MAX VALUE OF tdis = tSUEM + td + tOUTH MIN VALUE OF tdis = 0 td OUT tOUTH tdis Figure 6 N=1 tM MCLK OE tM = PERIOD OF MCLK td = PROP DELAY FROM MCLK ↑ TO OUT ↑ tOUTH = WIDTH OF OUTPUT PULSE tSU MAX VALUE OF tdis = tSUEM + td + tOUTH + tM MIN VALUE OF tdis = tSUEM + td + tOUTH td OUT tOUTH tdis SELECT TIMING If the PDN bit is set to “0”, the PDN/SELX pin can be used to switch between the internal oscillator and an external or crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs in a glitch–free fashion. Two asynchronous clock signals are involved, INTCLK is the internal reference oscillator 101697 6/16 divided by one or whatever value of M is selected. EXTCLK is the clock signal fed into the OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The behavior of OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will be divided by N. DS1075 From Internal to External clock This is accomplished by a high to low transition on the SELX pin. This transition is detected on the falling edge of INTCLK. The output OUT0 will be held low for a mini- mum of half the period of INTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the switching will not occur until EXTCLK returns to a low level. Figure 7 SELX tI tE OUT0 tLOW tI = PERIOD OF INTERNAL CLOCK tE = PERIOD OF EXTERNAL CLOCK tSIE Depending on the relative timing of the SELX signal and the internal clock, there may be up to one full cycle of tI on the output after the falling edge of SELX. Then, the “low” time (tLOW) between output pulses will be dependent on the relative timing between tI and tE. The time interval between the falling edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and minimum values of these parameters are: tLOW (min) = tI/2 tLOW (max) = tI/2 + tE tSIE (min) = tI/2 tSIE (max) = 3tI/2 + tE From External to Internal clock This is accomplished by a low to high transition on the SELX pin. In this case the switch is level triggered, to allow for the possibility of a clock signal not being present at OSCIN. Note therefore, that if a constant high– level signal is applied to OSCIN it will not be possible to switch over to the internal reference. (Level triggering was not employed for the switch from internal to external reference as this approach is slower and the internal clock may be running at a much higher frequency than the maximum allowed external clock rate). When SELX is high and a low level is sensed on EXTCLK, OUT0 will be held low until a falling edge occurs on INTCLK, then the next rising edge of INTCLK will be routed through to OUT0. NOTE: In each case there will be a small additional delay due to internal propagation delays. Figure 8 SELX tE tLOW tI OUT0 tSEI tElow tEhigh Depending on the relative timing of the SELX signal and the external clock, there may be up to one full tEhigh period on the output after the rising edge of SELX. Then, the “low” time (tLOW) between output pulses will be dependent on the relative timing between tI and tE. The tI = PERIOD OF INTERNAL CLOCK tE = PERIOD OF EXTERNAL CLOCK = tElow + tEhigh time interval between the falling edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and minimum values of these parameters are: 101697 7/16 DS1075 3. Disable MCLK (and OUT0 if EN0 bit = 0), switch OUT0 to high impedance state. tLOW (min) = tI/2 tLOW (max) = 3tI/2 + tElow tSEI (min) = tI/2 tSEI (max) = 3tI/2 + tEhigh 4. Disable internal oscillator and OSCIN buffer. NOTE: In each case there will be a small additional delay due to internal propagation delays. Power–UP When PDN is taken to a high level the following power– up sequence occurs: 1. Enable internal oscillator and/or OSCIN buffer. POWER–DOWN CONTROL 2. Set M and N to maximum values. If the PDN bit is set to “1”, the PDN/SELX pin can be used to power–down the device. If PDN is high the device will run normally. 3. Wait approximately 256 cycles of MCLK for it to stabilize. Power–Down If PDN is taken low a power–down sequence is initiated. The “Enabling Sequencer” is used to execute events in the following sequence: 4. Reset M and N to programmed values. 5. Enable OUT0 (assuming EN0 bit = 0). 6. Enable OUT. Steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs. 1. Disable OUT (same sequence as when OE is used) and reset N counters. 2. When OUT is low, switch OUT to high–impedance state. Figure 9 PDN Hi–Z OUT tdis tstab Hi–Z OUT0 tpdn POWER–ON RESET When power is initially applied to the device supply pin, a power–on reset sequence is executed, similar to that which occurs when the device is restored from a power– down condition. This sequence comprises two stages, first a conventional POR to initialize all on–chip circuitry, followed by a stabilization period to allow the oscillator to reach a stable frequency before enabling the outputs: 1. Initialize internal circuitry. 2. Enable internal oscillator and/or OSCIN buffer. 101697 8/16 3. Set M and N to maximum values. 4. Wait approximately 256 cycles of MCLK for the oscillator to stabilize. 5. Load M and N programmed values from EEPROM. 6. Enable OUT0 (assuming EN0=0). 7. Enable OUT. DS1075 Figure 10 VCC OUT tpor tstab OUT0 for programming is a variant of the 1–WireTM protocol used on a number of Dallas Semiconductor products. PROGRAMMING Normally when power is applied to the supply voltage pin the device will enter its normal operating mode following the power–on reset sequence. However the device can be made to enter a programming mode if a pull–up resistor is connected between IN/OUT and the supply voltage pin, prior to power–up. The method used HARDWARE The hardware configuration is shown in the diagram. A bus master is used to read and write data to the DS1075’s internal registers. The bus master may have either an open–drain or TTL–type architecture. Figure 11 VDD A) OPEN DRAIN BUS MASTER DS1075 1–WIRE PORT 5KΩ OPEN DRAIN PORT PIN RX DATA RX TX RX = RECEIVE TX = TRANSMIT TX 5 µA TYP. 100Ω MOSFET B) STANDARD TTL BUS MASTER TTL–EQUIVALENT PORT PINS VDD 5KΩ RX TO IN/OUT OF DS1075 TX 5KΩ Programming mode is entered by simply powering up the DS1075 with a pull–up of approximately 5KΩ. This will pull the IN/OUT pin above VIH on power–up and initiate the programming mode, causing the DS1075 to internally release the IN/OUT pin (after tPOR), and allow the pullup resistor to pull the pin to the supply rail and await the Master Tx Reset pulse (see diagram). NOTE: To ensure normal operation any external pull–up applied to IN/OUT must be greater than 20KΩ in value. This will cause the IN/OUT pin to remain below VIH on power–up, resulting in normal operation at the end of tSTAB. 101697 9/16 DS1075 Figure 12 +5V VCC PROGRAM (PULL–UP) +5V tpor FIRST MASTER TX RESET PULSE VOH VIH IN/OUT OSCILLATE (NO PULL–UP) tstab tpor TRANSACTION SEQUENCE INITIALIZATION The sequence for accessing the DS1075 via the 1–Wire port is as follows: Initialization Function Command Transaction/Data All transactions on the 1–Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the DS1075. The presence pulse lets the bus master know that the DS1075 is present and is ready to operate. Figure 13 MASTER TX ‘RESET PULSE’ DS1075 ‘PRESENCE PULSE’ tRSTH VPULLUP VPULLUP MIN VIH MIN VIL MAX 0V tRSTL tPDL tR tPDH RESISTOR MASTER DS1075 480 µs < tRSTL < 960 µs 480 µs < tRSTH < 960 µs 15 µs < tPDH < 60 µs 60 µs < tPDL < 240 µs FUNCTION COMMANDS Write MUX Register [02H] Once the bus master has detected a presence, it can issue one of the four function commands. All Function Commands are eight bits long, and are written lsb first. A list of these commands follows: This command allows the bus master to write to the DS1075’s MUX register. Write DIV Register [01H] This command allows the bus master to write to the DS1075’s DIV register. Read DIV Register [A1H] This command allows the bus master to read the DS1075’s DIV register. 101697 10/16 Read MUX Register [A2H] This command allows the bus master to read the DS1075’s MUX register. TRANSACTION/DATA Immediately following the Function Command, the nine data bits are written to or read from the DS1075. This data is written/read lsb first. The following diagrams illustrate the timing. Once data transfer is complete a DS1075 new transaction sequence can be started by re–initializing the device. Therefore to program both the DIV and MUX registers two complete transaction sequences are required. READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated below. All time slots are initiated by the master driving the data line low. The falling edge of the data line synchronizes the DS1075 to the master by triggering a delay circuit in the DS1075. During write time slots, the delay circuit determines when the DS1075 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit determines how long the DS1075 will hold the data line low overriding the 1 generated by the master. If the data bit is a “1”, the DS1075 will leave the read data time slot unchanged. WRITE “1” TIME SLOT Figure 14 tREC tSLOT VPULLUP VPULLUP MIN VIH MIN DS1075 SAMPLING WINDOW VIL MAX 0V tLOW1 RESISTOR MASTER DS1075 15 µs 60 µs 60 µs < tSLOT < 120 µs 1 µs < tLOW1 < 15 µs 1 µs < tREC < ∞ WRITE “0” TIME SLOT Figure 15 tSLOT tREC VPULLUP VPULLUP MIN VIH MIN DS1075 SAMPLING WINDOW VIL MAX 0V 15 µs 60 µs tLOW0 60 µs < tLOW0 < tSLOT < 120 µs 1 µs < tREC < ∞ 101697 11/16 DS1075 READ DATA TIME SLOT Figure 16 tSLOT VPULLUP VPULLUP MIN VIH MIN MASTER SAMPLING WINDOW VIL MAX 0V tSU tRELEASE tLOWR tRDV RESISTOR MASTER DS1075 60 µs < tSLOT < 120 µs 1 µs < tLOWR < 15 µs 0 µs < tRELEASE < 45 µs 1 µs < tREC < ∞ tRDV= 15 µs tSU < 1 µs RETURN TO NORMAL OPERATION DEFAULT REGISTER VALUES When programming is complete the DS1075 should be powered down. If the pull–up resistor on the IN/OUT pin is removed, normal device operation will be restored next time power is applied. Unless ordered from the factory with specific register program values, the DS1075 is shipped with the following default register values: DIV = 0 0000 0000 (Programmable divider will divide by two) MUX = 0 0011 0100 OUT0 Disabled Power–Down Enabled, Select Disabled M = 4 (Ignored, see MSEL) MSEL = 1 (M prescaler bypassed) DIV1 = 0 (N Dividers enabled) E/I = 0 (Internal oscillator selected) 101697 12/16 DS1075 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature –1.0V to +7.0V 0°C to 70°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITION Supply Voltage VCC High–level Output Voltage (IN/OUT, OUT0) VOH IOH = –4 mA, VCC = MIN Low–level Output Voltage (IN/OUT, OUT0) VOL IOL = 4 mA High–level Input Voltage (PDN/SELX, OE, IN/OUT) (OSCIN) VIH VIH Low–level Input Voltage (PDN/SELX, OE, IN/OUT) (OSCIN) VIL VIL High–level Input Current (PDN/SELX, OE, IN/OUT) IIH (OSCIN) IIH VIH=2.4V, VCC= 5.25V VIH=VCC =5.25V Low–level Input Current (PDN/SELX, OE, IN/OUT) (OSCIN) IIL IIL VIL=0,VCC=5.25V VIL=0,VCC=5.25V ICC CL = 15 pF (both outputs) Supply Current (Active) DS1075–100 DS1075–80 DS1075–66 DS1075–60 Standby Current (power–down) ICCQ (tA = 0°C to 70°C, VCC = 5V + 5%) MIN TYP MAX UNITS 4.75 5 5.25 V 2.4 V 0.4 2 3 Power–Down Mode NOTES V V V 0.8 2 V V 1 uA 25 uA –1 –25 uA uA 35 0.8 50 mA uA 101697 13/16 DS1075 AC ELECTRICAL CHARACTERISTICS (tA = 0°C to 70°C, VCC = 5V + 5%) SYMBOL CONDITION MIN TYP MAX UNITS Output Frequency Tolerance ∆fO VCC = 5V, TA = 25°C –0.5 0 +0.5 % Combined Freq. Variation ∆fO Over temp and voltage –1 +1 % Long Term Stability ∆fO –0.5 +0.5 % External clock 50 MHz Crystal reference 25 MHz PARAMETER Maximum Input Frequency fOSCIN Minimum Output Frequency fOUT Power–Up Time tpor + tstab 0.1 Enable OUT from PDN ↑ tstab Enable OUT0 from PDN ↑ tstab OUT Hi–Z from PDN ↓ NOTES 1 KHz 2 1 ms 3, 4 0.1 1 ms 4 0.1 1 ms 4, 5 tpdn 1 ms OUT0 Hi–Z from PDN ↓ tpdn 1 ms Load Capacitance (IN/OUT, OUT0) CL Output Duty Cycle IN/OUT OUT0 200 15 40 40 pF 60 60 6 % % NOTES: 1. This is the maximum frequency which can be applied to OSCIN, or, the maximum crystal frequency that can be used. 2. The values of M, N and the frequency of OSCIN (if used) must be chosen so that this spec is met 3. This is the time from when VCC is applied until the output starts oscillating 4. When the device is initially powered up, or restored from the power–down mode, OE should be asserted (high). Otherwise the start of the tstab interval will be delayed until OE goes high. OE can subsequently be returned to a low level during the tstab interval to force out low after the tstab interval. If the external mode is selected tstab will be a function of the OSCIN period, i.e., external clock frequency. See “Calculated Parameters” to determine the value of tstab in this case. 5. Although OE does not normally affect OUT0 operation, if OE is held low during power–up the start of the tstab period will be delayed until OE is asserted. If OE remains low, OUT0 will not start. 6. Operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency. 101697 14/16 DS1075 AC ELECTRICAL CHARACTERISTICS – CALCULATED PARAMETERS The following characteristic are derived from various device operating parameters (frequency, mode etc.). They are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount due to internal device setup times and propagation delays. However, these equations can be used to derive a more accurate idea of typical device performance than the guaranteed values. PARAMETER SYMBOL CONDITION MIN MAX OUT ↑ from OE ↑ ten tM 2tM OUT ↓ from OE ↓ N=1 N >2 tdis tdis tOUTH 0 tOUTH + tM tOUTH SELX ↓ to OUT0 ↑ – Internal to External – External to Internal tSIE tSEI tI/2 tI/2 3tI/2 + tE 3tI/2 + tEhigh Break during SEL switch – Internal to External – External to Internal tLOW tLOW tI/2 tI/2 tI/2 + tE 3tI/2 + tElow PDN ↓ to IN/OUT Hi–Z N=1 N≥2 tpdn tpdn tOUTH 0 tOUTH + tM tOUTH PDN ↓ to OUT0 Hi–Z N=1 N≥2 tpdn tpdn tOUTH 0 tOUTH + tM tOUTH PDN ↑ to OUT ↑ tstab 256tM PDN ↑ to OUT0 ↑ tstab 256tM OUT ↑ after Power–Up 256tM OUT0 ↑ after Power–Up 256tM 101697 15/16 DS1075 DATA SHEET REVISION SUMMARY The following represent the key differences between 11/16/97 and 05/01/97 version of the DS1075 data sheet. Please review this summary carefully. 1. Page 1, description, second paragraph. Word change 2. Page 14, AC electrical characteristic. Add Long Term Stability and new spec. The following represent the key differences between 05/01/97 and 10/15/97 version of the DS1075 data sheet. Please review this summary carefully. 1. Status Change (REMOVE PRELIMINARY). 101697 16/16