ETC 551011208-001

Audio Power Amplifier
350mW Audio Power Amplifier with Shutdown Mode
General Description
Key Specifications
The HWD2119 is a mono bridged power amplifier that is capable of delivering 350mWRMS output power into a 16Ω load
or 300mWRMS output power into an 8Ω load with 10%
THD+N from a 5V power supply.
The HWD2119 audio power amplifier is designed specifically
to provide high quality output power and minimize PCB
area with surface mount packaging and a minimal amount
of external components. Since the HWD2119 does not
require output coupling capacitors, bootstrap capacitors or
snubber networks, it is optimally suited for low-power portable applications.
The closed loop response of the unity-gain stable HWD2119
can be configured using external gain-setting resistors. The
device is available in LLP, MSOP, and SO package types to
suit various applications.
n THD+N at 1kHz, 350mW continuous average output
power into 16Ω
10% (max)
n THD+N at 1kHz, 300mW continuous average output
power into 8Ω
10% (max)
n Shutdown Current
0.7µA (typ)
LLP, SOP, and MSOP surface mount packaging.
Switch on/off click suppression.
Unity-gain stable.
Minimum external components.
n General purpose audio
n Portable electronic devices
n Information Appliances (IA)
Typical Application
FIGURE 1. Typical Audio Amplifier Application Circuit
Connection Diagrams
Small Outline (SO) Package
SO Marking
HWD 2119 M
Top View
XY - Date Code
TT - Die Traceability
Bottom 2 lines - Part Number
Top View
Order Numer HWD2119M
Mini Small Outline (MSOP) Package
MSOP Marking
Top View
Top View
Order Number HWD2119MM
19 -HWD2119MM
LLP Package
Top View
Order Number HWD2119LD
Absolute Maximum Ratings (Notes 2, 3)
Infrared (15 seconds)
Thermal Resistance
If Military/Aerospace specified devices are required,
please contact the CSMSC Semiconductor Sales Office/
Distributors for availability and specifications.
−65˚C to +150˚C
−0.3V to VDD +0.3V
117˚C/W (Note 10)
Internally Limited
150˚C/W (Note 11)
Supply Voltage
Storage Temperature
Input Voltage
Power Dissipation (PD) (Note 4)
ESD Susceptibility (Note 5)
ESD Susceptibility (Note 6)
Junction Temperature (TJ)
Operating Ratings (Notes 2, 3)
Temperature Range
Soldering Information (Note 1)
Small Outline Package
Vapor Phase (60 seconds)
−40˚C ≤ TA ≤ 85˚C
2.0V ≤ VCC ≤ 5.5V
Supply Voltage
Electrical Characteristics VDD = 5V
(Notes 2, 3)
The following specifications apply for VDD = 5V, RL = 16Ω unless otherwise stated. Limits apply for TA = 25˚C.
(Note 7)
(Notes 8, 9)
Quiescent Power Supply Current
VIN = 0V, Io = 0A
mA (max)
Shutdown Current
VPIN1 = VDD (Note 12)
µA (max)
Shutdown Voltage Input High
V (min)
Shutdown Voltage Input Low
V (max)
Output Offset Voltage
mV (max)
Output Power
Total Harmonic Distortion + Noise
VIN = 0V
THD = 10%, fIN = 1kHz
THD = 10%, fIN = 1kHz, RL = 8Ω
PO = 270mWRMS, AVD = 2, fIN =
Electrical Characteristics VDD = 3V
(Notes 2, 3)
The following specifications apply for VDD = 3V and RL = 16Ω load unless otherwise stated. Limits apply to TA = 25˚C.
(Note 7)
(Notes 8, 9)
Quiescent Power Supply Current
VIN = 0V, Io = 0A
mA (max)
Shutdown Current
VPIN1 = VDD (Note 12)
µA (max)
Shutdown Voltage Input High
V (min)
Shutdown Voltage Input Low
V (max)
Output Offset Voltage
Output Power
Total Harmonic Distortion + Noise
VIN = 0V
THD = 10%, fIN = 1kHz
THD = 10%, fIN = 1kHz, RL = 8Ω
PO = 80mWRMS, AVD = 2, fIN =
Electrical Characteristics VDD = 3V
(Notes 2, 3)
The following specifications apply for VDD = 3V and RL = 16Ω load unless otherwise stated. Limits apply to TA =
25˚C. (Continued)
Note 1: See AN-450 ’Surface Mounting and their Effects on Product Reliability’ for other methods of soldering surface mount devices.
Note 2: All voltages are measured with respect to the ground pin, unless otherwise specified.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which
guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit
is given. However, the typical value is a good indication of device’s performance.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum
allowable power dissipation is PDMAX = (TJMAX–TA)/θJA. For the HWD2119, TJMAX = 150˚C and the typical junction-to-ambient thermal resistance (θJA) when board
mounted is 210˚C/W for the MSOP package and 170˚C/W for the SOP package.
Note 5: Human body model, 100pF discharged through a 1.5 kΩ resistor.
Note 6: Machine Model, 220pF–240pF capacitor is discharged through all pins.
Note 7: Typical specifications are specified at 25˚C and represent the parametric norm.
Note 8: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Datasheet min/max specification limits are guaranteed by designs, test, or statistical analysis.
Note 10: The given θJA is for an HWD2119 package in an LDA08B with the Exposed-DAP soldered to a printed circuit board copper pad with an area equivalent to
that of the Exposed-DAP itself. The Exposed-DAP of the LDA08B package should be electrically connected to GND or an electrically isolated copper area.
Note 11: The given θJA is for an HWD2119 package in an LDA08B with the Exposed-DAP not soldered to any printed circuit board copper.
Note 12: The shutdown pin (pin1) should be driven as close as possible to VDD for minimum current in Shutdown Mode.
External Components Description
(Figure 1)
Functional Description
Combined with Rf, this inverting input resistor sets the closed-loop gain. Ri also forms a high pass filter with
Ci at fc = 1/(2πRiCi).
This input coupling capacitor blocks DC voltage at the amplifier’s terminals. Combined with Ri, it creates a
high pass filter with Ri at fc = 1/(2πRiCi). Refer to the section, Proper Selection of External Components
for an explanation of how to determine the value of Ci.
Combined with Ri, this is the feedback resistor that sets the closed-loop gain: Av = 2(RF/Ri).
This is the power supply bypass capacitor that filters the voltage applied to the power supply pin. Refer to
the Application Information section for proper placement and selection of Cs.
This is the bypass pin capacitor that filters the voltage at the BYPASS pin. Refer to the section, Proper
Selection of External Components, for information concerning proper placement and selection of CB.
Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
Typical Performance Characteristics
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Output Power
THD+N vs Frequency
THD+N vs Frequency
THD+N vs Output Power
Typical Performance Characteristics
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
THD+N vs Output Power
Output Power vs Supply Voltage
RL = 8Ω
Output Power vs Supply Voltage
RL = 16Ω
Typical Performance Characteristics
Output Power vs Supply Voltage
RL = 32Ω
Output Power vs Load Resistance
Power Dissipation vs
Output Power
VDD = 5V
Power Dissipation vs
Output Power
VDD = 3V
Power Derating Curves
Frequency Response vs
Input Capacitor Size
Typical Performance Characteristics
Supply Current vs
Supply Voltage
For the micro MUA08A package, θJA = 210˚C/W, for the
M08A package, θJA = 170˚C/W , and TJMAX = 150˚C for the
HWD2119. For a given ambient temperature,AT, Equation (4)
can be used to find the maximum internal power dissipation
supported by the IC packaging. If the result of Equation (3) is
greater than the result of Equation (4), then decrease the
supply voltage, increase the load impedance, or reduce the
ambient temperature. For a typical application using the
M08A packaged HWD2119 with a 5V power supply and an 8Ω
load, the maximum ambient temperature that does not violate the maximum junction temperature is approximately
42˚C. If a MUA08A packaged part is used instead with the
same supply voltage and load, the maximum ambient temperature is 17˚C. In both cases, it is assumed that a device
is a surface mount part operating around the maximum
power dissipation point. The assumption that the device is
operating around the maximum power dissipation point is
incorrect for an 8Ω load. The maximum power dissipation
point occurs when the output power is equal to the maximum
power dissipation or 50% efficiency. The HWD2119 is not
capable of the output power level (633mW) required to operate at the maximum power dissipation point for an 8Ω load.
To find the maximum power dissipation, the graph Power
Dissipation vs. Output Power must be used. From the
graph, the maximum power dissipation for an 8Ω load and a
5V supply is approximately 575mW. Substituting this value
back into equation (4) for PDMAX and using θJA = 210˚C/W
for the MUA08A package, the maximum ambient temperature is calculated to be 29˚C. Using θJA = 170˚C/W for the
M08A package, the maximum ambient temperature is 52˚C.
Refer to the Typical Performance Characteristics curves
for power dissipation information for lower output powers
and maximum power dissipation for each package at a given
ambient temperature.
Application Information
As shown in Figure 1, the HWD2119 consist of two operational
amplifiers. External resistors, Ri and RF set the closed-loop
gain of the first amplifier (and the amplifier overall), whereas
two internal 20kΩ resistors set the second amplifier’s gain at
-1. The HWD2119 is typically used to drive a speaker connected between the two amplifier outputs.
Figure 1 shows that the output of Amp1 servers as the input
to Amp2, which results in both amplifiers producing signals
identical in magnitude but 180˚ out of phase. Taking advantage of this phase difference, a load is placed between V01
and V02 and driven differentially (commonly referred to as
’bridge mode’). This results in a differential gain of
AVD= 2 *(Rf/Ri)
Bridge mode is different from single-ended amplifiers that
drive loads connected between a single amplifier’s output
and ground. For a given supply voltage, bridge mode has a
distinct advantage over the single-ended configuration: its
differential output doubles the voltage swing across the load.
This results in four times the output power when compared
to a single-ended amplifier under the same conditions. This
increase in attainable output assumes that the amplifier is
not current limited or the output signal is not clipped. To
ensure minimum output signal clipping when choosing an
amplifier’s closed-loop gain, refer to the Audio Power Amplifier Design Example section.
Another advantage of the differential bridge output is no net
DC voltage across the load. This results from biasing V01
and V02 at half-supply. This eliminates the coupling capacitor
that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a single-ended configuration forces a single supply amplifier’s half-supply bias voltage across the load. The current flow created by the halfsupply bias voltage increases internal IC power dissipation
and may permanently damage loads such as speakers.
As with any power amplifier, proper supply bypassing is
critical for low noise performance and high power supply
rejection. The capacitors connected to the bypass and power
supply pins should be placed as close to the HWD2119 as
possible. The capacitor connected between the bypass pin
and ground improves the internal bias voltage’s stability,
producing improved PSRR. The improvements to PSRR
increase as the bypass pin capacitor value increases. Typical applications employ a 5V regulator with 10µF and 0.1µF
filter capacitors that aid in supply stability. Their presence,
however, does not eliminate the need for bypassing the
supply nodes of the HWD2119. The selection of bypass capacitor values, especially CB , depends on desired PSRR
requirements, click and pop performance as explained in the
section, Proper Selection of External Components, as
well as system cost and size constraints.
Power dissipation is a major concern when designing a
successful bridged or single-ended amplifier. Equation (2)
states the maximum power dissipation point for a singleended amplifier operating at a given supply voltage and
driving a specified load.
PDMAX = (VDD)2 /(2π2RL ) (W) Single-ended
However, a direct consequence of the increased power delivered to the load by a bridged amplifier is an increase in the
internal power dissipation point for a bridge amplifier operating at the same given conditions. Equation (3) states the
maximum power dissipation point for a bridged amplifier
operating at a given supply voltage and driving a specified
PDMAX = 4(VDD)2/(2π2 RL ) (W) Bridge Mode
The voltage applied to the HWD2119’s SHUTDOWN pin controls the shutdown function. Activate micro-power shutdown
by applying VDD to the SHUTDOWN pin. When active, the
HWD2119’s micro-power shutdown feature turns off the amplifier’s bias circuitry, reducing the supply current. The logic
threshold is typically 1/2VDD. The low 0.7µA typical shutdown current is achieved by applying a voltage that is as
near as VDD as possible to the SHUTDOWN pin. A voltage
that is less than VDD may increase the shutdown current.
Avoid intermittent or unexpected micro-power shutdown by
ensuring that the SHUTDOWN pin is not left floating but
connected to either VDD or GND.
The HWD2119 has two operational amplifiers in one package
and the maximum internal power dissipation is four times
that of a single-ended amplifier. However, even with this
substantial increase in power dissipation, the HWD2119 does
not require heatsinking. From Equation (3), assuming a 5V
power supply and an 8Ω load, the maximum power dissipation point is 633mW. The maximum power dissipation point
obtained from Equation (3) must not exceed the power dissipation predicted by Equation (4):
Application Information
There are a few ways to activate micro-power shutdown.
These included using a single-pole, single-throw switch, a
microcontroller, or a microprocessor. When using a switch,
connect an external 10kΩ to 100kΩ pull-up resistor between
the SHUTDOWN pin and VDD. Connect the switch between
the SHUTDOWN pin and ground. Select normal amplifier
operation by closing the switch. Opening the switch connects the shutdown pin to VDD through the pull-up resistor,
activating micro-power shutdown. The switch and resistor
guarantee that the SHUTDOWN pin will not float. This prevents unwanted state changes. In a system with a microprocessor or a microcontroller, use a digital output to apply the
control voltage to the SHUTDOWN pin. Driving the SHUTDOWN pin with active circuitry eliminates the pull-up resistor
Optimizing the HWD2119’s performance requires properly selecting external components. Though the HWD2119 operates
well when using external components with wide tolerances,
best performance is achieved by optimizing component values.
The HWD2119 is unity gain stable, giving the designer maximum design flexibility. The gain should be set to no more
than a given application requires. This allows the amplifier to
achieve minimum THD+N and maximum signal-to-noise ratio. These parameters are compromised as the closed-loop
gain increases. However, low gain demands input signals
with greater voltage swings to achieve maximum output
power. Fortunately, many signal sources such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the
Audio Power Amplifier Design section for more information on selecting the proper gain.
Another important consideration is the amplifier’s close-loop
bandwidth. To a large extent, the bandwidth is dictated by
the choice of external components shown in Figure 1. The
input coupling capacitor, Ci, forms a first order high pass filter
that limits low frequency response. This value should be
chosen based on needed frequency response for a few
distinct reasons discussed below
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high
value input coupling capacitor (Ci in Figure 1). A high value
capacitor can be expensive and may compromise space
efficiency in portable designs. In many cases the speakers
used in portable systems, whether internal or external, have
little ability to reproduce signals below 150Hz. Applications
using speakers with limited frequency response reap little
improvement by using a large input capacitor.
Besides affecting system cost and size, Ci has an effect on
the HWD2119’s click and pop performance. When the supply
voltage is first applied, a transient (pop) is created as the
charge on the input capacitor changes from zero to a quiescent state. The magnitude of the pop is directly proportional
to the input capacitor’s value. Higher value capacitors need
more time to reach a quiescent DC voltage (usually 1/2 VDD)
when charged with a fixed current. The amplifier’s output
charges the input capacitor through the feedback resistor,
RF. Thus, selecting an input capacitor value that is no higher
than necessary to meet the desired -3dB frequency can
minimize pops.
As shown in Figure 1, the input resistor (Ri) and the input
capacitor, Ci produce a -3dB high pass filter cutoff frequency
that is found using Equation (5).
f-3dB = 1/(2 πRiCi) (Hz)
As an example when using a speaker with a low frequency
limit of 150Hz, Ci, using Equation (5) is 0.063µF. The 0.39µF
Ci shown in Figure 1 allows the HWD2119 to drive a high
efficiency, full range speaker whose response extends down
to 20Hz.
Besides optimizing the input capacitor value, the bypass
capacitor value, CB requires careful consideration. The bypass capacitor’s value is the most critical to minimizing
turn-on pops because it determines how fast the HWD2119
turns on. The slower the HWD2119’s outputs ramp to their
quiescent DC voltage (nominally 1/2VDD), the smaller the
turn-on pop. While the device will function properly (no oscillations or motorboating), with CB less than 1.0µF, the
device will be much more susceptible to turn-on clicks and
pops. Thus, a value of CB equal to or greater than 1.0µF is
recommended in all but the most cost sensitive designs.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to the value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how
fast the HWD2119 settles to quiescent operation, its value is
critical when minimizing turn-on pops. The slower the
HWD2119’s outputs ramp to their quiescent DC voltage (nominally 1/2VDD), the smaller the turn-on pop. Choosing CB
equal to 1.0µF along with a small value of Ci (in the range of
0.1µF to 0.39µF) produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger
than necessary for the desired bandwidth helps minimize
clicks and pops.
Optimizing Click and Pop Reduction Performance
The HWD2119 contains circuitry that minimizes turn-on and
shutdown transients or ’clicks and pops’. For this discussion,
turn on refers to either applying the power or supply voltage
or when the shutdown mode is deactivated. While the power
supply is ramping to it’s final value, the HWD2119’s internal
amplifiers are configured as unity gain buffers. An internal
current source charges the voltage of the bypass capacitor,
CB, connected to the BYPASS pin in a controlled, linear
manner. Ideally, the input and outputs track the voltage
charging on the bypass capacitor. The gain of the internal
amplifiers remains unity until the bypass capacitor is fully
charged to 1/2VDD. As soon as the voltage on the bypass
capacitor is stable, the device becomes fully operational.
Although the BYPASS pin current cannot be modified,
changing the size of the bypass capacitor, CB, alters the
device’s turn-on time and magnitude of ’clicks and pops’.
Increasing the value of CB reduces the magnitude of turn-on
pops. However, this presents a tradeoff: as the size of CB
increases, the turn-on time (Ton) increases. There is a linear
relationship between the size of CB and the turn on time.
Below are some typical turn-on times for various values of
Application Information
In order to eliminate ’clicks and pops’, all capacitors must be
discharged before turn-on. Rapidly switching VDD may not
allow the capacitors to fully discharge, which may cause
’clicks and pops’.
The following are the desired operational
Power Output
Load Impedance
Input Level
Input Impedance
1Vrms (max)
100Hz–20kHz ± 0.25dB
The design begins by specifying the minimum supply voltage
necessary to obtain the specified output power. To find this
minimum supply voltage, use the Output Power vs. Supply
Voltage graph in the Typical Performance Characteristics
section. From the graph for a 16Ω load, (graphs are for 8Ω,
16Ω, and 32Ω loads) the supply voltage for 100mW of output
power with 1% THD+N is approximately 3.15 volts.
Additional supply voltage creates the benefit of increased
headroom that allows the HWD2119 to reproduce peaks in
excess of 100mW without output signal clipping or audible
distortion. The choice of supply voltage must also not create
a situation that violates maximum dissipation as explained
above in the Power Dissipation section. For example, if a
3.3V supply is chosen for extra headroom then according to
Equation (3) the maximum power dissipation point with a
16Ω load is 138mW. Using Equation (4) the maximum ambient temperature is 121˚C for the MUA08A package and
126˚C for the M08A package.
After satisfying the HWD2119’s power dissipation requirements, the minimum differential gain is found using Equation
The last step in this design example is setting the amplifier’s
-3dB frequency bandwidth. To achieve the desired ± 0.25dB
pass band magnitude variation limit, the low frequency response must extend to at least one-fifth the lower bandwidth
limit and the high frequency response must extend to at least
five times the upper bandwidth limit. The gain variation for
both response limits is 0.17dB, well with in the ± 0.25dB
desired limit.
The results are:
fL = 100Hz/5 = 20Hz
fH = 20 kHz*5 = 100kHz
As mentioned in the External Components section, Ri and
Ci create a high pass filter that sets the amplifier’s lower
band pass frequency limit. Find the coupling capacitor’s
value using Equation (8).
Ci ≥ 1/(2πRifc) (F)
Ci ≥ 0.398µF, a standard value of 0.39µF will be used. The
product of the desired high frequency cutoff (100kHz in this
example) and the differential gain, AVD, determines the upper pass band response limit. With AVD = 1.27 and fH =
100kHz, the closed-loop gain bandwidth product (GBWP) is
127kHz. This is less than the HWD2119’s 900kHz GBWP. With
this margin the amplifier can be used in designs that require
more differential gain while avoiding performance restricting
bandwidth limitations.
Thus a minimum gain of 1.27 V/V allows the HWD2119 to
reach full output swing and maintain low noise and THD+N
performance. For this example, let AVD = 1.27. The amplifier’s overall gain is set using the input (Ri) and feedback (RF)
resistors. With the desired input impedance set to 20kΩ, the
feedback resistor is found using Equation (7).
RF/Ri = AVD/2 (V/V)
The value of RF is 13kΩ.
Application Information
Figure 2
The HWD2119 is unity-gain stable and requires no external
components besides gain-setting resistors, an input coupling
capacitor, and proper supply bypassing in the typical application. However, if a closed-loop differential gain of greater
than 10 is required, a feedback capacitor (C4) may be
needed as shown in Figure 2 to bandwidth limit the amplifier.
This feedback capacitor creates a low pass filter that eliminates possible high frequency oscillations. Care should be
taken when calculating the -3dB frequency in that an incorrect combination of R3 and C4 will cause rolloff before
20kHz. A typical combination of feedback resistor and capacitor that will not produce audio band high frequency rolloff
is R3 = 20kΩ and C4 = 25pF. These components result in a
-3dB point of approximately 320 kHz. It is not recommended
that the feedback resistor and capacitor be used to implement a band limiting filter below 100kHz.
Application Information
Figure 3
Application Information
Figure 4
Application Information
Silk Screen
Top Layer
Bottom Layer
Application Information
Composite View
Silk Screen
Top Layer
Bottom Layer
Application Information
Mono HWD2119 Reference Design Boards
Bill of Material for all Demo Boards
Part Number
Part Description
551011208-001 HWD2119 Mono Reference Design Board
Ref Designator
Tant Cap 1uF 16V 10
Cer Cap 0.39uF 50V Z5U 20% 1210
Tant Cap 1uF 16V 10
Res 20K Ohm 1/10W 5
R1, R2, R3
Jumper Header Vertical Mount 2X1
J1, J2
HWD2119 Audio AMP
This section provides practical guidelines for mixed signal
PCB layout that involves various digital/analog power and
ground traces. Designers should note that these are only
’rule-of-thumb’ recommendations and the actual results will
depend heavily on the final layout.
Single-Point Power / Ground Connections
The analog power traces should be connected to the digital
traces through a single point (link). A ’Pi-filter’ can be helpful
in minimizing high frequency noise coupling between the
analog and digital sections. It is further recommended to put
digital and analog power traces over the corresponding digital and analog ground traces to minimize noise coupling.
General Mixed Signal Layout Recommendation
Power and Ground Circuits
For two layer mixed signal design, it is important to isolate
the digital power and ground trace paths from the analog
power and ground trace paths. Star trace routing techniques
(bringing individual traces back to a central point rather than
daisy chaining traces together in a serial manner) can have
a major impact on low level signal performance. Star trace
routing refers to using individual traces to feed power and
ground to each circuit or even device. This technique will
take require a greater amount of design time but will not
increase the final price of the board. The only extra parts
required will be some jumpers.
Placement of Digital and Analog Components
All digital components and high-speed digital signals traces
should be located as far away as possible from analog
components and circuit traces.
Avoiding Typical Design / Layout Problems
Avoid ground loops or running digital and analog traces
parallel to each other (side-by-side) on the same PCB layer.
When traces must cross over each other do it at 90 degrees.
Running digital and analog traces at 90 degrees to each
other from the top to the bottom side as much as possible will
minimize capacitive noise coupling and cross talk.
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number HWD2119MM
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Order Number HWD2119M
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Order Number HWD2119LD
Chengdu Sino Microelectronics System Co.,Ltd
Headquarters of CSMSC:
Beijing Office:
Address: 2nd floor, Building D,
Science & Technology
Industrial Park, 11 Gaopeng
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Tel: +86-28-8517-7737
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