ETC BUK9E06-55B

BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
Rev. 03 — 30 November 2004
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive (HPA) TrenchMOS™ technology, featuring very low
on-state resistance.
1.2 Features
■ TrenchMOS™ technology
■ 175 °C rated
■ Q101 compliant
■ Logic level compatible.
1.3 Applications
■ Automotive systems
■ Motors, lamps and solenoids
■ 12 V and 24 V loads
■ General purpose power switching.
1.4 Quick reference data
■ EDS(AL)S ≤ 679 mJ
■ ID ≤ 75 A
■ RDSon = 5.1 mΩ (typ)
■ Ptot ≤ 258 W.
2. Pinning information
Table 1:
Pinning
Pin
Description
1
gate (G)
2
drain (D)
3
source (S)
mb
mounting base;
connected to drain (D)
Simplified outline
[1]
Symbol
G
mbb076
123
2
1
1 2 3
3
SOT404 (D2-PAK)
SOT78 (TO-220AB)
[1]
D
mb
mb
mb
It is not possible to make a connection to pin 2 of the SOT404 package.
SOT226 (I2-PAK)
S
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
BUK9506-55B
TO-220AB
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead
TO-220AB
SOT78
BUK9606-55B
D2-PAK
Plastic single-ended surface mounted package (Philips version of D2-PAK); SOT404
3 leads (one lead cropped)
BUK9E06-55B
I2-PAK
Plastic single-ended package (Philips version of I2-PAK); low-profile 3 lead
TO-220AB
SOT226
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
VDS
drain-source voltage (DC)
VDGR
drain-gate voltage (DC)
VGS
gate-source voltage (DC)
ID
drain current (DC)
Conditions
RGS = 20 kΩ
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
Tmb = 100 °C; VGS = 5 V; Figure 2
Min
Max
Unit
-
55
V
-
55
V
-
±15
V
[1]
-
146
A
[2]
-
75
A
[2]
-
75
A
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
-
587
A
Ptot
total power dissipation
Tmb = 25 °C; Figure 1
-
258
W
Tstg
storage temperature
−55
+175
°C
Tj
junction temperature
−55
+175
°C
[1]
-
146
A
[2]
-
75
A
Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
587
A
unclamped inductive load; ID = 75 A;
VDS ≤ 55 V; RGS = 50 Ω; VGS = 5 V; starting
at Tj = 25 °C
-
679
mJ
Source-drain diode
reverse drain current (DC)
IDR
IDRM
peak reverse drain current
Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
[1]
Current is limited by power dissipation chip rating
[2]
Continuous current is limited by package
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
2 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa16
120
03nh85
150
Pder
(%)
ID
(A)
80
100
40
50
Capped at 75 A due to package
0
0
0
50
100
150
Tmb (°C)
0
200
50
100
150
Tmb ( °C)
200
VGS ≥ 5 V
P tot
P der = ----------------------- × 100%
P
°
tot ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
Fig 2. Continuous drain current as a function of
mounting base temperature.
03nh83
103
tp = 10 µ s
Limit RDSon = VDS / ID
ID
(A)
102
100 µ s
Capped at 75 A due to package
1 ms
DC
10
10 ms
100 ms
1
10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13519
Product data sheet
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Rev. 03 — 30 November 2004
3 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base Figure 4
Rth(j-a)
thermal resistance from junction to ambient
Min
Typ
Max
Unit
-
-
0.58
K/W
SOT78 (TO-220AB) and SOT226 (I2-PAK)
vertical in free air
-
60
-
K/W
SOT404 (D2-PAK)
mounted on a printed-circuit
board; minimum footprint;
vertical in still air
-
50
-
K/W
5.1 Transient thermal impedance
03nh84
1
Zth(j-mb)
(K/W)
δ = 0.5
0.2
-1
10
0.1
0.05
0.02
δ=
P
10-2
single shot
tp
T
t
tp
T
10-3
10-6
10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13519
Product data sheet
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Rev. 03 — 30 November 2004
4 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
55
-
-
V
Tj = −55 °C
50
-
-
V
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
ID = 250 µA; VGS = 0 V
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
1.1
1.5
2
V
Tj = 175 °C
0.5
-
-
V
Tj = −55 °C
-
-
2.3
V
Tj = 25 °C
-
0.02
1
µA
Tj = 175 °C
-
-
500
µA
-
2
100
nA
Tj = 25 °C
-
5.1
6.0
mΩ
Tj = 175 °C
-
-
12
mΩ
VGS = 4.5 V; ID = 25 A; Figure 6 and 8
-
-
6.4
mΩ
VGS = 10 V; ID = 25 A; Figure 6 and 8
-
4.8
5.4
mΩ
ID = 25 A; VDD = 44 V; VGS = 5 V;
Figure 14 and 16
-
60
-
nC
-
11
-
nC
-
22
-
nC
-
2.4
-
V
-
5 674 7565 pF
-
755
906
pF
-
255
350
pF
VDS = 55 V; VGS = 0 V
IGSS
gate-source leakage current
VGS = ±15 V; VDS = 0 V
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 25 A; Figure 6 and 8
Dynamic characteristics
Qg(tot)
total gate charge
Qgs
gate-source charge
Qgd
gate-drain (Miller) charge
Vplat
plateau voltage
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Figure 12
VDS = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
-
37
-
ns
-
95
-
ns
turn-off delay time
-
117
-
ns
tf
fall time
-
106
-
ns
Ld
internal drain inductance
from drain lead 6 mm from package to
center of die
-
4.5
-
nH
from contact screw on mounting base to
center of die SOT78
-
3.5
-
nH
from upper edge of drain mounting base
to center of die SOT404/SOT226
-
2.5
-
nH
from source lead to source bonding pad
-
7.5
-
nH
Ls
internal source inductance
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
5 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
0.85
1.2
V
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 15
trr
reverse recovery time
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs;
VGS = 0 V; VR = 30 V
03nj65
350
ID
10
(A)
300 6
5
4.2
64
-
ns
79
-
nC
03nj64
7
VGS (V) is
4
250
-
3.8
RDSon
(mΩ)
3.6
6
200
3.4
150
3.2
100
3
5
2.8
50
2.6
2.4
4
0
0
2
4
6
8
VDS (V)
3
10
Tj = 25 °C
11
VGS (V)
15
Tj = 25 °C; ID = 25 A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values.
Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
03nj66
14
RDSon
(mΩ)
12
7
3
3.2
03ne89
2
VGS (V) is
a
3.4
4
1.5
10
8
1
5
10
6
0.5
4
2
0
100
200
300 I (A) 400
D
Tj = 25 °C
0
-60
60
120
Tj (°C)
180
R DSon
a = ---------------------------R DSon ( 25 °C )
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
9397 750 13519
Product data sheet
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
6 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ng52
2.5
VGS(th)
(V)
03ng53
10-1
ID
(A)
2.0
max
10-2
1.5
typ
10-3
min
min
1.0
typ
max
10-4
10-5
0.5
0.0
-60
10-6
0
60
120
Tj (°C)
180
0
1
2
3
VGS (V)
Tj = 25 °C; VDS = VGS
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature.
03nj62
200
Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
03nj67
8000
gfs
(S)
C
(pF)
Ciss
150
6000
100
4000
Coss
50
2000
Crss
0
0
20
40
60
I D (A)
80
Tj = 25 °C; VDS = 25 V
0
10-1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values.
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
9397 750 13519
Product data sheet
1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
7 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03nj63
100
03nj61
5
VGS
(V)
ID
(A)
4
75
VDD = 14 V
3
VDD = 44 V
50
2
25
Tj = 175 °C
1
Tj = 25 °C
0
0
0
1
2
3
VGS (V)
0
20
40
QG (nC)
60
Tj = 25 °C; ID = 25 A
VDS = 25 V
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values.
Fig 14. Gate-source voltage as a function of gate
charge; typical values.
03nj60
100
IS
(A)
VDS
75
ID
Vplat
50
VGS(th)
Tj = 175 °C
VGS
25
Qgs1
Qgs
Tj = 25 °C
0
0.0
0.2
0.4
0.6
0.8
Qgs2
1.0
VSD (V)
Qgd
Qg(tot)
003aaa508
VGS = 0 V
Fig 15. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values.
Fig 16. Gate charge waveform definitions.
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
8 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Package outline
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB
E
SOT78
A
A1
p
q
mounting
base
D1
D
L2
L1(1)
Q
b1
L
1
2
3
b
c
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
c
D
D1
E
e
L
L1(1)
L2
max.
p
q
Q
mm
4.5
4.1
1.39
1.27
0.9
0.6
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
JEITA
3-lead TO-220AB
SC-46
EUROPEAN
PROJECTION
ISSUE DATE
01-02-16
03-01-22
Fig 17. Package outline SOT78 (TO-220AB).
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
9 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (D2-PAK); 3 leads (one lead cropped)
SOT404
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
01-02-12
04-10-13
SOT404
Fig 18. Package outline SOT404 (D2-PAK).
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
10 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Plastic single-ended package (Philips version of I 2-PAK); low-profile 3 lead TO-220AB
SOT226
A
A1
E
D1
mounting
base
D
L1
L2
Q
b1
L
1
2
3
c
b
e
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
c
D
max
D1
E
e
L
L1
L2 (1)
max
Q
mm
4.5
4.1
1.40
1.27
0.85
0.60
1.3
1.0
0.7
0.4
11
1.6
1.2
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT226
REFERENCES
IEC
JEDEC
JEITA
low-profile
3-lead TO-220AB
EUROPEAN
PROJECTION
ISSUE DATE
03-10-14
04-02-24
Fig 19. Package outline SOT226 (I2-PAK).
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
11 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Mounting
10.85
10.60
10.50
1.50
7.50
7.40
1.70
2.25 2.15
8.15
8.275
8.35
1.50
4.60
0.30
4.85
5.40
7.95
8.075
3.00
0.20
1.20
1.30
1.55
solder lands
solder resist
5.08
MSD057
occupied area
solder paste
Dimensions in mm.
Fig 20. Reflow soldering footprint for SOT404.
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
12 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Revision history
Table 6:
Revision history
Document ID
Release
date
Data sheet
status
BUK95_96_9E06_55B_3
20041130
Product data sheet
Modifications:
Change
notice
Doc number
Supersedes
9397 750 13519
BUK95_96_9E06_55B_2
•
The format of this data sheet has been redesigned to comply with the new
presentation and information standard of Philips Semiconductors.
•
Latest version of package outlines imported into Section 7 of data sheet.
BUK95_96_9E06_55B-02
20021010
Product data sheet
9397 750 10474
BUK95_96_9E06_55B-01
BUK95_96_9E06_55B-01
20020813
Product data sheet
9397 750 09946
-
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
13 of 15
BUK95/96/9E06-55B
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
10. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
11. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
13. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
12. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
14. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
9397 750 13519
Product data sheet
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Rev. 03 — 30 November 2004
14 of 15
Philips Semiconductors
BUK95/96/9E06-55B
N-channel TrenchMOS™ logic level FET
15. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
5.1
6
7
8
9
10
11
12
13
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Transient thermal impedance . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mounting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 14
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 30 November 2004
Document number: 9397 750 13519
Published in The Netherlands