PHILIPS PHU108NQ03LT

PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
Rev. 03 — 18 April 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS™ technology.
1.2 Features
■ Logic level threshold
■ Lead-free construction
■ Very low on-state resistance
■ Low gate charge
1.3 Applications
■ DC-to-DC converter
■ Switch-mode power supplies
1.4 Quick reference data
■ VDS ≤ 25 V
■ RDSon ≤ 6 mΩ
■ ID ≤ 75 A
■ Qgd = 5.6 nC (typ)
2. Pinning information
Table 1:
Pinning
Pin
Description
1
gate (G)
2
drain (D)
3
source (S)
mb
mounting base;
connected to drain
Simplified outline
Symbol
mb
[1]
G
mbb076
2
1
2
3
1
3
1
SOT404 (D2PAK)
[1]
D
mb
mb
SOT428 (DPAK)
It is not possible to make a connection to pin 2 of the SOT404 and SOT428 packages.
2
3
SOT533 (IPAK)
S
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PHB108NQ03LT
D2PAK
plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404
PHD108NQ03LT
DPAK
plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT428
PHU108NQ03LT
IPAK
plastic single-ended package; 3 leads (in-line)
SOT533
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
VDS
drain-source voltage (DC)
25 °C ≤ Tj ≤ 175 °C
-
25
V
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
-
25
V
-
±20
V
Tmb = 25 °C; VGS = 5 V; Figure 2 and 3
-
75
A
Tmb = 100 °C; VGS = 5 V; Figure 2
-
75
A
VDGR
drain-gate voltage (DC)
VGS
gate-source voltage
ID
drain current (DC)
IDM
peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
-
240
A
Ptot
total power dissipation
Tmb = 25 °C; Figure 1
-
187
W
Tstg
storage temperature
−55
+175
°C
Tj
junction temperature
−55
+175
°C
Source-drain diode
IS
source (diode forward) current (DC) Tmb = 25 °C
-
75
A
ISM
peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs
-
240
A
-
180
mJ
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID = 43 A;
tp = 0.25 ms; VDD ≤ 25 V; RGS = 50 Ω;
VGS = 10 V; starting at Tj = 25 °C
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
2 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa16
120
03ar58
120
Ider
(%)
Pder
(%)
80
80
40
40
0
0
0
50
100
150
Tmb (°C)
200
0
P tot
P der = ------------------------ × 100 %
P
°
50
100
150
Tmb (°C)
200
ID
I der = --------------------- × 100 %
I
°
tot ( 25 C )
D ( 25 C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
03ar59
103
ID
(A)
Limit RDSon = VDS / ID
tp = 10 µs
102
100 µ s
DC
1 ms
10
10 ms
1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse; VGS = 5 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
3 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
5. Thermal characteristics
Table 4:
Thermal characteristics
Symbol Parameter
Conditions
Rth(j-mb)
thermal resistance from junction to mounting base Figure 4
Rth(j-a)
thermal resistance from junction to ambient
Min
Typ
Max
Unit
-
-
0.8
K/W
SOT404
mounted on a printed-circuit
board; minimum footprint;
vertical in still air
-
50
-
K/W
SOT428
mounted on a printed-circuit
board; minimum footprint;
vertical in still air
-
75
-
K/W
mounted on a printed-circuit
board; vertical in still air;
SOT404 minimum footprint
-
50
-
K/W
vertical in free air
-
70
-
K/W
SOT533
03ar60
1
Zth(j-mb)
(K/W)
δ = 0.5
0.2
10-1
0.1
0.05
δ=
P
0.02
tp
T
single pulse
t
tp
10-2
10-5
T
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
4 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
6. Characteristics
Table 5:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Tj = 25 °C
25
-
-
V
Tj = −55 °C
22
-
-
V
Static characteristics
V(BR)DSS
VGS(th)
IDSS
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
ID = 250 µA; VGS = 0 V
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
1
1.5
2
V
Tj = 175 °C
0.5
-
-
V
Tj = −55 °C
-
-
2.2
V
Tj = 25 °C
-
-
1
µA
Tj = 175 °C
-
-
500
µA
VDS = 25 V; VGS = 0 V
RG
gate resistance
f = 1 MHz
-
1.2
-
Ω
IGSS
gate-source leakage current
VGS = ±10 V; VDS = 0 V
-
0.02
100
nA
RDSon
drain-source on-state resistance
VGS = 5 V; ID = 25 A; Figure 6 and 8
Tj = 25 °C
-
6.7
7.5
mΩ
Tj = 175 °C
-
12.1
13.5
mΩ
VGS = 10 V; ID = 25 A; Figure 6 and 8
-
5.3
6
mΩ
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Figure 11 and 12
-
16.3
-
nC
-
4
-
nC
Dynamic characteristics
Qg(tot)
total gate charge
Qgs
gate-source charge
Qgs1
pre-VGS(th) gate-source charge
-
2.5
-
nC
Qgs2
post-VGS(th) gate-source charge
-
1.5
-
nC
Qgd
gate-drain (Miller) charge
-
5.6
-
nC
Vplat
plateau voltage
-
2.4
-
V
Qg(tot)
total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
-
12.5
-
nC
Ciss
input capacitance
1375 -
pF
output capacitance
VGS = 0 V; VDS = 12 V; f = 1 MHz;
Figure 14
-
Coss
-
640
-
pF
Crss
reverse transfer capacitance
-
250
-
pF
Ciss
input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
-
2120
-
pF
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG = 5.6 Ω
-
15
-
ns
-
38
-
ns
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
-
32
-
ns
tf
fall time
-
25
-
ns
-
0.86
1.2
V
-
34
-
ns
-
21
-
nC
Source-drain diode
VSD
source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 13
trr
reverse recovery time
Qr
recovered charge
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V;
VR = 25 V
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
5 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ar61
80
10 6 5 4.5
VGS (V) =
ID
(A)
03ar62
15
4
VGS (V) =
3.5
RDSon
(mΩ)
3.5
60
10
4
3
4.5
5
6
10
40
5
2.5
20
2
0
0
0
0.2
0.4
0.6
0.8
VDS (V)
1
0
Tj = 25 °C
20
40
60
ID (A)
80
Tj = 25 °C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
03ar63
80
03af18
2
ID
(A)
a
60
1.5
40
1
20
0.5
25 °C
Tj = 175 °C
0
0
1
2
3
VGS (V)
4
0
-60
Tj = 25 °C and 175 °C; VDS > ID × RDSon
60
120
Tj (°C)
180
R DSon
a = ----------------------------R DSon ( 25 °C )
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
9397 750 14707
Product data sheet
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
6 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03aa33
2.5
VGS(th)
(V)
2
1.5
03aa36
10-1
ID
(A)
max
10-2
typ
10-3
min
max
10-4
min
1
typ
10-5
0.5
10-6
0
-60
0
60
120
Tj (°C)
180
0
1
2
VGS (V)
3
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig 9. Gate-source threshold voltage as a function of
junction temperature
Fig 10. Sub-threshold drain current as a function of
gate-source voltage
03ar64
10
VGS
(V)
ID = 25 A
Tj = 25 °C
8
VDS
ID
6
VDS = 19 V
12 V
Vplat
4
VGS(th)
VGS
2
Qgs1
Qgs2
Qgs
0
0
10
20
30 QG (nC) 40
Qgd
Qg(tot)
003aaa508
ID = 25 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Gate charge waveform definitions
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
7 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
03ar65
80
03ar66
104
IS
(A)
C
(pF)
60
Ciss
103
40
175 °C
Coss
Tj = 25 °C
20
Crss
0
0.2
0.4
0.6
0.8
1
VSD (V)
102
10-1
1.2
Tj = 25 °C and 175 °C; VGS = 0 V
1
10
VDS (V)
102
VGS = 0 V; f = 1 MHz
Fig 13. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
03ar67
4000
C
(pF)
Ciss
3000
Crss
2000
1000
0
0
2
4
6
8
VGS (V)
10
VDS = 0 V
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
8 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
7. Package outline
SOT404
Plastic single-ended surface mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-10-13
05-02-11
SOT404
Fig 16. Package outline SOT404 (D2PAK)
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
9 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y
E
A
A
A1
b2
E1
mounting
base
D2
D1
HD
2
L
L2
1
L1
3
b1
b
w
M
c
A
e
e1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
b1
b2
c
D1
D2
min
E
E1
min
e
e1
HD
L
L1
min
L2
w
y
max
mm
2.38
2.22
0.93
0.73
0.89
0.71
1.1
0.9
5.46
5.00
0.56
0.20
6.22
5.98
4.0
6.73
6.47
4.45
2.285
4.57
10.4
9.6
2.95
2.55
0.5
0.9
0.5
0.2
0.2
OUTLINE
VERSION
SOT428
REFERENCES
IEC
JEDEC
JEITA
TO-252
SC-63
EUROPEAN
PROJECTION
ISSUE DATE
05-02-09
05-02-11
Fig 17. Package outline SOT428 (DPAK)
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
10 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
Plastic single-ended package (IPAK); 3 leads (in-line)
SOT533
E
A
E1
A1
D1
mounting
base
D2
L1
Q
L
1
2
3
e1
w
b
c
M
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D1
D2
E
mm
2.38
2.22
0.89
0.71
0.89
0.71
0.56
0.46
1.10
0.96
6.23
5.97
6.73
6.47
E1
e
e1
2.285
5.21
4.57
5.00 BSC (1) BSC (1)
L
L1 (2)
max
Q
w
9.6
9.2
2.7
1.1
1.0
0.3
Notes
1. Basic spacing between centers.
2. Terminal dimensions are uncontrolled within zone L1.
OUTLINE
VERSION
SOT533
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-09-22
05-02-11
TO-251
Fig 18. Package outline SOT533 (IPAK)
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
11 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
8. Revision history
Table 6:
Revision history
Document ID
Release
date
Data sheet
status
PHB_PHD_PHU108NQ03LT_3
20050418
Product data 2004070095
sheet
Modifications:
Change
notice
Doc.
number
Supersedes
9397 750
14707
PHP_PHB_PHD108NQ03LT-02
•
The format of this data sheet has been redesigned to comply with the new
presentation and information standard of Philips Semiconductors.
•
•
•
•
Removal of PHP108NQ03LT
•
•
•
•
Table 5 “Characteristics” RG, Qgs1, Qgs2 and Vplat tests added.
Addition of PHU108NQ03LT
Section 4 “Limiting values” ID, IDM, Ptot and ISM data corrected.
Table 5 “Characteristics” RDSon, Qg(tot), Qgs, Qgd, Ciss, Coss, Crss, td(on), tr, td(off), tf and
Qr test conditions and/or typical values modified.
Table 5 “Characteristics” VGS(th), Ciss, Crss and Qg(tot) data added.
Figure 2, 3, 4, 5, 6, 7, 8, 11,13 and 14 modified.
Figure 12 and 15 added.
PHP_PHB_PHD108NQ03LT-02
20020911
Product data -
9397 750
10159
PHP_PHB_PHD108NQ03LT-01
PHP_PHB_PHD108NQ03LT-01
20011218
Product data -
9397 750
09065
-
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
12 of 14
PHB/PHD/PHU108NQ03LT
Philips Semiconductors
N-channel TrenchMOS™ logic level FET
9. Data sheet status
Level
Data sheet status [1]
Product status [2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
12. Trademarks
TrenchMOS — is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: [email protected]
9397 750 14707
Product data sheet
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Rev. 03 — 18 April 2005
13 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOS™ logic level FET
14. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
11
12
13
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information . . . . . . . . . . . . . . . . . . . . 13
© Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 18 April 2005
Document number: 9397 750 14707
Published in The Netherlands