TI TMS57535A

TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
D Dot and N-Line Inversion Available
D Six-Bit (64 Gray-Scale) Digital Driver
D Mini-LVDS Level Input (Five Pairs of Serial
D
D
D
Data Inputs)
480 Output Ports (for UXGA Format)
VDD for Logic Port: 2.7 V to 3.6 V
VDD for LCD Driving Port: 8 V to 13.5 V
PACKAGE INFORMATION
The TCP’s external shape is customized. To
order the required shape, contact a TI sales
representative.
description
TMS57535A is a six bit (64 gray-scale) source
driver for TFT liquid-crystal display (LCD) with 480
output ports to deal with UXGA format.
PRODUCT PREVIEW
Reduction in the number of input ports and
electromagnetic interference (EMI) is expected
with the introduction of mini-LVDS (low voltage
differential signaling) interface at the input ports.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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1
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
functional block diagram
OUT479
OUT478
OUT480
OUT1 OUT2 OUT3
LCH
LP
Output Circuit
POL
Digital to Analog
Converter
GMA1 to GMA10
6
6
PRODUCT PREVIEW
LV5A
LV5B
6
480 × 6 Bit
× 2 Line Latch
TP1
LV0A
LV0B
LV1A
LV1B
6
Dn0 to Dn5
Serial
to
Parallel
Converter
Shift Register
CLKA
CLKB
SB
EIO1
EIO2
Logic Controller
L/R
2
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6
6
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
TCP pin assignments
TMS57535A
VSS1
VDD1
GMA10
GMA9
GMA8
GMA7
GMA6
SB
LCH
LP
L/R
VSS2
VSS*
LV5B
LV5A
VSS*
LV4B
LV4A
VSS*
LV3B
LV3A
VSS*
CLKB
CLKA
VSS*
LV2B
LV2A
VSS*
LV1B
LV1A
VSS*
LV0B
LV0A
VSS*
VDD2 (*1)
VDD2 (*2)
TP1
POL
EIO2
EIO1
GMA5
GMA4
GMA3
GMA2
GMA1
VDD1
VSS1
PRODUCT PREVIEW
OUT 480
OUT 479
OUT 478
OUT 477
OUT 476
OUT 5
OUT 4
OUT 3
OUT 2
OUT 1
NOTE: Pattern side up and no dimension specification for the TCP
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3
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
Terminal Functions
TERMINAL
NAME
DESCRIPTION
CLKA, CLKB
I
Clock (mini-LVDS). Shift clock (refer to Table 1)
LV0A, B–LV5A, B
I
Display data (mini-LVDS). Displays data with gray-scale data (6-bit) and control signal (RST=reset) (refer to Table
1)
I
Shift direction. Controls the direction of loaded data at the shift register (refer to Table 2)
L/R
EIO1, EIO2
PRODUCT PREVIEW
I/O
I/O
Start pulse. Input/Output definition of address shift register (refer to Table 2)
TP1
I
Input mode and output timing control. Changes the input mode, latches the registered data, and transfers to the DAC
at the rising edge. Voltage to LCD pixel is output at falling edge.
POL
I
Polarity control. Controls the polarity of the output. Defined by the POL signal at TP1 as H
(refer to Table 3)
LCH
I
Drivability control.
LCH = H: Higher drivability for heavy load
LCH = L; Normal drivability
LP
I
Low power mode selection. Decreases the charge/discharge current to output load. LP=H: low power mode. Refer
to the application notes.
SB
I
Bus-line set-back. Changes the data order of mini-LVDS input (see Table 1)
OUT1–OUT480
O
Output. Supplies voltage to each LCD pixel.
VDD1, VSS1
I
Power supply (output circuits). Power supply for output (driving) circuits
VDD2(*1)
VDD2(*2)
VSS2
VSS*
I
Power supply (control=logic circuits). VDD2(*1) is for mini-LVDS receiver and VDD2(*2) is for other logic circuits.
Supplies stable voltage to VDD2(*1).
VDD2(*1) and VDD2(*2) must be at the same electric potential.
Possible to wire the VSS potential between each mini-LVDS signal line from VSS* terminal, though no wiring, no
relation to function itself.
GMA1–GMA10
I
γ-corrected power supplies. Receives the external γ-corrected power supplies by using operational amplifiers.
Maintain the recommended operating conditions.
Table 1. Function Table (Bus-Line Set-Back)
PIN NAME
SB=L
LV0A
DUMMY
SB=H
LV4–
LV0B
DUMMY
LV4+
LV1A
LV0+
LV3–
LV1B
LV0–
LV3+
LV2A
LV1+
LV2–
LV2B
LV1–
LV2+
CLKA
CLK+
CLK–
CLKB
CLK–
CLK+
LV3A
LV2+
LV1–
LV3B
LV2–
LV1+
LV4A
LV3+
LV0–
LV4B
LV3–
LV0+
LV5A
LV4+
DUMMY
LV5B
LV4–
DUMMY
Suffix + indicates positive potential and – indicates negative potential
at each differential signal input pair.
4
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TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
Table 2. Function Table (L/R and EIOn)
L/R
EIO1
EIO2
Shift Direction
H
Right shift: in
Right shift: out
OUT1 → OUT480
L
Left shift: out
Left shift: in
OUT480 → OUT1
Table 3. Function Table (POL and Reference GAMMA)
POL
ODD-NUMBERED OUTPUT
EVEN-NUMBERED OUTPUT
H
GMA6 to GMA10
GMA1 to GMA5
L
GMA1 to GMA5
GMA6 to GMA10
detailed description
data mapping
Display and control data (RST) are input to LV0+,– to LV4+,–.
Data mapping is changed in response to the mode; the mode is changed by TP1.
PRODUCT PREVIEW
<Data Input Mode>
CLK+
LV0+
D00
D01
D02
D03
D04
D05
D00
LV1+
D10
D11
D12
D13
D14
D15
D10
LV2+
D20
D21
D22
D23
D24
D25
D20
LV3+
D30
D31
D32
D33
D34
D35
D30
LV4+
D40
D41
D42
D43
D44
D45
D40
Data Input Cycle
< Control Signal Input Mode >
CLK+
LV0+
RST
RST
RST
RST
RST
RST
RST
LV0–
There is no assignment from LV1+,– to LV4+,–. Therefore, they are don’t care.
Output timing and polarity are controlled by TP1 and POL signals. Refer to the Terminal Function table and
Table 3.
composition of display data
MSB
LSB
Dn5
Dn4
Dn3
Dn2
Dn1
Dn0
N = 0 to 4
relation between display data and output number
OUTPUT
OUT1
OUT2
OUT3
Display data
D00 to D05
D10 to D15
D20 to D25
–––––––
OUT478
OUT479
OUT480
D20 to D25
D30 to D35
D40 to D45
This relationship is irrespective of L/R condition.
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TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
detailed description (continued)
cascade
Multiple chips can be used in a cascade connection.
D Input EIO pad at lead (head) chip is fixed to H.
D Input EIO after secondary chips are connected to output EIO of lead chip.
Receiving the display data
D The lead (head) chip is set to control signal input mode (also called control mode), and the receivers at
LV0+,– and CLK+,– on all chips are activated by the rising edge of TP1.
D Input the reset (RST) signal to LV0+,– as L. This RST must be maintained over 200 ns after rising of TP1.
D Input RST as H to LV0+,–. The duration of H must be over 50 ns and at least three CLK cycles.
D Input the RST as L to LV0+,–; then change to the data input mode function. Input TP1 again when a second
RST is necessary.
PRODUCT PREVIEW
D Data sampling starts at the rising edge of CLK after reading of RST=L.
D The internal counter starts counting the data cycle for EIO signal generation at the same time data sampling
starts.
D When data sampling is finished, the receivers turn off.
D After the receivers turn off, keep the timing for at least five more CLK cycles until TP1 is applied.
D Figure 1 shows the rough timing chart from application of TP1 to the start of data sampling.
Read Reset (RST)
Read RST = L
CLK1
CLK+
LV0+
RST
Greater than 50 ns
and 3 CLK Cycles
LV1+ to LV4+
DATA1
DATA2
DATA1
DATA2
Start Data Sampling
200 ns
TP1
H
Input EIO
Control Signal Input Mode
Figure 1. Timing From Start to Sampling (Reference)
6
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Data Input Mode
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
detailed description (continued)
relation between input data and output voltage
The digital-to-analog converter (D/A) consists of resistors connected in a ladder configuration. Figure 2 shows
an outline of the relation between input data and γ-corrected voltages.
VDD1
GMA1
GMA2
GMA3
GMA4
GMA5
GMA6
GMA7
GMA8
GMA10
VSS1
0
10
20
30
3F
Input Data – Hex
Figure 2. γ-Corrected Power Supplies
ladder resistors
Resistors are connected to each terminal of the power supplies for γ-corrected supplies, and the resistance ratio
is given in Table 4.
Table 4. Resistor Ratio
GMA1
GMA6
R1
GMA2
R5
GMA7
R2
GMA3
R6
GMA8
R3
GMA4
RESISTOR
R1, R8
RATIO
161
R2, R7
55
R3, R6
R4, R5
32
69
R7
GMA9
R4
GMA5
Positive Polarity
R8
GMA10
Negative Polarity
Figure 3. Ladder Resistors Connection
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7
PRODUCT PREVIEW
GMA9
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
detailed description (continued)
relation between input data and output voltage
Table 5. Positive Polarity
PRODUCT PREVIEW
DATA
(HEX)
OUTPUT VOLTAGE
DATA
(HEX)
OUTPUT VOLTAGE
00
GMA1
20
GMA3
01
GMA2+(GMA1–GMA2)X 145/161
21
GMA4+(GMA3–GMA4)X 30/32
02
GMA2+(GMA1–GMA2)X 130/161
22
GMA4+(GMA3–GMA4)X 28/32
03
GMA2+(GMA1–GMA2)X 116/161
23
GMA4+(GMA3–GMA4)X 26/32
04
GMA2+(GMA1–GMA2)X 103/161
24
GMA4+(GMA3–GMA4)X 24/32
05
GMA2+(GMA1–GMA2)X 91/161
25
GMA4+(GMA3–GMA4)X 22/32
06
GMA2+(GMA1–GMA2)X 80/161
26
GMA4+(GMA3–GMA4)X 20/32
07
GMA2+(GMA1–GMA2)X 69/161
27
GMA4+(GMA3–GMA4)X 18/32
08
GMA2+(GMA1–GMA2)X 59/161
28
GMA4+(GMA3–GMA4)X 16/32
09
GMA2+(GMA1–GMA2)X 49/161
29
GMA4+(GMA3–GMA4)X 14/32
0A
GMA2+(GMA1–GMA2)X 41/161
2A
GMA4+(GMA3–GMA4)X 12/32
0B
GMA2+(GMA1–GMA2)X 33/161
2B
GMA4+(GMA3–GMA4)X 10/32
0C
GMA2+(GMA1–GMA2)X 26/161
2C
GMA4+(GMA3–GMA4)X 8/32
0D
GMA2+(GMA1–GMA2)X 19/161
2D
GMA4+(GMA3–GMA4)X 6/32
0E
GMA2+(GMA1–GMA2)X 12/161
2E
GMA4+(GMA3–GMA4)X 4/32
0F
GMA2+(GMA1–GMA2)X 6/161
2F
GMA4+(GMA3–GMA4)X 2/32
10
GMA2
30
GMA4
11
GMA3+(GMA2–GMA3)X 49/55
31
GMA5+(GMA4–GMA5)X 67/69
12
GMA3+(GMA2–GMA3)X 44/55
32
GMA5+(GMA4–GMA5)X 65/69
13
GMA3+(GMA2–GMA3)X 39/55
33
GMA5+(GMA4–GMA5)X 63/69
14
GMA3+(GMA2–GMA3)X 34/55
34
GMA5+(GMA4–GMA5)X 61/69
15
GMA3+(GMA2–GMA3)X 30/55
35
GMA5+(GMA4–GMA5)X 59/69
16
GMA3+(GMA2–GMA3)X 26/55
36
GMA5+(GMA4–GMA5)X 56/69
17
GMA3+(GMA2–GMA3)X 22/55
37
GMA5+(GMA4–GMA5)X 53/69
18
GMA3+(GMA2–GMA3)X 19/55
38
GMA5+(GMA4–GMA5)X 50/69
19
GMA3+(GMA2–GMA3)X 16/55
39
GMA5+(GMA4–GMA5)X 46/69
1A
GMA3+(GMA2–GMA3)X 13/55
3A
GMA5+(GMA4–GMA5)X 42/69
1B
GMA3+(GMA2–GMA3)X 10/55
3B
GMA5+(GMA4–GMA5)X 37/69
1C
GMA3+(GMA2–GMA3)X 8/55
3C
GMA5+(GMA4–GMA5)X 32/69
1D
GMA3+(GMA2–GMA3)X 6/55
3D
GMA5+(GMA4–GMA5)X 26/69
1E
GMA3+(GMA2–GMA3)X 4/55
3E
GMA5+(GMA4–GMA5)X 16/69
1F
GMA3+(GMA2–GMA3)X 2/55
3F
GMA5
NOTE: GMA5 and GMA6 are not connected in the chip.
8
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TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
relation between input data and output voltage (continued)
Table 6. Negative Polarity
OUTPUT VOLTAGE
DATA
(HEX)
OUTPUT VOLTAGE
00
GMA10
20
GMA8
01
GMA10+(GMA9–GMA10)X 16/161
21
GMA8+(GMA7–GMA8)X 2/32
02
GMA10+(GMA9–GMA10)X 31/161
22
GMA8+(GMA7–GMA8)X 4/32
03
GMA10+(GMA9–GMA10)X 45/161
23
GMA8+(GMA7–GMA8)X 6/32
04
GMA10+(GMA9–GMA10)X 58/161
24
GMA8+(GMA7–GMA8)X 8/32
05
GMA10+(GMA9–GMA10)X 70/161
25
GMA8+(GMA7–GMA8)X 10/32
06
GMA10+(GMA9–GMA10)X 81/161
26
GMA8+(GMA7–GMA8)X 12/32
07
GMA10+(GMA9–GMA10)X 92/161
27
GMA8+(GMA7–GMA8)X 14/32
08
GMA10+(GMA9–GMA10)X 102/161
28
GMA8+(GMA7–GMA8)X 16/32
09
GMA10+(GMA9–GMA10)X 112/161
29
GMA8+(GMA7–GMA8)X 18/32
0A
GMA10+(GMA9–GMA10)X 120/161
2A
GMA8+(GMA7–GMA8)X 20/32
OB
GMA10+(GMA9–GMA10)X 128/161
2B
GMA8+(GMA7–GMA8)X 22/32
OC
GMA10+(GMA9–GMA10)X 135/161
2C
GMA8+(GMA7–GMA8)X 24/32
OD
GMA10+(GMA9–GMA10)X 142/161
2D
GMA8+(GMA7–GMA8)X 26/32
OE
GMA10+(GMA9–GMA10)X 149/161
2E
GMA8+(GMA7–GMA8)X 28/32
OF
GMA10+(GMA9–GMA10)X 155/161
2F
GMA8+(GMA7–GMA8)X 30/32
10
GMA9
30
GMA7
11
GMA9+(GMA8–GMA9)X 6/55
31
GMA7+(GMA6–GMA7)X 2/69
12
GMA9+(GMA8–GMA9)X 11/55
32
GMA7+(GMA6–GMA7)X 4/69
13
GMA9+(GMA8–GMA9)X 16/55
33
GMA7+(GMA6–GMA7)X 6/69
14
GMA9+(GMA8–GMA9)X 21/55
34
GMA7+(GMA6–GMA7)X 8/69
15
GMA9+(GMA8–GMA9)X 25/55
35
GMA7+(GMA6–GMA7)X 10/69
16
GMA9+(GMA8–GMA9)X 29/55
36
GMA7+(GMA6–GMA7)X 13/69
17
GMA9+(GMA8–GMA9)X 33/55
37
GMA7+(GMA6–GMA7)X 16/69
18
GMA9+(GMA8–GMA9)X 36/55
38
GMA7+(GMA6–GMA7)X 19/69
19
GMA9+(GMA8–GMA9)X 39/55
39
GMA7+(GMA6–GMA7)X 23/69
1A
GMA9+(GMA8–GMA9)X 42/55
3A
GMA7+(GMA6–GMA7)X 27/69
1B
GMA9+(GMA8–GMA9)X 45/55
3B
GMA7+(GMA6–GMA7)X 32/69
1C
GMA9+(GMA8–GMA9)X 47/55
3C
GMA7+(GMA6–GMA7)X 37/69
1D
GMA9+(GMA8–GMA9)X 49/55
3D
GMA7+(GMA6–GMA7)X 43/69
1E
GMA9+(GMA8–GMA9)X 51/55
3E
GMA7+(GMA6–GMA7)X 53/69
1F
GMA9+(GMA8–GMA9)X 53/55
3F
GMA6
PRODUCT PREVIEW
DATA
(HEX)
NOTE: GMA5 and GMA6 are not connected in the chip.
electrical/timing specifications
Basically, the ground-level voltage is VSS1 = VSS2 = 0 V.
Electrical and timing characteristics are assured under the recommended operating conditions.
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TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage at logic port, VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5 V
Supply voltage at driver port, VDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 14.0 V
Input voltage: GMA1 to GMA10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD1 + 0.5 V
Except GMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD2 + 0.5 V
Output voltage: EIO1, EIO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD2 + 0.5 V
OUT1 to OUT480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD1 + 0.5 V
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
D Keep the order of the VDD2 input port except GMA, VDD1, and GMA1 to GMA10 when turning on the device,
and reverse the order when turning it off.
recommended operating conditions
PRODUCT PREVIEW
MIN
Supply voltage
γ-corrected
corrected supply voltage
VDD1
VDD2
NOM
8
2.7
GMA1 to GMA5
Clock frequency, CLK
3
146
–10
EIO1, EIO2
capacitance CI
Input capacitance,
POST OFFICE BOX 655303
V
V
152
MHz
125
pF
75
°C
10
Except EIO and GMAn
5
NOTE: Relation of γ-corrected input voltage
VDD1>GMA1, GMAn ≤ GMAn+1 (n=1 to 9), GMA10>VSS1
10
3.6
VDD1–0.2
1/2VDD1
Load capacitance, driver output (CL), OUT1 to OUT480
Operating free-air temperature range, TA
UNIT
13.5
1/2VDD1
VSS1+0.2
GMA6 to GMA10
MAX
• DALLAS, TEXAS 75265
pF
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
TEST
CONDITIONS
PARAMETERS
MIN
TYP
MAX
UNIT
VIH1
High-level input voltage
EIO1, EIO2,
L/R, TP1, LCH
LP, SB, POL
0.7×VDD2
VDD2
V
VIL1
Low-level input voltage
EIO1, EIO2,
L/R, TP1, LCH
LP, SB, POL
0
0.25×VDD2
V
II(lkg)
Input leakage current
EIO1, EIO2,
L/R, TP1, LCH
LP, SB, POL,
CLKA,B,
LV0A,B to LV5A,B
–1
1
µA
VI
Mini-LVDS input voltage
(center)
CLKA,B,
LV0A.B to LV5A,B
0.3+(VID/2)
(VDD2–1.2)–VID/2
V
VID
Mini-LVDS differential voltage
(amplitude: peak to peak)
CLKA,B,
LV0A,B to LV5A,B
0.2
0.6
V
IO(chg)
Output current
OUT1 to OUT480
IO(dis)
VX = VDD1–0.2
VO = VX–1.0
TBD
µA
VX = VSS+0.2
VO = VX+1.0
TBD
µA
δVO
Output swing difference
deviation
OUT1 to OUT480
See Note 1
±10
mV
δVO(avg)
Averaged output voltage
deviation
OUT1 to OUT480
See Note 2
±10
mV
RGMA
Ladder resistance
GMA1–GMA5
GMA6–GMA10
VO
Output voltage range
OUT1 to OUT480
Ω
15850
VSS1+0.2
PRODUCT PREVIEW
electrical characteristics
VDD1–0.2
V
ID(dp)
Driver port dynamic current
consumption
VDD1–VSS1
Black raster,
VDD1 = 13.5 V,
TP1 = 10 µs
No load
IS(dp)
Driver port static current
consumption
VDD1–VSS1
Black raster,
VDD1 = 13.5 V,
No load
TBD
mA
ID(lp)
Logic port dynamic current
consumption
VDD2–VSS2
TP1 = 10 µs,
fCLK = 110 MHz,
Checkered
TBD
mA
IS(lp)
Logic port static current
consumption
VDD2–VSS2
No clock, no
input
TBD
mA
TBD
mA
NOTES: 1. Amplitude offset when all ports output the same data
2. Deviation in averaged amplitude offset between chips
3. Input the same value to all pairs of mini-LVDS inputs and mini-LVDS differential voltage ports.
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11
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
timing requirements
MIN
TYP
t1
t2
Clock pulse cycle
PARAMETERS
6.5
6.8
Clock pulse high period
2.5
ns
t3
t4
Clock pulse low period
2.5
ns
Data setup time
1.25
ns
t5
t6
Data hold time
1.25
ns
EIO setup time
–1
ns
t8
t9
EIO signal delay time
t10
t15
CLK, LV0 to LV5 falling time
PRODUCT PREVIEW
t16
TEST CONDITIONS
Load = 25 pF
16
CLK, LV0 to LV5 rising time
Driver output delay time (see Note 4)
MAX
UNIT
ns
TBD
ns
0.5
ns
0.5
ns
Target voltage ±0.1 VDD1
4
6-bit accuracy
8
µss
50 ns over 3
CLK cycles
t20
Reset (RST) high period
t25
t28
TP1 high period
0.2
µs
POL setup time
–5
ns
t29
POL hold time
6.0
ns
t30
Receiver off to TP1 timing
t31
t32
TP1 to reset input time
CLK
cycles
5
Reset low to TP1 rising time
200
ns
0
ns
NOTE 4: Output load condition:
R
R
C
C
R
R
C
R
C
C
R = 4 kΩ
C = 25 pF
t1
t2
t3
CLK–
80%
50%
t10
t4
LV0+,–
to
LV4+,–
t5
t4
t9
t5
80%
50%
VID
20%
t10
Figure 4. Data Read Timing
12
VID
20%
CLK+
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
t9
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
Read RST = H
Read RST = L
Starting Data Sampling
1
2
CLK+
50%
LV0+,– NA
50%
RST = L RST = L RST = H RST = H RST = H
NA
RST = L
NA
Data
Data
Data
NA
NA
Data
Data
Data
t20
LV1+,–
to NA
LV4+,–
NA
NA
t32
NA
NA
NA
NA
t31
TP1
70%
EIO (IN) H
Control Signal Input Mode
Data Input Mode
PRODUCT PREVIEW
NOTE: No assigned data for NA
Figure 5. Input Data Timing (Lead Chip)
276
277
CLK+
LV0+,–
to
LV4+,–
EIO (OUT)
EIO (IN)
280
50%
Data
Data
Data
50%
Data
Data
288
286
50%
Data
Data
289(1)
50%
Data
t8
t8
70%
25%
Data
Data
t6
t6
70%
25%
Data
Data
Data
Figure 6. Input Data Timing (Cascade Port)
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• DALLAS, TEXAS 75265
13
TMS57535A
480CH 64G/S COLOR TFT SOURCE DRIVER
SLDS142 – AUGUST 2001
Last Data Timing
288
289
292
50%
CLK+
50%
LV0+,–
Data
Data
NA
NA
NA
NA
NA
NA
NA
NA
LV1
to
LV4+,–
Data
Data
NA
NA
NA
NA
NA
NA
NA
NA
RST = L RST = L RST = L
NA
NA
t32
TP1
25%
70%
t30
NOTE: No assigned data for NA
PRODUCT PREVIEW
Figure 7. Last Data Sampling to TP1 Timing
t25
TP1
70%
25%
t28
POL
70%
25%
t29
70%
70%
25%
25%
t16
t15
OUTn
(n = 1 to 480)
Hi-Z
Figure 8. Output Timing
Dxx
n Line
n+1 Line
n–1 Line
n Line
n+2 Line
n+3 Line
TP1
OUT
n+1 Line
Figure 9. Relation Between Input and Output Data
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
n+2 Line
NA
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