ISSI IS61QDB24M18

72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
.
A
May 2009
Features
• 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data
valid window.
• Separate read and write ports with concurrent
read and write operations.
• Two echo clocks (CQ and CQ) that are delivered
simultaneously with data.
• +1.8V core power supply and 1.5, 1.8V VDDQ,
used with 0.75, 0.9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls,
byte writes, data in, and data outputs.
• Synchronous pipeline read with early write operation.
• Full data coherency.
• Double data rate (DDR) interface for read and
write input ports.
• Boundary scan using limited set of JTAG 1149.1
functions.
• Fixed 2-bit burst for read and write operations.
• Byte write capability.
• Clock stop support.
• Fine ball grid array (FBGA) package
- 15mm x 17mm body size
- 1mm pitch
- 165-ball (11 x 15) array
• Two input clocks (K and K) for address and control registering at rising edges only.
• Two input clocks (C and C) for data output control.
• Programmable impedance output drivers via 5x
user-supplied precision resistor.
Description
The 72Mb IS61QDB22M36 and
IS61QDB24M18 are synchronous, high-performance CMOS static random access memory
(SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth
Table on page 8 for a description of the basic operations of these SRAMs.
The input address bus operates at double data rate.
The following are registered internally on the rising
edge of the K clock:
•
•
•
•
•
Read address
Read enable
Write enable
Byte writes
Data-in for early writes
The following are registered on the rising edge of
the K clock:
Integrated Silicon Solution, Inc.
Rev. A
05/14/09
• Write address
• Byte writes
• Data-in for second burst addresses
Byte writes can change with the corresponding datain to enable or disable writes on a per-byte basis. An
internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The
first data-in burst is clocked at the same time as the
write command signal, and the second burst is timed
to the following rising edge of the K clock.
During the burst read operation, the data-outs from
the first burst are updated from output registers off
the second rising edge of the C clock (1.5 cycles
later). The data-outs from the second burst are
updated with the third rising edge of the C clock. The
K and K clocks are used to time the data-outs whenever the C and C clocks are tied high.
The device is operated with a single +1.8V power
supply and is compatible with HSTL I/O interfaces.
1
372Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
x36 FBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
NC/SA*
W
BW2
K
BW1
R
SA
10
11
A
CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
SA
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
9
10
11
NC/SA*
NC/SA*
CQ
Note*: The following pins are reserved for higher densities: 10A for 144Mb, and 2A for 288Mb.
x18 FBGA Pinout (Top View)
1
2
3
4
5
6
A
CQ
NC/SA*
B
NC
Q9
C
NC
D
7
8
SA
W
BW1
K
NC
R
SA
SA
CQ
D9
SA
NC
K
BW0
SA
NC
NC
Q8
NC
D10
VSS
SA
SA
SA
VSS
NC
Q7
D8
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
Note*: The following pins are reserved for higher densities: 2A for 144Mb.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
ISSI
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
®
Pin Description
Symbol
Pin Number
Description
K, K
6B, 6A
Input clock.
C, C
6P, 6R
Input clock for output data control.
CQ, CQ
11A, 1A
Output echo clock.
Doff
1H
DLL disable when low.
SA
3A, 9A, 4B, 8B, 5C, 6C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P
3R, 4R, 5R, 7R, 8R, 9R
2M x 36 address inputs.
SA
10A, 3A, 9A, 4B, 8B, 5C, 6C, 7C, 5N, 6N, 7N, 4P, 5P, 7P, 8P, 3R
4R, 5R, 7R, 8R, 9R
4M x 18 address inputs.
D0–D8
D9–D17
D18–D26
D27–D35
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
1C, 1D, 2E, 1G, 1J, 2K, 1M, 1N, 2P
2M x 36 data inputs.
Q0–Q8
Q9–Q17
Q18–Q26
Q27–Q35
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
9P, 9N, 10L, 9K, 9G, 10F, 9E, 9D, 10B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
1B, 2C, 1E, 1F, 2J, 1K, 1L, 2M, 1P
2M x 36 data outputs.
D0–D8
D9–D17
10P, 11N, 11M, 10K, 11J, 11G, 10E, 11D, 11C
3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N
4M x 18 data inputs.
Q0–Q8
Q9–Q17
11P, 10M, 11L, 11K, 10J, 11F, 11E, 10C, 11B
2B, 3D, 3E, 2F, 3G, 3K, 2L, 3N, 3P
4M x 18 data outputs.
W
4A
Write control, active low.
R
8A
Read control, active low.
BW0, BW1, BW2, BW3 7B, 7A, 5A,5B
2M x 36 byte write control, active low.
BW0, BW1
7B, 5A
4M x 18 byte write control, active low.
VREF
2H, 10H
Input reference level.
VDD
5F, 7F, 5G, 7G, 5H, 7H, 5J, 7J, 5K, 7K
Power supply.
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output power supply.
VSS
4C, 8C, 4D, 5D, 6D, 7D, 8D, 5E, 6E, 7E, 6F, 6G, 6H, 6J,
6K, 5L, 6L, 7L, 4M, 5M, 6M, 7M, 8M, 4N, 8N
Ground
ZQ
11H
Output driver impedance control.
TMS, TDI, TCK
10R, 11R, 2R
IEEE 1149.1 test inputs (1.8V LVTTL levels).
TDO
1R
IEEE 1149.1 test output (1.8V LVTTL level).
NC
2A, 10A
2Mx36, No Connect
NC
2A, 7A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,1F,9F,10F,
4Mx18, No Connect
1G, 9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M,2M,9M,1N,9N,10N,
1P, 2P, 9P
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
3
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Block Diagram
D (Data-In)
36 (or 18)
Data
Reg
36 (or 18)
36 (or 18)
BWx
4 (or 2)
2M x 36
(4M x 18)
Memory
Array
72
(or 36)
Output Driver
W
Control
Logic
72
(or 36)
Output Select
R
Add
Reg
Sense Amps
20 (or 21)
Write/Read Decode
Address
Output Reg
Write Driver
20 (or 21)
36 (or 18)
Q (Data-Out)
CQ, CQ
(Echo Clock Out)
K
K
C
Clock
Gen
Select Output Control
C
SRAM Features
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R in active
low state at the rising edge of the K clock. A second set of clocks, C and C, are used to control the timing to
the outputs. A set of free-running echo clocks, CQ and CQ, are produced internally with timings identical to
the data-outs. The echo clocks can be used as data capture clocks by the receiver device.
When the C and C clocks are connected high, the K and K clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked 1.5 cycles later by the rising edge of the K clock.
The data corresponding to the second burst is clocked 2 cycles later by the following rising edge of the K
clock.
A NOP operation (R is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every rising edge of the K clock whenever W is low. The write
address is provided 0.5 cycles later, registered by the rising edge of K. Again, the write always occurs in
bursts of two.
The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the
burst, is presented 0.5 cycles earlier or at the rising edge of the preceding K clock. The data-in corresponding
to the second write burst address follows next, registered by the rising edge of K.
The data-in provided for writing is initially kept in write buffers. The information on these buffers is written into
the array on the following write cycle. A read cycle to the last write address produces data from the write
buffers. Similarly, a read address followed by the same write address produces the latest write data. The
SRAM maintains data coherency.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
During a write, the byte writes independently control which byte of any of the two burst addresses is written
(see X18/X36 Write Truth Tables on page 9 and Timing Reference Diagram for Truth Table on page 8).
Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.
RQ Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM
to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance
driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range
of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in
Programmable Impedance Output Driver DC Electrical Characteristics on page 13. The RQ resistor should
be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded
ZQ trace must be less than 3 pF.
The ZQ pin can also be directly connected to VDDQ to obtain a minimum impedance setting. ZQ must never
be connected to VSS.
Programmable Impedance and Power-Up Requirements
Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by
drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable
impedances values. The final impedance value is achieved within 1024 clock cycles.
Single Clock Mode
This device can be also operated in single-clock mode. In this case, C and C are both connected high at
power-up and must never change. Under this condition, K and K will control the output timings.
Either clock pair must have both polarities switching and must never connect to VREF, as they are not differential clocks
Depth Expansion
Separate input and output ports enable easy depth expansion, as each port can be selected and deselected
independently. Read and write operations can occur simultaneously without affecting each other. Also, all
pending read and write transactions are always completed prior to deselecting the corresponding port.
In the following application example, the second pair of C and C clocks is delayed such that the return data
meets the data setup and hold times at the memory controller.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
5
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
Application Example
SRAM #1
D
Vt
R
SA
ZQ R=250Ω
CQ
CQ
Q
R W BW0 BW1 C C K K
SRAM #4
ZQ
R=250Ω
CQ
CQ
D
Q
R W BW0 BW1 C C K K
SA
Data In
Data Out
Vt
Address
R
R
Vt
W
BW
Memory
Controller
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Ω Vt=VREF
SRAM1 Input CQ
SRAM1 Input CQ
SRAM4 Input CQ
SRAM4 Input CQ
Power-Up and Power-Down Sequences
The following sequence is used for power-up:
1. The power supply inputs must be applied in the following order while keeping Doff in LOW logic state:
1) VDD
2) VDDQ
3) VREF
2. Start applying stable clock inputs (K, K, C, and C).
3. After clock signals have stabilized, change Doff to HIGH logic state.
4. Once the Doff is switched to HIGH logic state, wait an additional 1024 clock cycles to lock the DLL.
NOTES:
1. The power-down sequence must be done in reverse of the power-up sequence.
2. VDDQ can be allowed to exceed VDD by no more than 0.6V.
3. VREF can be applied concurrently with VDDQ.
6
Integrated Silicon Solution, Inc.
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
State Diagram
Power Up
Read NOP
Read
Write
Read
Read
Write
Load New
Read Address
Always
(fixed)
Write NOP
Load New
Write Address
Read
DDR Read
Write
Write
Always
(fixed)
DDR Write
Notes: 1. Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.
2. Read refers to read active status with R = low. Read refers to read inactive status with R = high.
3. Write refers to write active status with W = low. Write refers to write inactive status with W = high.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
The Timing Reference Diagram for Truth Table on page 8 is helpful in understanding the clock and write truth
tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. All read
and write commands are issued at the beginning of cycle “t”.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
7
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Timing Reference Diagram for Truth Table
Cycle
t
t+1
Read A
Write B
t+2
Read C
t+3
Write D
K Clock
K Clock
W
R
BW 0,1,2,3
Address
A
B
C
D
Data-In
DB
DB+1
DD
DD+1
QA
Data-Out
QA+1
QC+2
QC+3
C Clock
C Clock
CQ Clock
CQ Clock
Clock Truth Table (Use the following table with the Timing Reference Diagram for Truth Table.)
Clock
Controls
Data-In
Data-Out
Mode
K
R
W
DB
DB+1
QA
QA+1
Stop Clock
Stop
X
X
Previous state
Previous State
Previous state
Previous state
No Operation (NOP)
L→ H
H
H
X
X
High-Z
High-Z
Read A
L→ H
L
X
X
X
D out at C
(t + 1.5)
D out at C (t + 2)
Write B
L→ H
X
L
D in at K (t)
D in at K
(t + 0.5)
X
X
Notes:
1. The internal burst counter is always fixed as two-bit.
2. X = don’t care; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R is active low
4. A write operation is started when control signal W is active low. Before entering into the stop clock, all pending read and write
commands must be completed.
5. For timing definitions, refer to the AC Characteristics on page 15,16. Signals must have AC specifications at timings indicated in
parenthesis with respect to switching clocks K, K, C, and C.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
X36 Write Truth Table Use the following table with the Timing Reference Diagram for Truth Table on
page 8.
K
(t + 0.5)
BW0
BW1
BW2
BW3
DB
L→H
L
H
H
H
D0-8 (t)
Write Byte 1
L→H
H
L
H
H
D9-17 (t)
Write Byte 2
L→H
H
H
L
H
D18-26 (t)
Write Byte 3
L→H
H
H
H
L
D27-35 (t)
Write All Bytes
L→H
L
L
L
L
D0-35 (t)
Abort Write
L→H
H
H
H
H
Don’t care
Operation
K(t)
Write Byte 0
DB+1
Write Byte 0
L→H
L
H
H
H
D0-8 (t + 0.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t + 0.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (t + 0.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (t + 0.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t + 0.5)
Abort Write
L→H
H
H
H
H
Don’t care
Notes;
1. For all cases. W must be active low during the rising edge of K occurring at time t.
2. For timing definitions, refer to the AC Characteristics on page 15,16. Signals must have AC specifications with respect to switching
clocks K and K.
X18 Write Truth Table (Use this table with the Timing Reference Diagram for Truth Table on page 8.)
K
(t + 0.5)
BW0
BW1
DB
L→H
L
H
D0–8 (t)
Write Byte 1 on B
L→H
H
L
D9–17 (t)
Write All Bytes on B
L→H
L
L
D0–17 (t)
Abort Write on B
L→H
H
H
Don’t care
Operation
K(t)
Write Byte 0 on B
DB+1
Write Byte 1 on B+1
L→H
L
H
D0–8(t + 0.5)
Write Byte 2 on B+1
L→H
H
L
D9–17(t + 0.5)
Write All Bytes on B+1
L→H
L
L
D0–17(t + 0.5)
Abort Write on B+1
L→H
H
H
Don’t care
Notes;
1. Refer to Timing Reference Diagram for Truth Table on page 8. Cycle time starts at n and is referenced to the K clock.
2. For all cases, W must be active low during the rising edge of K occurring at t.
3. For timing definitions, refer to the AC Characteristics on page 15,16. Signals must have AC specs with respect to switching clocks K
and K.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
9
ISSI
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
®
Absolute Maximum Ratings
Item
Symbol
Rating
Units
Power supply voltage
VDD
-0.5 to 2.9
V
Output power supply voltage
VDDQ
-0.5 to 2.9
V
Input voltage
VIN
-0.5 to VDD+0.3
V
VDOUT
-0.5 to 2.6
V
Data out voltage
Operating temperature
1
o
TA
0 to 70
Junction temperature
TJ
110
o
Storage temperature
TSTG
-55 to +125
o
C
C
C
Note: Stresses greater than those listed in this table can cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this datasheet is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
Recommended DC Operating Conditions (TA = 0 to +70° C)
Parameter
Maximum
Units
Notes
1.8 - 5%
1.8 + 5%
V
1
VDDQ
1.4
1.9
V
1
Input high voltage
VIH
VREF +0.1
VDDQ + 0.3
V
1, 2
Input low voltage
VIL
-0.3
VREF - 0.1
V
1, 3
VREF
0.68
0.95
V
1, 5
VIN - CLK
-0.3
VDDQ + 0.3
V
1, 4
Supply voltage
Output driver supply voltage
Input reference voltage
Clocks signal voltage
1.
2.
3.
4.
5.
Symbol
Minimum
VDD
Typical
All voltages are referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
VIH(Max) AC = See 0vershoot and Undershoot Timings.
VIL(Min) AC = See 0vershoot and Undershoot Timings.
VIN-CLK specifies the maximum allowable DC excursions of each clock (K, K, C, and C).
Peak-to-peak AC component superimposed on VREF may not exceed 5% of VREF.
0vershoot and Undershoot Timings
20% Min Cycle Time
VIL(Min) AC
VDDQ+0.6V
Undershoot Timing
VDDQ
GND
VIH(Max) AC
Overshoot Timing
GND-0.6V
20% Min Cycle Time
PBGA Thermal Characteristics
Item
Symbol
Rating
Units
Thermal resistance junction to ambient (airflow = 1m/s)
RΘJA
18.6
° C/W
Thermal resistance junction to case
RΘJC
4.3
° C/W
Thermal resistance junction to pins
RΘJB
1.77
° C/W
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
11
ISSI
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
Capacitance (TA = 0 to +
®
C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter
Symbol
Test Condition
Maximum
Units
Input capacitance
CIN
VIN = 0V
4
pF
Data-in capacitance (D0–D35)
CDIN
VDIN = 0V
4
pF
Data-out capacitance (Q0–Q35)
COUT
VOUT = 0V
4
pF
Clocks Capacitance (K, K, C, C)
DC Electrical Characteristics (TA = 0 to + 70C, V DD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
x36 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
IDD33
—
—
800
700
600
x18 average power supply operating current
(IOUT = 0, V IN = VIH or V IL)
IDD33
IDD40
IDD50
—
—
Power supply standby current
(R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0)
ISB
Notes
mA
1, 3
800
700
600
mA
1, 3
—
200
mA
1
Input leakage current, any input (except JTAG)
(VIN = VSS or V DD)
ILI
-2
+2
uA
Output leakage current
(VOUT = VSS or V DDQ, Q in High-Z)
ILO
-2
+2
uA
Output “high” level voltage (IOH = -6mA)
VOH
VDDQ -0.4
VDDQ
V
Output “low” level voltage (IOL = +6mA)
VOL
VSS
VSS+0.4
ILIJTAG
-100
+100
JTAG leakage current
(VIN = VSS or V DD)
1.
2.
3.
4.
5.
12
IDD40
IDD50
Units
V
uA
2, 4
2, 4
5
IOUT = chip output current.
Minimum impedance output driver.
The numeric suffix indicates the part operating at speed, as indicated in AC Characteristics on page 15, 16
JEDEC Standard JESD8-6 Class 1 compatible.
For JTAG inputs only.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Typical AC Input Characteristics
Item
Symbol
Minimum
AC input logic high
VIH (ac)
VREF + 0.2
AC input logic low
VIL (ac)
Clock input logic high (K, K, C, C)
VIH-CLK (ac)
Clock input logic low (K, K, C, C)
VIL-CLK (ac)
1.
2.
3.
4.
Maximum
Notes
1, 2, 3, 4
VREF - 0.2
VREF + 0.2
1, 2, 3, 4
1, 2, 3
VREF - 0.2
1, 2, 3
The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
Performance is a function of VIH and VIL levels to clock inputs.
See the AC Input Definition diagram.
See the AC Input Definition diagram. The signals should swing monotonically with no steps rail-to-rail with input signals never ringing back past VIH (AC) and VIL (AC) during the input setup and input hold window. VIH (AC) and VIL (AC) are used for timing purposes only.
AC Input Definition
K
VREF
K
VRAIL
VIH (AC)
VREF
Setup
Time
Hold
Time
VIL (AC)
V-RAIL
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +70° C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Minimum
Maximum
Units
Notes
Output “high” level voltage
VOH
VDDQ / 2
VDDQ
V
1, 3
Output “low” level voltage
VOL
VSS
VDDQ / 2
V
2, 3
 VDDQ-
1. IOH =  ----------------2 
⁄
 RQ
--------
 5  ± 15% @ VOH = VDDQ / 2 For: 175Ω ≤RQ ≤350Ω.
RQ
 VDDQ- ⁄  -------2. IOL =  ---------------- 5  ± 15% @ VOL = VDDQ / 2 For: 175Ω ≤RQ ≤350Ω.
2 
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
13
ISSI
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
®
AC Test Conditions (TA = 0 to + 70C, VDD = 1.8V -5%, +5%, VDDQ = 1.5, 1.8V)
Parameter
Symbol
Conditions
Units
VDDQ
1.5, 1.8
V
Input high level
VIH
VREF + 0.5
V
Input Low Level
VIL
VREF - 0.5
V
0.75, 0.9
V
Output driver supply voltage
Input reference voltage
VREF
Input rise time
TR
0.35
ns
Input fall time
TF
0.35
ns
Output timing reference level
VREF
V
Clock Reference Level
VREF
V
Notes
1, 2
Output load conditions
1. See AC Test Loading.
2. Parameter tested with RQ = 250 and VDDQ = 1.5V.
AC Test Loading
50
Q
0.75, 0.9V
50
5pF
Test
Comparator
0.75, 0.9V
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
AC Characteristics (TA = 0 to + 70C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
33
(300MHz)
Units
Min
Max
3.3
7.5
ns
0.2
ns
Notes
Clock
Cycle time (K, K, C, C)
tKHKH
Clock phase jitter (K, K, C, C)
tKC-VAR
Clock high pulse (K, K, C, C)
tKHKL
1.32
ns
Clock low pulse (K, K, C, C)
tKLKH
1.32
ns
Clock to clock (KH>KH, CH>CH)
tKHKH
1.49
Clock to data clock (KH>CH, KH>CH)
tKHCH
0.0
tKC-lock
1024
DLL lock (K, C)
Doff Low period to DLL reset
ns
0.8
ns
cycle
ns
5
Output Times
C, C high to output valid
tCHQV
C, C high to output hold
tCHQX
C, C high to echo clock valid
tCHCQV
C, C high to echo clock hold
tCHCQX
CQ, CQ high to output valid
tCQHQV
CQ, CQ high to output hold
tCQHQX
0.45
-0.45
0.40
-0.40
0.27
-0.27
0.45
ns
1, 3
ns
1, 3
ns
3
ns
3
ns
1, 3
ns
1, 3
ns
1, 3
ns
1, 3
C high to output high-Z
tCHQZ
C high to output low-Z
tCHQX1
-0.45
Address valid to K, K rising edge
tAVKH
0.35
—
ns
2
Control inputs valid to K rising edge
tIVKH
0.35
—
ns
2
Data-in valid to K, K rising edge
tDVKH
0.35
—
ns
2
K rising edge to address hold
tKHAX
0.35
—
ns
2
K rising edge to control inputs hold
tKHIX
0.35
—
ns
2
K, K rising edge to data-in hold
tKHDX
0.35
—
ns
2
Setup Times
Hold Times
1. See AC Test Loading on page 14
2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
15
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
AC Characteristics (TA = 0 to + 70C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
40
(250MHz)
50
(200MHz)
Units
Min
Max
Min
Max
4.0
7.5
5.0
7.5
ns
0.2
ns
Notes
Clock
Cycle time (K, K, C, C)
tKHKH
Clock phase jitter (K, K, C, C)
tKC-VAR
Clock high pulse (K, K, C, C)
tKHKL
1.6
2.0
ns
Clock low pulse (K, K, C, C)
tKLKH
1.6
2.0
ns
Clock to clock (KH>KH, CH>CH)
tKHKH
1.8
2.2
ns
Clock to data clock (KH>CH, KH>CH)
tKHCH
0.0
tKC-lock
1024
DLL lock (K, C)
Doff Low period to DLL reset
0.2
0.8
0.0
0.8
cycle
1024
5
ns
5
ns
Output Times
C, C high to output valid
tCHQV
C, C high to output hold
tCHQX
C, C high to echo clock valid
tCHCQV
C, C high to echo clock hold
tCHCQX
CQ, CQ High to output valid
tCQHQV
CQ, CQ high to output hold
tCQHQX
0.45
-0.45
0.45
-0.45
0.40
-0.40
0.4
-0.40
0.30
-0.30
0.35
-0.35
0.45
0.45
ns
1, 3
ns
1, 3
ns
3
ns
3
ns
1, 3
ns
1, 3
ns
1, 3
ns
1, 3
C High to output high-Z
tCHQZ
C High to output low-Z
tCHQX1
-0.45
Address valid to K, K rising edge
tAVKH
0.35
—
0.4
—
ns
2
Control inputs valid to K rising edge
tIVKH
0.35
—
0.4
—
ns
2
Data-in valid to K, K rising edge
tDVKH
0.35
—
0.4
—
ns
2
K rising edge to address hold
tKHAX
0.35
—
0.4
—
ns
2
K rising edge to Control Inputs Hold
tKHIX
0.35
—
0.4
—
ns
2
K, K rising edge to data-in hold
tKHDX
0.35
—
0.4
—
ns
2
-0.45
Setup Times
Hold Times
1. See AC Test Loading on page 15.
2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.4. Specs cover -40C to +85C temperature range.
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
ISSI
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
®
Read and Deselect Cycles Timing Diagram
Read
tKHKH
tKHKL
Read
tKLKH
NOP
Read
NOP
K
tKHKH
K
tKHAX
tAVKH
SA
A1
A2
A3
tIVKH tKHIX
R
Q (Data Out)
Q1-1
tKHKH
Q2-1
Q2-2
Q3-1
tCHQV
tKLKH
tKHKL
Q1-2
tCHQX
tCHQX
tCHQZ
C
tKLKH
tCHQV
C
tCHCQV
tCHCQX
tCQHQV
tCQHQX
CQ
tCHCQX
tCHCQV
CQ
Don’t Care
Undefined
Notes: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 (that is, the next internal
burst address following A1+0).
2. Outputs are disabled one cycle after an NOP.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
17
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Write and NOP Timing Diagram
Write
Write
NOP
Write
NOP
tKLKH
tKHKH
tKHKL
K
tKHKH
K
tAVKH
A1
SA
tIVKH
tKHAX
A2
A3
tKHIX
tKHIX
W
tIVKH
tKHIX
BW
tKHDX
tDVKH
D(Data In)
D1-1
D1-2
D2-1
D2-2
D3-1
D3-2
Don’t Care
Undefined
Notes: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1 (that is, the next internal
burst address following A1+0).
2. BWx assumed active.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Read, Write, and NOP Timing Diagram
Read
Write
Read
Write
Read
Write
NOP
Write
NOP
K
K
SA
A1
A2
A3
A4
A5
A6
A7
D2-1
D2-2
D4-1
D4-2
D6-1
D6-2
D7-1
D7-2
Q1-1
Q1-2
Q3-1
Q3-2
W
BWx
R
D(Data In)
Q(Data Out)
Q5-1
Q5-2
C
C
CQ
CQ
Don’t Care
Undefined
Notes: 1. If address A1=A2, data Q1-1=D2-1, data Q1-2=D2-2.
Write data is forwarded immediately as read results.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
19
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and
printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM
core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST
signal is not required.
Signal List
•
•
•
•
TCK: test clock
TMS: test mode select
TDI: test data-in
TDO: test data-out
JTAG DC Operating Characteristics (TA = 0 to +70° C)
Operates with JEDEC Standard 8-5 (1.8V) logic signal levels
Parameter
Symbol
Minimum
Typical
Maximum
Units
Notes
JTAG input high voltage
VIH1
1.3
—
VDD+0.3
V
1
JTAG input low voltage
VIL1
-0.3
—
0.5
V
1
JTAG output high level
VOH1
VDD-0.4
—
VDD
V
1, 2
JTAG output low level
VOL1
VSS
—
0.4
V
1, 3
1.
2.
3.
All JTAG inputs and outputs are LVTTL-compatible.
IOH1 = -2mA
IOL1 = +2mA.
JTAG AC Test Conditions (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Conditions
Units
Input pulse high level
VIH1
1.3
V
Input pulse low level
VIL1
0.5
V
Input rise time
TR1
1.0
ns
Input fall time
TF1
1.0
ns
0.9
V
Input and output timing reference level
20
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
JTAG AC Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum
Maximum
Units
TCK cycle time
tTHTH
20
—
ns
TCK high pulse width
tTHTL
7
—
ns
TCk low pulse width
tTLTH
7
—
ns
TMS setup
tMVTH
4
—
ns
TMS hold
tTHMX
4
—
ns
TDI setup
tDVTH
4
—
ns
TDI hold
tTHDX
4
—
ns
TCK low to valid data
tTLOV
—
7
ns
Notes
1
1. See AC Test Loading on page 14.
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tTHMX
TMS
tMVTH
tTHDX
TDI
tDVTH
TDO
tTLOV
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
21
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Scan Register Definition
Register Name
Bit Size x18 or x36
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
ID Register Definition
Field Bit Number and Description
Part
Revision Number
(31:29)
Part Configuration
(28:12)
JEDEC Code
(11:1)
Start Bit
(0)
4M x 18
000
00def0wx0t0q0b0s0
000 101 001 00
1
2M x 36
000
00def0wx0t0q0b0s0
000 101 001 00
1
Part Configuration Definition:
def = 011 for 72Mb
wx = 11 for x36, 10 for x18
t = 1 for DLL, 0 for non-DLL
q = 1 for QDB2, 0 for DDRII
b = 1 for burst of 4, 0 for burst of 2
s = 1 for separate I/0, 0 for common I/O
22
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
Instruction Set
Code
Instruction
TDO Output
Notes
000
EXTEST
Boundary Scan Register
2,6
001
IDCODE
32-bit Identification Register
010
SAMPLE-Z
Boundary Scan Register
1, 2
011
PRIVATE
Do not use
5
100
SAMPLE
Boundary Scan Register
4
101
PRIVATE
Do not use
5
110
PRIVATE
Do not use
5
111
BYPASS
Bypass Register
3
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the shift-DR state.
4. SAMPLE instruction does not place DQs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6. This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high,
Q will be updated with information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR
state after EXTEST is loaded. The value of the internal register can be changed during SAMPLE and EXTEST only.
List of IEEE 1149.1 Standard Violations
•
•
•
•
•
7.2.1.b, e
7.7.1.a-f
10.1.1.b, e
10.7.1.a-d
6.1.1.d
JTAG Block Diagram
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
TDO
Instruction Register (3 bits)
Control Signals
TMS
TAP Controller
TCK
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
23
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
TAP Controller State Machine
1
Test Logic Reset
0
0
Run Test Idle
1
1
Select DR
0
0
1
1
Select IR
1
Capture IR
Capture DR
0
0
0
Shift IR
0
Shift DR
1
1
1
1
Exit1 IR
Exit1 DR
0
0
0
0
Pause DR
Pause IR
1
1
Exit2 DR
Exit2 IR
0
0
1
1
Update DR
0
24
1
Update IR
1
0
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
Order
Pin ID
Order
Pin ID
Order
Pin ID
1
6R
37
10D
73
2C
2
6P
37
9E
74
3E
3
6N
39
10C
75
2D
4
7P
40
11D
76
2E
5
7N
41
9C
77
1E
6
7R
42
9D
78
2F
7
8R
43
11B
79
3F
8
8P
44
11C
80
1G
9
9R
45
9B
81
1F
10
11P
46
10B
82
3G
11
10P
47
11A
83
2G
12
10N
48
10A
84
1H
13
9P
49
9A
85
1J
14
10M
50
8B
86
2J
15
11N
51
7C
87
3K
16
9M
52
6C
88
3J
17
9N
53
8A
89
2K
18
11L
54
7A
90
1K
19
11M
55
7B
91
2L
20
9L
56
6B
92
3L
21
10L
57
6A
93
1M
22
11K
58
5B
94
1L
23
10K
59
5A
95
3N
24
9J
60
4A
96
3M
25
9K
61
5C
97
1N
26
10J
62
4B
98
2M
27
11J
63
3A
99
3P
28
11H
64
2A
100
2N
29
10G
65
1A
101
2P
30
9G
66
2B
102
1P
31
11F
67
3B
103
3R
32
11G
68
1C
104
4R
33
9F
69
1B
105
4P
34
10F
70
3D
106
5P
35
11E
71
3C
107
5N
36
10E
72
1D
108
5R
109
Internal
®
Note:
1) NC pins as defined on FBGA pinouts on page 2 are read as “don’t cares”.
2) State of Internal pin (#109) is loaded via JTAG
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
05/14/09
25
372 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ISSI
®
NOTE :
1. Controlling dimension : mm
Package Outline
12/10/2007
26
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
05/14/09
72 Mb (2M x 36 & 4M x 18)
QUAD (Burst of 2) Synchronous SRAMs
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
300 MHz
250 MHz
200 MHz
Order Part No.
IS61QDB22M36-300M3
IS61QDB22M36-300M3L
IS61QDB24M18-300M3
IS61QDB24M18-300M3L
IS61QDB22M36-250M3
IS61QDB22M36-250M3L
IS61QDB24M18-250M3
IS61QDB24M18-250M3L
IS61QDB22M36-200M3L
IS61QDB24M18-200M3L
Integrated Silicon Solution, Inc.
Rev. 05/14/09
Organization
2Mx36
2Mx36
4Mx18
4Mx18
2Mx36
2Mx36
4Mx18
4Mx18
2Mx36
4Mx18
Package
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
165 BGA
165 BGA, Lead-free
165 BGA, Lead-free
165 BGA, Lead-free
27