IS61LF102436A IS61VF102436A IS61LF204818A IS61VF204818A 1M x 36, 2M x 18 36Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VF: Vdd 2.5V + 5%, Vddq 2.5V + 5% • JEDEC 100-Pin TQFP and 165-pin PBGA packages. • Lead-free available APRIL 2008 DESCRIPTION The ISSI IS61LF/VF102436A and IS61LF/VF204818A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LF/ VF102436A is organized as 1,048,476 words by 36 bits. The IS61LF/VF204818A is organized as 2M-words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency -6.5 6.5 7.5 133 -7.5 7.5 8.5 117 Units ns ns MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. Rev. B 04/17/08 1 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A BLOCK DIAGRAM MODE Q0 CLK CLK A0 BINARY COUNTER ADSC ADSP A Q1 CE ADV A1 A0' A1' 1Mx36; 2Mx18; MEMORY ARRAY CLR 20/21 D Q 18/19 20/21 ADDRESS REGISTER CE CLK 36, or 18 D GW BWE BW(a-d) x18: a,b x36: a-d 36, or 18 Q DQ(a-d) BYTE WRITE REGISTERS CLK CE 2/4/8 Q CE2 D CE2 ENABLE REGISTER INPUT REGISTERS CLK 36, or 18 DQa - DQd OE CE CLK ZZ POWER DOWN OE 2 Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A 165-pin BGA 165-Ball, 13x15 mm BGA Bottom view Integrated Silicon Solution, Inc. Rev. B 04/17/08 3 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A 165 PBGA PACKAGE PIN CONFIGURATION 1M x 36 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 BWE ADSC ADV A NC B NC A CE2 BWd BWa CLK GW OE ADSP A NC C DQPc NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPb D DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb E DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb F DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb G DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb H NC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQd DQd Vddq Vdd Vss Vss Vss Vdd VddqDQaDQa K DQd DQd Vddq Vdd Vss Vss Vss Vdd VddqDQaDQa L DQd DQd Vddq Vdd Vss Vss Vss Vdd VddqDQaDQa M DQd DQd Vddq Vdd Vss Vss Vss Vdd VddqDQaDQa N DQPd NC Vddq Vss NC A NC Vss Vddq NC DQPa P NC NC A A NC A1* NC A A A A R MODE A A A NC A0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. (Under Evaluation) PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance. Address Status Processor OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select NC DQa-DQd DQPa-Pd Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply Vss Ground BWx (x=a,b,c,d) Synchronous Byte Write Controls 4 Output Power Supply Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A 165 PBGA PACKAGE PIN CONFIGURATION 2M x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWb NC CE2 BWE ADSC ADV A A B NC A CE2 NC BWa CLK GW OE ADSP A NC C NC NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPa D NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa E NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa F NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa G NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa H NC NC NC Vdd Vss Vss Vss Vdd NC J DQb NC Vddq Vdd Vss Vss Vss Vdd VddqDQa NC K DQb NC Vddq Vdd Vss Vss Vss Vdd VddqDQa NC L DQb NC Vddq Vdd Vss Vss Vss Vdd VddqDQa NC M DQb NC Vddq Vdd Vss Vss Vss Vdd VddqDQa NC NC ZZ N DQPb NC Vddq Vss NC A NC Vss Vddq NC NC P NC NC A A NC A1* NC A A A A R MODE A A A NC A0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. (Under Evaluation) PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol BWE Byte Write Enable A0, A1 ADV ADSP Synchronous Burst Address Inputs Synchronous Burst Address Advance. Address Status Processor OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select NC DQa-DQd DQPa-Pd Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs Power Supply BWx (x=a,b) Synchronous Byte Write Controls Vss Ground Integrated Silicon Solution, Inc. Rev. B 04/17/08 Pin Name Output Power Supply 5 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A PIN CONFIGURATION A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP DQPc DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1M x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQd Synchronous Data Input/Output 6 DQPa-DQPd Vss GW MODE OE Vdd Vddq ZZ Parity Data Input/Output Ground Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Snooze Enable Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A PIN CONFIGURATION A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC A VSS VDD A A A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC 2M x 18 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs Synchronous Controller Address Status ADSC ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output Integrated Silicon Solution, Inc. Rev. B 04/17/08 DQPa-DQPb Vss GW MODE OE Vdd Vddq ZZ Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 Ground Synchronous Global Write Enable Burst Sequence Mode Selection Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Snooze Enable 7 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A TRUTH TABLE(1-8) (3CE option) OPERATION Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Deselect Cycle, Power-Down Snooze Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS CE None H None L None L None L None L None X External L External L External L External L External L Next X Next X Next H Next H Next X Next H Current X Current X Current H Current H Current X Current H CE2 X X H X H X L L L L L X X X X X X X X X X X X CE2 X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP ADSC ADV WRITE OE X L X X X L X X X X L X X X X H L X X X H L X X X X X X X X L X X X L L X X X H H L X L X H L X H L H L X H H H H L H L H H L H H X H L H L X H L H H H H L L X X H L L X H H H H L H H H H H X H H H L X H H H H H H H L X X H H L X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s and DQPf. BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are available on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. 8 Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Vdd Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Voltage on Vdd Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to Vddq + 0.5 V –0.5 to Vdd + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. Rev. B 04/17/08 9 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A OPERATING RANGE (IS61LFxxxxx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 3.3V ± 5% 3.3V ± 5% Vddq 3.3V/2.5V ± 5% 3.3V/2.5V ± 5% Vdd 2.5V ± 5% 2.5V ± 5% Vddq 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61VFxxxxx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Voh Output HIGH Voltage Vol Output LOW Voltage Vih Input HIGH Voltage Vil Input LOW Voltage Ili Input Leakage Current Ilo Output Leakage Current 3.3V Test Conditions Min. Ioh = –4.0 mA (3.3V) 2.4 Ioh = –1.0 mA (2.5V) Iol = 8.0 mA (3.3V) — Iol = 1.0 mA (2.5V) 2.0 –0.3 Vss ≤ Vin ≤ Vdd(1) –5 Vss ≤ Vout ≤ Vddq, OE = Vih –5 2.5V Max. — Min. 2.0 Max. — Unit V 0.4 — 0.4 V Vdd + 0.3 0.8 5 5 1.7 –0.3 –5 –5 Vdd + 0.3 0.7 5 5 V V µA µA 7.5 MAX x18 x36 340 340 350 350 295 Note: 1. Vil (min.) = –2.0V AC (pulse width 2.0 ns). Not 100% tested. Vih (max.) = Vdd + 2.0V AC (pulse width 2.0 ns). Not 100% tested. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Test Conditions Temp. range Device Selected, Com. OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, typ.(2) Cycle Time ≥ tkc min. Device Deselected, Com. Vdd = Max., Ind. All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Device Deselected, Com. Vdd = Max., Ind. Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V typ.(2) f=0 6.5 MAX x18 x36 360 360 375 375 295 155 160 Unit mA 155 160 155 160 155 160 mA 140 140 145 145 80 140 145 140 145 mA 80 Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested. 10 Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT 50Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. Rev. B 04/17/08 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 11 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 12 Figure 4 Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toelz(2,3) toehz(2,3) tas tws tces tavs tds tah twh tceh tavh tdh tpds tpus Notes: Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down 6.5 Min. Max. — 133 7.5 — 2.2 — 2.2 — — 6.5 2.5 — 2.5 — — 3.8 — 3.2 0 — — 3.5 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — 2 — 2 7.5 Min. Max. — 117 8.5 — 2.5 — 2.5 — — 7.5 2.5 — 2.5 — — 4.0 — 3.4 0 — — 3.5 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — 2 — 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. Rev. B 04/17/08 13 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS Address tAH RD1 WR1 tWS tWH tWS tWH RD2 RD3 GW BWE tWS tWH WR1 BWd-BWa tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2 and CE2 only sampled with ADSP or ADSC CE2 Unselected with CE2 CE2 tOEHZ OE tKQX tOEQX DATAOUT High-Z tKQX tKQ DATAIN High-Z tKQLZ tKQ 1a tKQLZ 2b 2c 2d tKQHZ tKQHZ 1a High-Z tDS Single Read Flow-through 14 2a tDH Single Write Burst Read Unselected Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS Address tAH WR1 WR2 tWS tWH tWS tWH tWS tWH WR3 GW BWE BWd-BWa WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE1 Masks ADSP CE Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z tDH 1a Single Write Integrated Silicon Solution, Inc. Rev. B 04/17/08 BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected 15 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions ZZ ≥ Vih Min. typ. (1) Max. — 27 Unit Isb2 Current during SNOOZE MODE 90 mA tpds ZZ active to input ignored — 2 cycle tpus ZZ inactive to input sampled 2 — cycle tzzi ZZ active to SNOOZE current — 2 cycle trzzi ZZ inactive to exit SNOOZE current 0 — ns 1. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested. SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care 16 Integrated Silicon Solution, Inc. Rev. B 04/17/08 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Configuration 1Mx36 2Mx18 Access Time 6.5 6.5 Order Part Number IS61LF102436A-6.5TQL IS61LF102436A-6.5B3 IS61LF204818A-6.5TQ IS61LF204818A-6.5TQL IS61LF204818A-6.5B3 Package 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Order Part Number IS61LF102436A-6.5TQLI IS61LF102436A-6.5B3I IS61LF102436A-7.5TQI IS61LF102436A-7.5TQLI IS61LF102436A-7.5B3I IS61LF102436A-7.5B3LI IS61LF204818A-6.5TQI IS61LF204818A-6.5B3I IS61LF204818A-7.5TQI IS61LF204818A-7.5TQLI IS61LF204818A-7.5B3I Package 100 TQFP, Lead-free 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 165 PBGA, Lead-free 100 TQFP 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA Industrial Range: -40°C to +85°C Configuration 1Mx36 1Mx36 2Mx18 2Mx18 Access Time 6.5 7.5 6.5 7.5 Integrated Silicon Solution, Inc. Rev. B 04/17/08 17 IS61LF102436A IS61LF204818A IS61VF102436A IS61VF204818A ORDERING INFORMATION (Vdd = 2.5V /Vddq = 2.5V) Commercial Range: 0°C to +70°C Configuration 1Mx36 1Mx36 2Mx18 2Mx18 Access Time 6.5 7.5 6.5 7.5 Order Part Number IS61VF102436A-6.5TQ IS61VF102436A-6.5B3 IS61VF102436A-7.5TQ IS61VF102436A-7.5B3 IS61VF204818A-6.5TQ IS61VF204818A-6.5B3 IS61VF204818A-7.5TQ IS61VF204818A-7.5B3 Package 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA Order Part Number IS61VF102436A-6.5TQI IS61VF102436A-6.5B3I IS61VF102436A-7.5TQI IS61VF102436A-7.5TQLI IS61VF102436A-7.5B3I IS61VF204818A-6.5TQI IS61VF204818A-6.5B3I IS61VF204818A-7.5TQI IS61VF204818A-7.5B3I Package 100 TQFP 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA Industrial Range: -40°C to +85°C Configuration 1Mx36 1Mx36 2Mx18 2Mx18 18 Access Time 6.5 7.5 6.5 7.5 Integrated Silicon Solution, Inc. Rev. B 04/17/08 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Millimeters Min Max Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Symbol Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 A1 CORNER φ b (165X) 5 6 7 8 9 10 11 10 11 9 8 7 6 5 4 3 2 1 A A B B C C D D E E e F F G G D D1 H H J J K K L L M M N N P P R R E1 E A2 e A A1 BGA - 13mm x 15mm MILLIMETERS Sym. Min. N0. Leads Nom. Max. Notes: 1. Controlling dimensions are in millimeters. INCHES Min. 165 Nom. Max. 165 A — — 1.20 — A1 0.25 0.33 0.40 0.010 — 0.047 0.013 0.016 A2 — 0.79 — — 0.031 — D 14.90 15.00 15.10 0.587 0.591 0.594 D1 13.90 14.00 14.10 0.547 0.551 0.555 E 12.90 13.00 13.10 0.508 0.512 0.516 E1 9.90 10.00 10.10 0.390 0.394 0.398 e — 1.00 — — 0.039 — b 0.40 0.45 0.50 0.016 0.018 0.020 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03