IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A DECEMBER 2013 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% • JEDEC 100-Pin QFP, 119-ball and 165-ball BGA packages • Automotive temperature available • Lead Free available DESCRIPTION The ISSI IS61(64)LPS12832A, IS61(64)LPS/VP- S12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.The IS61(64)LPS12832A is organized as 131,072 words by 32 bits.The IS61(64)LPS/ VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/VPS25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency 250 2.6 4 250 200 3.1 5 200 Units ns ns MHz Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A BLOCK DIAGRAM MODE Q0 CLK CLK A0 BINARY COUNTER ADSC ADSP A Q1 CE ADV A1 A0' A1' 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY CLR 17/18 D Q 15/16 17/18 ADDRESS REGISTER CE CLK 32, 36, or 18 D GW BWE BW(a-d) x18: a,b x32/x36: a-d 32, 36, or 18 Q DQ(a-d) BYTE WRITE REGISTERS CLK CE 2/4/8 Q CE2 D CE2 ENABLE REGISTER INPUT REGISTERS CLK OUTPUT REGISTERS CLK 32, 36, or 18 DQa - DQd OE CE CLK D ZZ POWER DOWN Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 165-pin BGA 119-pin BGA 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array 119-Ball, 14x22 mm BGA 1mm Ball Pitch, 7x17 Ball Array Bottom view Bottom View Integrated Silicon Solution, Inc. 3 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 119 BGA PACKAGE PIN CONFIGURATION 128K x 36 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A CE2 NC C NC A A VDD A A NC D DQc DQPc Vss NC Vss DQPb E DQc DQc Vss CE Vss DQb DQb F VDDQ DQc Vss OE Vss DQb VDDQ G DQc DQc BWc ADV BWb DQb DQb H DQc DQc Vss GW Vss DQb DQb J VDDQ VDD NC VDD NC VDD VDDQ K DQd DQd Vss CLK Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd Vss BWE Vss DQa VDDQ N DQd DQd Vss A1* Vss DQa DQa P DQd DQPd Vss A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ DQb Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC GW Address Status Controller Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Controls BWE Byte Write Enable 4 Symbol OE Pin Name Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Output Power Supply Vdd Power Supply Vddq Output Power Supply Vss Ground Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 119 BGA PACKAGE PIN CONFIGURATION 256Kx18 (TOP VIEW) 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A CE2 NC C NC A A VDD A A NC D DQb NC Vss NC Vss DQPa NC E NC DQb Vss CE Vss NC DQa Vss OE Vss DQa VDDQ NC DQa F VDDQ NC G NC DQb BWb ADV Vss H DQb NC Vss GW Vss DQa NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQb Vss CLK Vss NC DQa L DQb NC Vss NC BWa DQa NC M VDDQ DQb Vss BWE Vss NC VDDQ N DQb NC Vss A1* Vss DQa NC P NC DQPb Vss A0* Vss NC DQa R NC A MODE VDD NC A NC T NC A A NC A A ZZ U VDDQ NC NC NC NC NC VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 Synchronous Burst Address Inputs ZZ Power Sleep Mode MODE Burst Sequence Selection NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Output Power Supply Vdd Power Supply Vddq Output Power Supply Vss Ground ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls BWE Byte Write Enable Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 5 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 165 BGA PACKAGE PIN CONFIGURATION 128K x 36 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 BWc BWb CE2 BWE ADSC ADV A NC NC A NC A CE B NC A CE2 BWd BWa CLK GW OE ADSP A C DQPc NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPb D DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb E DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb F DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb G DQc DQc Vddq Vdd Vss Vss Vss Vdd Vddq DQb DQb H NC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa K DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa L DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa M DQd DQd Vddq Vdd Vss Vss Vss Vdd Vddq DQa DQa N DQPd NC Vddq Vss NC NC NC Vss Vddq NC DQPa P NC NC A A NC A1* NC A A A NC R MODE NC A A NC A0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 Synchronous Burst Address Inputs OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC DQx DQPx Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Vss Ground ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b,c,d) Synchronous Byte Write Controls 6 Isolated Output Power Supply 3.3V/2.5V Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 165 BGA PACKAGE PIN CONFIGURATION 256K x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWb NC CE2 BWE ADSC ADV A A B NC A CE2 NC BWa CLK GW OE ADSP A NC C NC NC Vddq Vss Vss Vss Vss Vss Vddq NC DQPa D NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa E NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa F NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa G NC DQb Vddq Vdd Vss Vss Vss Vdd Vddq NC DQa H NC NC NC Vdd Vss Vss Vss Vdd NC NC ZZ J DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC K DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC L DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC M DQb NC Vddq Vdd Vss Vss Vss Vdd Vddq DQa NC N DQPb NC Vddq Vss NC NC NC Vss Vddq NC NC P NC NC A A NC A1* NC A A A NC R MODE NC A A NC A0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance ADSP Address Status Processor ADSC GW Address Status Controller Global Write Enable CLK CE, CE2, CE2 Synchronous Clock Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Controls Pin Name BWE Byte Write Enable OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection NC DQx DQPx Vdd Vddq No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Isolated Output Power Supply 3.3V/2.5V Vss Ground Integrated Silicon Solution, Inc. 7 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A PIN CONFIGURATION 100-Pin QFP (128K x 32) DQPc DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (128K x 36) (3 Chip-Enable option) (3 Chip-Enable option) PIN DESCRIPTIONS A0, A1 A Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK 8 DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Output Enable Vdd 3.3V/2.5V Power Supply Vddq Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable Vss ZZ Synchronous Clock Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A PIN CONFIGURATION A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-Pin QFP (256K x 18) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC (3 Chip-Enable Option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs Synchronous Controller Address Status ADSC ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 GW MODE Synchronous Global Write Enable Burst Sequence Mode Selection OE Vdd Vddq Vss ZZ Output Enable 3.3V/2.5V Power Supply Isolated Output Buffer Supply: 3.3V/2.5V Ground Snooze Enable 9 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A TRUTH TABLE(1-8) OPERATIONADDRESS CE CE2 CE2ZZADSP ADSC ADV Deselect Cycle, Power-Down None H X X L X L X Deselect Cycle, Power-Down None L X L L L X X Deselect Cycle, Power-Down None L H X L L X X Deselect Cycle, Power-Down None L X L L H L X Deselect Cycle, Power-Down None L H X L H L X Snooze Mode, Power-Down None X X X H X X X Read Cycle, Begin Burst External L L H L L X X Read Cycle, Begin Burst External L L H L L X X Write Cycle, Begin Burst External L L H L H L X Read Cycle, Begin Burst External L L H L H L X Read Cycle, Begin Burst External L L H L H L X Read Cycle, Continue Burst Next X X X L H H L Read Cycle, Continue Burst Next X X X L H H L Read Cycle, Continue Burst Next H X X L X H L Read Cycle, Continue Burst Next H X X L X H L Write Cycle, Continue Burst Next X X X L H H L Write Cycle, Continue Burst Next H X X L X H L Read Cycle, Suspend Burst Current X X X L H H H Read Cycle, Suspend Burst Current X X X L H H H Read Cycle, Suspend Burst Current H X X L X H H Read Cycle, Suspend Burst Current H X X L X H H Write Cycle, Suspend Burst Current X X X L H H H Write Cycle, Suspend Burst Current H X X L X H H WRITE OECLK DQ X X L-H High-Z X X L-H High-Z X X L-H High-Z X X L-H High-Z X X L-H High-Z X X X High-Z X L L-H Q X H L-H High-Z L X L-H D H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z L X L-H D L X L-H D H L L-H Q H H L-H High-Z H L L-H Q H H L-H High-Z L X L-H D L X L-H D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes 10 GW BWEBWaBWbBWcBWd HHXXXX HLHHHH H L L H H H H L L L L L L X X X X X Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or No Connect) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00011011 01001110 10110001 11100100 LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) SymbolParameter Tstg Storage Temperature Pd Power Dissipation Iout Output Current (per I/O) Vin, Vout Voltage Relative to Vss for I/O Pins Vin Voltage Relative to Vss for for Address and Control Inputs Vdd Voltage on Vdd Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to Vddq + 0.5 V –0.5 to Vdd + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. 11 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A OPERATING RANGE (IS61/64LPSXXXXX) Range Commercial Ambient Temperature 0°C to +70°C VddVddq 3.3V + 5% 3.3V / 2.5V + 5% Industrial –40°C to +85°C 3.3V + 5% 3.3V / 2.5V + 5% Automotive –40°C to +125°C 3.3V + 5% 3.3V / 2.5V + 5% OPERATING RANGE (IS61/64VPSXXXXX) Range Commercial Ambient Temperature 0°C to +70°C VddVddq 2.5V + 5% 2.5V + 5% Industrial –40°C to +85°C 2.5V + 5% 2.5V + 5% Automotive –40°C to +125°C 2.5V + 5% 2.5V + 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Voh Output HIGH Voltage Ioh = –4.0 mA (3.3V) Ioh = –1.0 mA (2.5V) Vol Output LOW Voltage Iol = 8.0 mA (3.3V) Iol = 1.0 mA (2.5V) Vih Input HIGH Voltage Vil Input LOW Voltage Ili Input Leakage Current Vss ≤ Vin ≤ Vdd(1) Ilo Output Leakage Current Vss ≤ Vout ≤ Vddq, OE = Vih 12 3.3V Min. Max. 2.4 — — 2.5V Min. Max. 2.0 — 0.4 — 2.0 Vdd + 0.3 -0.3 0.8 -5 5 -5 5 0.4 1.7 Vdd + 0.3 -0.30.7 -5 5 -5 5 Unit V V V V µA µA Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Test Conditions Device Selected, OE = Vih, ZZ ≤ Vil, All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, Cycle Time ≥ tkc min. Device Deselected, Vdd = Max., All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Device Deselected, Vdd = Max., Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V f=0 Temp. range Com. Ind. Auto. -250-200 MAXMAX x18 x32/x36 x18 x32/x36 Unit 225 225 200 200 mA 250 250 210 210 275 275 225 225 Com. Ind. Auto. 90 90 90 90 100 100 100 100 120120 120120 Com. Ind. Auto. typ.(2) 70 75 90 70 75 90 40 70 75 90 40 mA 70 mA 75 90 Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. Integrated Silicon Solution, Inc. 13 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω Output 50Ω 1.5V Figure 1 14 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5 I/O OUTPUT LOAD EQUIVALENT 1,667 Ω 2.5V ZO = 50Ω Output 50Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 OUTPUT 5 pF Including jig and scope 1,538 Ω Figure 4 15 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) SymbolParameter fmax Clock Frequency tkc Cycle Time tkh Clock High Time tkl Clock Low Time tkq Clock Access Time tkqx(2) Clock High to Output Invalid tkqlz(2,3) Clock High to Output Low-Z tkqhz(2,3) Clock High to Output High-Z toeq Output Enable to Output Valid toeqx(2) Output Disable to Output Invalid toelz(2,3) Output Enable to Output Low-Z toehz Output Disable to Output High-Z tas Address Setup Time tss Address Status Setup Time tws Read/Write Setup Time tces Chip Enable Setup Time tavs Address Advance Setup Time tds Data Setup Time tah Address Hold Time tsh Address Status Hold Time twh Write Hold Time tceh Chip Enable Hold Time tavh Address Advance Hold Time tdh Data Hold Time (2,3) -250 Min. Max. — 250 4.0 — 1.7 — 1.7 — — 2.6 0.8 — 0.8 — — 2.6 — 2.8 0 — 0 — 1.2 1.2 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0.3 — 2.6 — — — — — — — — — — — — -200 Min. — 5 2 2 — 1.5 1 — — 0 Max. 200 — — — 3.1 — — 3.0 3.1 — Unit MHz ns ns ns ns ns ns ns ns ns 0 — 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 — 3.0 — — — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 16 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst ADV tAS Address tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BWx tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c tKQLZ 2d tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected Integrated Silicon Solution, Inc. 17 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS Address tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE WR1 BWx tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write 18 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Isb2 Current during SNOOZE MODE tpds ZZ active to input ignored tpus ZZ inactive to input sampled tzzi ZZ active to SNOOZE current trzzi ZZ inactive to exit SNOOZE current Conditions ZZ ≥ Vih Min. — 2 2 — 0 Max. 60 — — 2 — Unit mA cycle cycle cycle ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 19 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Commercial Range: 0°C to +70°C Configuration 128Kx32 Frequency Order Part Number Package 250 200 IS61LPS12832A-250TQ IS61LPS12832A-250B2 IS61LPS12832A-250B3 IS61LPS12832A-200TQ IS61LPS12832A-200B2 IS61LPS12832A-200B3 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 250 200 IS61LPS12836A-250TQ IS61LPS12836A-250TQL IS61LPS12836A-250B2 IS61LPS12836A-250B3 IS61LPS12836A-200TQ IS61LPS12836A-200B2 IS61LPS12836A-200B3 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 250 200 IS61LPS25618A-250TQ IS61LPS25618A-250B2 IS61LPS25618A-250B3 IS61LPS25618A-200TQ IS61LPS25618A-200B2 IS61LPS25618A-200B3 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 128Kx36 256Kx18 20 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ORDERING INFORMATION (3.3V core/2.5V-3.3V I/O) Industrial Range: -40°C to +85°C Configuration 128Kx32 Frequency Order Part Number Package 250 200 IS61LPS12832A-250TQI IS61LPS12832A-250B2I IS61LPS12832A-250B3I IS61LPS12832A-200TQI IS61LPS12832A-200TQLI IS61LPS12832A-200B2I IS61LPS12832A-200B3I 100 QFP 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA 250 200 IS61LPS12836A-250TQI IS61LPS12836A-250B2I IS61LPS12836A-250B3I IS61LPS12836A-200TQI IS61LPS12836A-200TQLI IS61LPS12836A-200B2I IS61LPS12836A-200B2LI IS61LPS12836A-200B3I 100 QFP 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 119 BGA, Lead-free 165 BGA 250 200 IS61LPS25618A-250TQI IS61LPS25618A-250B2I IS61LPS25618A-250B3I IS61LPS25618A-200TQI IS61LPS25618A-200TQLI IS61LPS25618A-200B2I IS61LPS25618A-200B3I 100 QFP 119 BGA 165 BGA 100 QFP 100 QFP, Lead-free 119 BGA 165 BGA Order Part Number Package 200 IS64LPS12832A-200TQA3 IS64LPS12832A-200TQLA3 100 QFP 100 QFP, Lead-free 200 IS64LPS12836A-200TQA3 100 QFP 200 IS64LPS25618A-200TQA3 IS64LPS25618A-200TQLA3 100 QFP 100 QFP, Lead-free 128Kx36 256Kx18 Automotive Range: -40°C to +125°C Configuration 128Kx32 Frequency 128Kx36 256Kx18 Integrated Silicon Solution, Inc. 21 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A ORDERING INFORMATION (2.5V core/2.5V I/O) Commercial Range: 0°C to +70°C Configuration 128Kx36 Frequency Order Part Number Package 250 200 IS61VPS12836A-250TQ IS61VPS12836A-250B2 IS61VPS12836A-250B3 IS61VPS12836A-200TQ IS61VPS12836A-200B2 IS61VPS12836A-200B3 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 250 200 IS61VPS25618A-250TQ IS61VPS25618A-250B2 IS61VPS25618A-250B3 IS61VPS25618A-200TQ IS61VPS25618A-200B2 IS61VPS25618A-200B3 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 256Kx18 22 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A Industrial Range: -40°C to +85°C Configuration 128Kx36 Frequency Order Part Number Package 250 200 IS61VPS12836A-250TQI IS61VPS12836A-250B2I IS61VPS12836A-250B3I IS61VPS12836A-200TQI IS61VPS12836A-200B2I IS61VPS12836A-200B3I 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 250 200 IS61VPS25618A-250TQI IS61VPS25618A-250B2I IS61VPS25618A-250B3I IS61VPS25618A-200TQI IS61VPS25618A-200B2I IS61VPS25618A-200B3I 100 QFP 119 BGA 165 BGA 100 QFP 119 BGA 165 BGA 256Kx18 Automotive Range: -40°C to +125°C Configuration 128Kx32 Frequency Order Part Number Package 200 IS64VPS12832A-200TQA3 100 QFP 200 IS64VPS12836A-200TQA3 100 QFP 200 IS64VPS25618A-200TQA3 100 QFP 128Kx36 256Kx18 Integrated Silicon Solution, Inc. 23 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 24 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MS-028 NOTE : Package Outline 10/02/2008 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 25 26 Package Outline 1. CONTROLLING DIMENSION : MM . NOTE : 08/28/2008 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A Integrated Silicon Solution, Inc. Rev. H1 12/06/2013