MURATA-PS ADCDS

ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
For full details go to
www.murata-ps.com/rohs
FEATURES
PRODUCT OVERVIEW
2.3 MPPS
The ADCDS-1603 is an application-specific CCD
signal processor designed for electronic-imaging
applications that employ CCD's (charge coupled
devices) as their photodetector. The ADCDS-1603
incorporates a "user configurable" input amplifier,
a CDS (correlated double sampler) and a 16-bit
resolution sampling A/D converter in a single
package, providing the user with a complete, high
performance, low-cost, low-power, integrated
solution.
Internal 16-bit resolution A/D
Internal correlated doubler sampler (CDS)
Resistor programmable gain adjustment
from 0dB to 15.5dB
1.3 LSB RMS Noise
Small, 40-pin, TDIP or SMT package
Analog front end programmable bandwidth
Extended temperature range –40ºC to +125ºC
Low power, 674mW
Low cost, functionally complete
The key to the ADCDS-1603's performance is a
unique, high-speed, high-accuracy CDS circuit,
which eliminates the effects of residual charge,
charge injection and "kT/C" noise on the CCD's
output floating capacitor, producing a pixel data
output signal. The ADCDS-1603 digitizes this
resultant pixel data signal using a high-speed,
low-noise sampling A/D converter.
The ADCDS-1603 requires only the rising edge
of start convert pulse to initiate its conversion
process and a Reference Hold command to
acquire and hold the CCD reference level output.
Additional features of the ADCDS-1603 include
gain adjust, offset adjust, precision +2.048V
reference, and a programmable analog bandwidth
function.
FUNCTIONAL BLOCK DIAGRAM
+5VA
–5VA
38
+5V D
36
34
499
INVERTING INPUT 4
100
INPUT AMPLIFIER
0.01μF
DIRECT INPUT 3
23 BIT 1 (MSB)
NON-INVERTING INPUT 5
5K 7
22pf
CORRELATED
DOUBLE
SAMPLER
SAMPLING
A/D
8
BIT 16 (LSB)
6
+2.048V REFERENCE OUTPUT
OFFSET ADJUST 2
REFERENCE HOLD 26
START CONVERT 25
32, 33
DIGITAL GROUND
TIMING
AND
CONTROL
27
DATA VALID
30 31
AØ A1
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7, 35, 37
ANALOG GROUND
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MDA_ADCDS-1603.E06 Page 1 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
ABSOLUTE MAXIMUM RATINGS
Parameters
Min.
Typ.
Max.
Units
–5V Supply (Pin 38)
–6.5
–
+0.3
Volts
+5V Supply (Pin 34, 36)
–0.3
–
+6.5
Volts
Digital Input (Pin 25, 26, 30, 31)
–0.3
–
Vdd+0.3V
Volts
Analog Input (Pin 3, 4, 5)
–6
–
+6
Volts
Lead Temperature
–
–
300
°C
Noise
A1
A0
DC Noise Gain = 1 (pin 4 = NC) ~
Start Convert Rate
2.3 MHz
LO
LO
2
63
LSB RMS
uV RMS
1.8 MHz
LO
HI
1.5
48
LSB RMS
uV RMS
1.0 MHz
HI
LO
1.3
41
LSB RMS
uV RMS
800 MHz
HI
HI
1.3
41
LSB RMS
uV RMS
DC Noise Gain = 5.99 (pin 4 = GND) ~
Start Convert Rate
2.3 MHz
LO
LO
2.5
13
LSB RMS
uV RMS
1.8 MHz
LO
HI
2.0
10.8
LSB RMS
uV RMS
1.0 MHz
HI
LO
1.6
8.5
LSB RMS
uV RMS
800 MHz
HI
HI
1.6
8.5
LSB RMS
uV RMS
FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range, under the following
conditions: +5VA = +5V, +5VD = 5V, –5VA = –5V, sample rate = 2.3MHz.
Analog Input
Min.
Typ.
Max.
Units
Input Voltage Range (Reference
Signal - Pixel data Signal)
Gain of 5.99 (Pin 4 to GND)
Gain of 1 (Pin 4 Open)
–
–
–
–
0.342
2.048
V p-p
V p-p
Input Resistance
–
5000
–
Ohms
Input Capacitance
–
22
–
pF
Digital Inputs
Logic Levels
Logic 1 A0, A1 (pins 30, 31)
Logic 0 A0, A1 (pins 30, 31)
Logic 1 (pins 25, 26)
Logic 0 (pins 26, 26)
Logic Loading
Logic 1
Logic 0
4.5
–
+2.4
–
–
–
–
–
+Vdd
0.4
–
+0.8
Volts
Volts
Volts
Volts
–
–
–
–
+10
-10
uA
uA
Logic Levels (pins 8-23)
Logic 1 (0.5mA)
Logic 0 (0.5mA)
2.8
–
3.0
–
3.3
+0.4
Volts
Volts
Logic Levels (pin 27)
Logic 1 (0.5mA)
Logic 0 (0.5mA)
4.5
–
5.0
–
+0.4
Volts
Volts
2.038
2.038
2.028
2.048
2.048
2.048
2.058
2.058
2.068
Volts
Volts
Volts
Reference
Min.
Reference Voltage +25ºC
2.033
0.2
mA
Reference Voltage 0 to +70ºC
2.033
Reference Voltage -40 to +125ºC
2.033
Digital Outputs
Internal Reference Voltage
(Fine gain adjust pin 1 grounded)
+25°C
0 to 70°C
–40 to +125°C
Reference Current
–
Linearity
Differential Nonlinearity
(Histogram, 98kHz)
+25°C
0 to 70°C
–40 to +125°C
–0.90
–0.90
–0.98
±0.5
±0.5
±0.6
+1.2
+1.2
+2
LSB
LSB
LSB
Integral Nonlinearity
+25°C
0 to 70°C
–40 to +125°C
–
–
–
±1
±1
±2
–
–
–
LSB
LSB
LSB
Guaranteed No Missing Codes
0 to 70°C
–40 to +125°C
16
16
–
–
–
–
LSB
LSB
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Offset/Gain
Min.
Typ.
Max.
Units
Min.
Typ.
Max.
Units
Offset Error Gain = 1
+25°C
0 to 70°C
–40 to +125°C
–
–
–
0.5
0.5
0.5
1
1
1.5
%FSR
%FSR
%FSR
Gain Error Gain = 1
+25°C
0 to 70°C
–40 to +125°C
–
–
–
0.5
0.5
0.5
1
1
1.5
%FSR
%FSR
%FSR
Bandwidth
Min.
Typ.
Max.
Units
Input Amplifier –3db BW ‚
Input Common Mode Voltage
Output Voltage Swing
13.5
–3.5
–2.5
–
–
–
–
3.5
2.5
MHz
V
V
Typ.
Max.
Units
2.048
2.063
V
2.048
2.063
V
2.048
2.063
V
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MDA_ADCDS-1603.E06 Page 2 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
3. Offset adjustment resistor (Figure 3), Rext (Figure 2b, 2c, & 2f),
and Rext1 & Rext2 (Figure 2d) should be placed as close to the
ADCDS-1603 as possible.
Signal Timing 
0.001
–
2.3€
MHz
Conversion Time
434
–
–
nSec
Start Convert Pulse Width
20
50
140
nSec
+4.75
–4.75
–4.75
+5.0
–5.0
+5.0
+5.25
–5.25
+5.25
Volts
Volts
Volts
Power Supply Currents
+5V Supply
–5V Supply
+5V D Supply
–
–
+78
–47
+10
+83
–52
+12
mA
mA
mA
Power Dissipation
–
635
735
mW
Conversion Rate (–40 to 125°C)
4. A0 and A1 (pins 30, 31) should be bypassed with 0.1μf capacitors to
ground to reduce susceptibility to noise.
Power Requirements
ADCDS-1603 Modes of Operation
Power Supply Range
+5V A Supply
–5V Supply
+5V D Supply 
Power Supply Rejection
(5%) @25°C
The input amplifier stage of the ADCDS-1603 provides the designer with
a tremendous amount of flexibility. The architecture of the ADCDS-1603
allows its input-amplifier to be configured in any of the following
configurations:
t%JSFDU.PEF"$DPVQMFE
t/PO*OWFSUJOH.PEF
t*OWFSUJOH.PEF
–
±0.01
±0.03
%FSR/%V
Operating Temperature Range
ADCDS-1603
ADCDS-1603EX
0
–40
–
–
+70
+125
°C
°C
Storage Temperature
–65
–
+150
°C
When applying inputs that are less than 2.048Vp-p, a coarse gain
adjustment (applying an external resistor to pin 4) must be performed
to ensure that the full scale pixel data input signal (saturated signal)
produces 2.048Vp-p signal at the input-amplifier's output (VOUT)
(See figure 2b & 2C).
Environmental
Package Type
In all three modes of operation, the pixel data portion of the signal at
the CDS input (i.e. input-amplifier's VOUT) must be more negative than its
associated reference level and VOUT should not exceed 2.048Vdc.
40-Pin, TDIP, 2.24" × 1.27" FR4 PCB
Weight
18.1 Grams
Pin Type
.020 Diameter Au Plate Phosphor Bronze
Cover
The ADCDS-1603 achieves its specified accuracies without the need for
external calibration. If required, the device's small initial offset error can be
reduced to zero using the OFFSET ADJUST (pin 2) feature (See figure 3). For
fine gain adjustment model, contact the factory.
Tin Plate Steel
~See Table 3.
See Timing Specs, Table 2.
€See Technical Note: Optimal Performance.
CMOS Loading
‚A0, A1 = LO
Direct Mode (AC Coupled)
TECHNICAL NOTES
Figure 2a. describes the configuration for applications using a pixel data
input signal with a maximum amplitude of 0.342Vp-p. In this case the input
amplifier is configured for the maximum gain of 5.99 (VOUT = 1+(499/100)).
All input resistors having a 0.1% tolerance.
This is the most common input configuration as it allows the ADCDS-1603
to interface directly to the output of the CCD with a minimum amount of
analog "front-end" circuitry. This mode of operation is used with full-scale
pixel data input signals from 0.342Vp-p to 2.048Vp-p.
1. Obtaining fully specified performance from the ADCDS-1603 requires
careful attention to pc-board layout and power supply decoupling.
The device's analog and digital grounds are connected to each other
internally. Depending on the level of digital switching noise in the overall
CCD system, the performance of the ADCDS-1603 may be improved by
connecting all ground pins (7,32,33,35, 37) to a large analog ground
plane beneath the package. The use of a single +5V analog supply for
both the +5VA (pin 36) and +5VD (pin 34) may also be beneficial.
2. Bypass all power supplies to ground with a 4.7μf ceramic capacitor in
parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to
the package as possible.
VIN
N.C.
4
100
3
0.01μF
Rext
499
VOUT
= 2.048Vp-p
5
5k
22pf
Figure 2a. Direct Mode
VIN
N.C.
4
100
3
0.01μF
Figure 2b. describes the configuration for applications using a pixel
data input signal with an amplitude greater than 0.342Vp-p and less
than 2.048Vp-p. Using a single external series resistor, the coarse gain
of the ADCDS-1603 can be set. The coarse gain of the input amplifier
can be determined fron the following equation: VOUT = 2.048Vp-p = VIN*
(1+(499/(100+Rext))) (all internal resistors having a 0.1% tolerance).
Rext
499
V OUT
= 2.048Vp-p
5
5k
22pf
Figure 2b. Direct Mode
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N.C.
VIN
4
100
3
0.01μF
499
V OUT
= 2.048Vp-p
5
5k
22pf
Figure 2c. Non-inverting Mode
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MDA_ADCDS-1603.E06 Page 3 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Non-Inverting Mode
The non-inverting mode of the ADCDS-1603 allows the designer to either
attenuate or add non-inverting gain to the pixel data input signal. This
configuration also allows bypassing the ADCDS-1603's internal coupling
capacitor, allowing the user to provide an external capacitor of appropriate
value.
Figure 2c. describes the typical configuration for applications using pixel
data input signals with amplitudes greater than 0.342Vp-p and less than
2.048Vp-p. Using a single external series resistor, the coarse gain of the
ADCDS-1603 can be set. The coarse gain of the circuit can be determined
from the following equation:
VOUT = 2.048Vp-p = VIN*(1+(499/(100+Rext))),
with all internal resistors having a 0.1% tolerance.
Figure 2d. describes the typical configuration for applications using a
pixel data input signal whose amplitude is greater than 2.048Vp-p. Using
a single external series resistor (Rext 1) in conjunction with the internal
5K (1%) resistor to ground, an attenuation of the input signal can be
achieved. The coarse gain of this circuit can be determined from the
following equation:
VOUT = 2.048Vp-p = [VIN*(5000/(Rext1+5000))]*
[1+(499/(100+Rext2))],
with all internal resistors having a 0.1% tolerance.
Inverting Mode
The inverting mode of operation can be used in applications where the
analog input to the ADCDS-1603 has a pixel data input signal whose
amplitude is more positive than its associated reference level. The
ADCDS-1603's correlated double sampler (i.e. input amplifier's VOUT)
requires that the pixel data signal's amplitude be more negative than its
reference level at all times (see timing diagram for details). Using the
Rext2
4
100
3
0.01μF
Figure 2e. describes the typical configuration for applications using a pixel
data input signal with a maximum amplitude of 0.342Vp-p. The coarse
gain of this circuit can be determined from the following equation:
VOUT = 2.048Vp-p = –VIN*(499/100),
with all internal resistors having a 0.1% tolerance.
Figure 2f. describes the typical configuration used in applications
needing to invert pixel data input signals whose amplitude is greater
than 0.342Vp-p. Using a single external series resistor, the initial gain
of the ADCDS-1603 can be set. The coarse gain of this circuit can be
determined from the following equation:
VOUT = 2.048Vp-p = –VIN*(499/100+Rext),
with all internal resistors having a 0.1% tolerance.
Offset Adjustment
Manual offset adjustment for the ADCDS-1603 can be accomplished
using the adjustment circuit shown in Figure 3. A software controlled
D/A converter can be substituted for the 20KΩ potentiometer. The offset
adjustment feature allows the user to adjust the Offset/Dark Current level
of the ADCDS-1603 until the output bits are 00 0000 0000 0000 and the
LSB flickers between 0 and 1. The ADCDS-1603's offset adjustment is
dependent on the value of the external series resistor used in the offset
adjust circuit (Figure 3) and the gain of the input-amplifier.
It should be noted that with increasing amounts of offset adjustment
(smaller values of external series resistors), the ADCDS-1603 becomes
more susceptible to power supply noise or voltage variations seen at the
wiper of the offset potentiometer.
Rext
499
–VIN
V OUT = 2.048Vp-p
NO CONNECT
Rext1
ADCDS-1603 in the inverting mode allows the designer to perform an
additional signal inversion to correct for any analog "front end" preprocessing that may have occurred prior to the ADCDS-1603.
3
VOUT = 2.048Vp-p
5k
100
499
ADCDS-1603
0.01μf
VOUT = 2.048Vp-p
20k
5
5k
22pf
Figure 2f. Inverting Mode
+5V
NO CONNECT
0.01μf
22pf
Figure 2d. Non-inverting Mode
4
3
499
5
5k
–VIN
100
NO CONNECT
5
VIN
4
External
Series
Resistor
Offset
Adjust
2
22pf
–5V
Figure 2e. Inverting Mode
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Figure 3. Offset Adjustment Circuit
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MDA_ADCDS-1603.E06 Page 4 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Fine Gain Adjustment
Optimal Performance
For fine gain adjustment model, contact the factory.
Disturbances to the system while the A/D is undergoing a conversion
can result in degradation of performance. It is therefore recommended
that both digital and analog signals (including the Reference/Pixel data
inputs to the ADCDS) not be allowed to switch during a time window of
150ns to 300ns following the rising edge of the Start Convert command
when operating in the 0°C to 70°C temperature range, and from 140ns
to 320ns for the extended temperature range. See timing Figure 7
"A/D Critical Conversion Window."
Output Coding
The ADCDS-1603's output coding is Straight Binary as indicated in
Table 1. The table shows the relationship between the output data
coding and the difference between the reference signal voltage and
its corresponding pixel data signal voltage.
The max conversion rate of 2.3MHz for the ADCDS-1603 is dictated by
the settling time of the input circuitry and the conversion time requirement of the A/D converter. Switching the analog input from Reference
to pixel data 300ns after the rising edge of Start Convert allows a sufficient amount of settling time (approx. 130ns) for the pixel data input
signal to settle to the 16 bit accuracy. In the unique application where
the Reference to Pixel data signal is presented to the ADCDS-1603 prior
to the 120ns to 300ns restriction it may be possible to increase the
ADCDS-1603 conversion rate up to 3MHz.
Table 1. Output Coding
Reference – Pixel Data
(V)
Scale
Digital Output
>+2.048
2.048
1.536
1.024
0.512
0.256
0.00003125
0
<0
>Full Scale
Full Scale -1LSB
3/4FS
1/2FS
1/4FS
1/8FS
1LSB
0
<0
1111 1111 1111 1111
1111 1111 1111 1110
11 0000 0000 0000
10 0000 0000 0000
01 0000 0000 0000
00 1000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
0000 0000 0000 0000
~

Note: At initial power-up, the first 186 conversions should be ignored.
Resultant signal from internal CDS (Input to A/D). Assumes Input Amplifier gain set properly.
See "Modes of Operation" section.
The pixel data portion of the differential signal must be more negative than its associated
reference level and VOUT should not exceed +2.048V DC.
+5VD
4.7μF
–5VA
4.7μF
+5VA
4.7μF
0.1μF
0.1μF
0.1μF
34
6
4.7μF
+5V
38
36
23 BIT 1 (MSB)
+2.048V REFERENCE OUT
22 BIT 2
0.1μF
External Series
Resistor
21 BIT 3
ADCDS-1603
2
20 BIT 4
19 BIT 5
OFFSET ADJUST
18 BIT 6
20K7
3
–5V
See
Figures
2a–2f
17 BIT 7
DIRECT INPUT
16 BIT 8
4
INVERTING INPUT
15 BIT 9
14 BIT 10
5
13 BIT 11
NON-INVERTING INPUT
12 BIT 12
30
A0
11 BIT 13
10 BIT 14
31
0.1μF
A1
0.1μF
25
START CONVERT
27
9
BIT 15
8
BIT 16 (LSB)
DATA VALID
26
REF. HOLD
32, 33 DIGITAL GROUND
7, 35, 37
ANALOG GROUND
Figure 6. ADCDS-1603 Connection Diagram
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MDA_ADCDS-1603.E06 Page 5 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1603's input stage must have sufficient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle €. If only a single analog
bandwidth was offered, the ADCDS-1603's bandwidth would be set
to acquire and digitize CCD output signals to 16-bit accuracy, at the
maximum conversion rate of 2.3MHz (434ns see Figure 8 for details).
Applications not requiring the maximum conversion rate would be
forced to use the full analog bandwidth at the possible expense of noise
performance.
The ADCDS-1603 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1603 allows the user to "bandwidth
limit" the input stage in order to realize the highest level of noise performance
for the application being considered. Table 2 describes recommendations in
selecting the appropriate reference hold (Reference Aquisition Time) and CDS
output (Pixel Data Settling Time) needed for a particular application. Each of
the selections listed in Table 3 have been optimized to provide only enough
analog bandwidth to acquire a full scale input step (Vsat), to 16-bit accuracy,
in a single conversion. Increasing the analog bandwidth (using a faster settling
and acquisition time) would only serve to potentially increase the amount of
noise at the ADCDS-1603's output. The ADCDS-1603 uses a two bit digital
word to select four different analog bandwidths for the ADCDS-1603's input
stage (See Table 2 for details). Table 3 shows typical RMS noise for given
bandwidth and gain settings.
Table 2. Timing Specification €
Table 3. RMS Noise
Parameters
2.3 MHz Conversion
Conversion Time
A0 (pin 30)
A1 (pin31)
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
1.8 MHz Conversion
Conversion Time
A0 (pin 30)
A1 (pin31)
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
1 MHz Conversion
Conversion Time
A0 (pin 30)
A1 (pin31)
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
800 kHz Conversion
Conversion Time
A0 (pin 30)
A1 (pin31)
Reference Acquisition Time
Pixel Data Settling Time
Start Convert
€
Symbol€
Min.
Typ.
Max.
Units
T1
–
–
–
–
–
20
434
LO
LO
180
120
50
3
–
–
–
134
140
ns
–
–
–
–
–
20
555
HI
LO
230
205
50
–
–
–
–
–
140
ns
–
–
–
–
–
20
1000
LO
HI
370
520
50
–
–
–
–
–
140
ns
–
–
–
–
–
20
1250
HI
HI
470
680
50
–
–
–
–
–
140
ns
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
T4
ns
ns
ns
ns
ns
ns
Parameters
Min.
Typ.
Max.
Units
2.3 MHz Conversion
A0
A1
Gain = (pin 4 open)
Gain = 6 (pin 4 - to GND)
–
–
–
–
–
–
1.5
2.1
LO
LO
–
–
LSB RMS
LSB RMS
2 MHz Conversion
A0
A1
Gain = (pin 4 open)
Gain = 6 (pin 4 - to GND)
–
–
–
–
–
–
1.4
2
HI
LO
–
–
LSB RMS
LSB RMS
1 MHz Conversion
A0
A1
Gain = (pin 4 open)
Gain = 6 (pin 4 - to GND)
–
–
–
–
–
–
1.3
1.6
LO
HI
–
–
LSB RMS
LSB RMS
800 kHz Conversion
A0
A1
Gain = (pin 4 open)
Gain = 6 (pin 4 - to GND)
–
–
–
–
–
–
1.2
1.5
HI
HI
–
–
LSB RMS
LSB RMS
ns
ns
See timing figures 7 and 8.
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MDA_ADCDS-1603.E06 Page 6 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Timing
Once the A/D conversion has been initiated, the Reference Hold (Pin 26)
can be placed back into the "Acquisition" mode in order to begin aquiring
the next reference level. For optimal performance the ADCDS-1603's
should be placed back into the "Aquisition" mode (Reference Hold to logic
"0") during the CCD's "Reference Quiet Time" ("Reference Quiet Time" is
defined as the period when the CCD's reference signal has settled from
all switching transients to the desired accuracy (see Figure 7.) Placing the
sample-hold back into the "aquisition" mode during the "Reference Quiet
Time" prevents the ADCDS-1603's internal amplifiers from unnecessarily
tracking (reproducing) the reset feedthrough glitch that occurs during the
CCD's reset to reference transition.
The ADCDS-1603 requires two independently operated signals to
accurately digitize the analog output signal from the CCD array.
t
3FGFSFODF)PMEQJO
t
4UBSU$POWFSUQJO
The "Reference Hold" signal controls the operation of the internal
correlated double sampler (CDS) circuit. A logic "1" capture the value of
the CCD's reference signal. The Reference Hold Signal allows the user to
control the exact moment when the internal CDS is placed into the "hold"
mode. For optimal performance the internal CDS should be placed into the
"hold" mode once the reference signal has fully settled from all switching
transients to the desired accuracy (t2).
Disturbances to the system while the A/D is undergoing a conversion can
result in degradation of performance. It is therefore recommended that
both digital and analog signals (including the Reference/Pixel data inputs
to the ADCDS) not be allowed to switch during a time window of 150ns
to 300ns following the rising edge of the Start Convert command when
operating in the 0°C to 70°C temperature range, and from 140ns to
320ns for the extended temperature range. See timing Figure 7
"A/D Critical Conversion Window."
Once the reference signal has been "held" and the pixel data portion
of the CCD's analog output signal appears at the ADCDS-1603's input,
the ADCDS-1603's correlated double sampler produces a "CDS Output"
signal (see Figure 8.) which is the difference between the "held"
reference level and its associated pixel data level (Reference-Pixel Data).
When the "CDS Output" signal has settled to the desired accuracy (t3), the
A/D conversion process can be initiated with the rising edge of the Start
Convert (Pin 25) signal.
Note: At initial power-up, the first 186 conversions should be ignored.
300 ns min.
START
CONVERT
150 ns max.
A/D Critical
Conversion
Window
Reset
Reference
"Quiet Time"
CCD
OUTPUT
Reference
Pixel Data
Reference
REFERENCE
HOLD
Hold
Acquisition
Time
t4
Acquisition mode during
Reference “Quiet Time”
Figure 7. Reference Hold Timing
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MDA_ADCDS-1603.E06 Page 7 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
Reset
Feedthrough
Glitch
CCD
OUTPUT
Reference N
Ref. N+1
Pixel
Data N
REFERENCE
HOLD
(Pin 26)
Pixel Data
N+2
Ref. N+3
Ref. N+4
Pixel Data
N+3
t2
Reference Hold
Reference
Acquisition
Time
t3
Pixel Data
Settling Time
Ref. N+2
Pixel Data
N+1
Full Scale Step
(Vsat)
CDS
OUTPUT
N+2
N+1
N
t1
N+3
t4
START CONVERT
(Pin 25)
90ns typ.
DATA VALID
(Pin 27)
Data Invalid
DATA
Data Invalid
10ns min.
30ns max.
Data Invalid
Data Invalid
* 20ns min.
N-1 Data Valid
N Data Valid
N+1 Data Valid
N+2 Data Valid
* Output Data guaranteed to be valid a minimum of 20ns after falling edge of DATA VALID (pin 27).
++ CDS Output captured by S/H at rising edge of Start Convert (pin 25).
Figure 8. ADCDS-1603 Timing Diagram
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
Figure 9. ADCDS-1603 Differential Nonlinearity, LSBs
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MDA_ADCDS-1603.E06 Page 8 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
ADCDS-1603 Grounded Input Histogram – 2.3 MHz Rate
2.3 MHz Rate Gain = 6, A0=LO, A1=LO
2.29 LSB RMS, 12uV RMS
2.3 MHz Rate Gain = 1, A0=LO, A1=LO
1.64 LSB RMS, 51.1uV RMS
12000
18000
16000
10000
14000
8000
12000
10000
6000
8000
4000
6000
4000
2000
2000
0
0
19
21
23
25
Output Code
27
29
54
31
59
62
65
68
Output Code
71
74
ADCDS-1603 Grounded Input Histogram – 1.8 MHz Rate
1.8 MHz Rate Gain = 1, A0=HI, A1=LO
1.55 LSB RMS, 48.3uV RMS
1.8 MHz Rate Gain = 6, A0=HI, A1=LO
2.07 LSB RMS, 10.8uV RMS
18000
14000
16000
12000
14000
10000
12000
10000
8000
8000
6000
6000
4000
4000
2000
2000
0
0
24
26
28
30
Output Code
32
34
more
30
32
34
36
38
40
42
44
46
more
Output Code
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MDA_ADCDS-1603.E06 Page 9 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
ADCDS-1603 Grounded Input Histogram – 1.0 MHz Rate
1.0 MHz Rate Gain = 6, A0=LO, A1=HI
1.62 LSB RMS, 8.5uV RMS
1.0 MHz Rate Gain = 1, A0=LO, A1=HI
1.32 LSB RMS, 41.3uV RMS
20000
20000
18000
18000
16000
16000
14000
14000
12000
12000
10000
10000
8000
8000
6000
6000
4000
4000
2000
2000
0
0
33
35
37
39
Output Code
41
43
33
more
35
37
39
41
43
45
47
Output Code
ADCDS-1603 Grounded Input Histogram – 800 MHz Rate
800 kHz Rate
Gain = 1, A0=HI, A1=HI
1.31 LSB RMS,
800 kHz Rate
41.0uV RMS
Gain = 6, A0=HI, A1=HI
1.65 LSB RMS,
8.6uV RMS
18000
22000
20000
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
16000
14000
12000
10000
8000
6000
4000
2000
0
39
41
43
45
47
49
41
43
45
47
49
51
53
Output Code
Output Code
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MDA_ADCDS-1603.E06 Page 10 of 11
ADCDS-1603
16-Bit, 2.3 Megapixels/Second
CCD Signal Processor
INPU/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
FUNCTION
NO CONNECTION
OFFSET ADJUST
DIRECT INPUT
INVERTING INPUT
NON-INVERTING INPUT
+2.048V REF. OUTPUT
ANALOG GROUND
BIT 16 (LSB)
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
MECHANICAL DIMENSIONS inches (mm)
PIN
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
FUNCTION
NO CONNECTION
NO CONNECTION
–5VA
ANALOG GROUND
+5VA
ANALOG GROUND
+5VD
DIGITAL GROUND
DIGITAL GROUND
A1
AØ
NO CONNECTION
NO CONNECTION
DATA VALID
REFERENCE HOLD
START CONVERT
NO CONNECTION
BIT 1 (MSB)
BIT 2
BIT 2
ADCDS-1603
1.27 TYP.
(32.25)
16-BIT, 2.3MHz
CCD SIGNAL PROCESSOR
2.24 TYP. (56.90)
0.100 TYP.
(2.540)
0.32 TYP
(8.128)
1.900 ±0.008
(48.260)
0.100 TYP.
(2.540)
TDIP
Package
ORDERING INFORMATION
MODEL
ADCDS-1603
ADCDS-1603EX
ADCDS-1603-C
ADCDS-1603EX-C
OPERATING
TEMPERATURE RANGE
0.900 ±0.010
(22.86)
PACKAGE
(40-PIN)
0 to 70°C
–40°C to 125°C
0 to 70°C
–40°C to 125°C
R.04
TYP
TDIP
TDIP
TDIP
TDIP
90°
TYP
0.34
(8.64)
Contact factory for SMT models.
-C suffix models are RoHS compliant.
SMT
Package
0.11 (2.79)
.005
All Leads
0.28 REF
(7.11)
Contact MPS for more information.
USA:
Mansfield (Ma), Tel: (508) 339-3000, email: [email protected]
Canada: Toronto, Tel: (866) 740 1232, email: [email protected]
Murata Power Solutions, Inc.
11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A.
Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
UK:
Milton Keynes, Tel: +44 (0)1908 615232, email: [email protected]
France:
Montigny Le Bretonneux, Tel: +33 (0)1 34 60 01 01, email: [email protected]
Germany: München, Tel: +49 (0)89-544334-0, email: [email protected]
DS-0565E 12 Jun 2008
www.murata-ps.com email: [email protected] ISO 9001 REGISTERED
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply
the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without
notice.
© 2008 Murata Power Solutions, Inc.
www.murata-ps.com
Japan:
Tokyo, Tel: 3-3779-1031, email: [email protected]
Osaka, Tel: 6-6354-2025, email: [email protected]
Website: www.murata-ps.jp
China:
Shanghai, Tel: +86 215 027 3678, email: [email protected]
Guangzhou, Tel: +86 208 221 8066, email: [email protected]
Technical enquiries email: [email protected], tel: +1 508 339 3000
MDA_ADCDS-1603.E06 Page 11 of 11