LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Description Features The LX7302 is a single phase step down DC-DC controller IC designed to drive a high side N-channel MOSFET and a low side N-channel synchronous rectifier. The LX7302 uses a fixed on-time hysteretic control approach for fast transient response. Regulation is accomplished on a pulse-by-pulse basis without the need for an integrating error amplifier. The constant on-time is determined by the product of the ratio of the input to output voltage and the user adjustable switching period. Integrated High & Low Side Drivers The output voltage is programmable by an external reference applied to RS1 (in External Reference Mode) or by the VID pins (in self referenced mode). When using the VID pins, there are four possible reference levels programmed by resistors attached to the RS# pins. A droop function is supported to reduce the output voltage under heavy loads minimizing overshoot upon load release. Input Voltage Range 5V to 26V 200kHz to 1MHz Switching Frequency Differential Feedback Inductor Current Sensing Droop Control Enable/Disable VID Control or Ext Reference Power Saving Mode OCP, OVP, UVP, OTP, UVLO Applications Microprocessor Core DDR Memory Notebook Computers The LX7302 has protection functions that latch off the power MOSFETs in the event of a fault. Fault conditions are under voltage, over voltage and over temperature. A power good indicator is provided. A cycle-by-cycle current limit will limit the peak current in the lower MOSFET. If the output voltage should drop as a result of sustained current limit, the under voltage detect will trip and shut off the converter. Under voltage lock out (UVLO) keeps the converter off in the event the VCC voltage is too low. Figure 1. Product Highlight Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 1 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Typical Application Diagrams VIN = 5 to 25V 3 x 330uF BSC057N03LS L 560nH VOUT BSC030N03LS VCC BSC030N03LS 1.0k 2 x 560uF 0.47uF 1.0V (RS1 Selected) 10 1uF 10k 4.7k 4.7k 0 Droop Disable CBST SW LG VCC OCP CSP VCC 0.1uF VCC BST UG POK RS3 RS2 10k Power Good External Reference (Optional) 80.6k and 1nF not installed for VID operation; 41.2k not installed for external reference operation. 1nF RS1 RS0 RT AGND FBP External Reference Control (Optional) 80.6k 43k CSN EN/P VID1 VID0 TON 10k VID1 1M Enable VID0 GND VIN FCCM/ PSM 1nF 10nF 33.2k 37.4k 41.2k 49.9k 49.9k Figure 2: Typical Application Diagram Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 2 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet SW LG VCC OCP CSP Pin/Ball Configuration 20 BST UG POK RS3 RS2 19 18 17 16 1 15 MSC 7302 xxxx 2 3 4 14 13 12 5 11 7 8 9 LQ PACKAGE (Top View) Exposed Pad = GND 10 RS1 RS0 RT AGND FBP 6 CSN EN/P VID1 VID0 TON RoHS / Pb-free 100% Matte Tin Finish Figure 3: Pinout Ordering Information Ambient Temperature Type Package Part Number Packaging Type 0°C to 85°C RoHS compliant, Pb-free QFN 3x3 20L LX7302CLQ LX7302CLQ-TR Bulk/Tube Tape and Reel Thermal Properties Thermal Resistance θJA Min Typ 39 Max Units °C/W Note: The Jx numbers assume no forced airflow. Junction Temperature is calculated using TJ = TA + (PD x JA). In particular, θJA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 3 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Pin Description Pin Pin Number Designator 1 BST 2 3 UG POK 4 RS3 5 RS2 6 RS1 7 RS0 8 RT 9 AGND 10 FBP 11 TON 12 VID0 Copyright © 2012 Rev. 1.0, 12/17/2012 Description Boost - Power pin - Used for the upper MOSFET driver charge pump. Connect a 100nF capacitor from the BST pin to the SW pin. Upper Gate – Power Pin - Connect to the gate of the High side N-ch MOSFET(s). Power OK – Logic Output Pin – Open drain logic; hi – Z indicates power good. Resistor 3 – Signal Pin - Reference voltage 3 is programmed using a resistor to ground. The reference current based on the value of RT will flow through the RS3 programming resistor. Resistor 2 – Signal Pin - Reference voltage 2 is programmed using a resistor to ground. The reference current based on the value of RT will flow through the RS2 programming resistor. This dual use pin is also used to program the reference mode so the IC uses either internal or external reference. Grounding RS2 selects the internal reference mode. Resistor 1 – Signal Pin - Reference voltage 1 is programmed using a resistor to ground. The reference current based on the value of RT will flow through the RS1 programming resistor. When using an external reference, (with RS2 grounded), the external reference is applied to the RS1 pin. Resistor 0 – Signal Pin – Reference voltage 0 is programmed using a resistor to ground. The reference current based on the value of RT will flow through the RS0 programming resistor. Resistor Switching Period – Signal Pin – Sets the reference current for the IC. Reference current is VRT/RRT. For normal operation, RRT should be 49.9kΩ to AGND. Analog Ground Reference – Signal Pin – Connect to ground at the point of regulation. Feedback Positive – Signal Pin – Connect to the output at the point of regulation. TON programming – Signal pin – This pin is used to control the switch on-time and indirectly controls the switching frequency in the steady state. A resistor connects from this pin to the input voltage for the power converter. Voltage Programming 0 – Logic Input – Logic input used to select one of 4 possible resistor programmable reference levels. Connect to system ground when not used. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 4 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Pin Pin Number Designator 13 VID1 14 EN/P 15 CSN 16 CSP 17 OCP 18 VCC 19 LG 20 SW EP GND Copyright © 2012 Rev. 1.0, 12/17/2012 Description Voltage Programming 1 – Logic Input - Logic input used to select one of 4 possible resistor programmable reference levels. Connect to system ground when not used. Enable/Power Save – Signal Pin - Tri level “logic” pin used to enable the IC and to select either FCCM mode or PSM mode. Low level disables the IC; float this pin to select FCCM; connect to VCC to select PSM. Current Sense Negative – Signal Pin – This pin is used as the reference pin for the measuring the current in the external inductor for the droop function. Grounding this pin disables the droop function. Current Sense Positive – Signal Pin – This pin is used to measure current in the external inductor to be used for the droop function. May be left floating when not used (CSN connected to GND). OCP – Signal Pin - This pin is used to set the switch current limit. A programming resistor connects from this pin to the SW pin. VCC (Chip Power Supply) – Power Pin – This pin provides power to the IC. It should be decoupled to GND with at least 100nF. Lower Gate – Power Pin – Connect to the gate of the Synchronous rectifier N-ch MOSFET(s). Switch Node – Power Pin - This pin connects to the line or input side of the power inductor and the common point of the high side and low side switches. Ground – Power Pin – The Exposed Pad of the IC is to be connected to the GND plane. When connecting to the ground plane 12 mil diameter vias spaced on a 47mil matrix should be used to keep inductance low and to provide a path for thermal conduction. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 5 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Functional Block Diagram EN/P EN/P Level Detect PSM Enable IC Enable UVLO VCC BST UG On Time Generator TON Zero Crossing Detector SW R FBP VCC Q S FB Ref LG PSM Switch Control Logic OVREF GND IOCS OCP UVREF Over temp Detect POK PGTH RT Oscillator REF SR = 10xSS Digital Stepper DAC and Logic IREF Generator SR_Ref VID0 VID1 RS0 RS1 RS2 RS3 Raw_Ref + IC On/off via RS2 + Reference Programming Droop Disable AGND - CSP Droop Function CSN Bandgap FBP Offset Correction FB Ref IC Enable IREF Droop Disable 0.4V Figure 4: Block Diagram Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 6 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Absolute Maximum Ratings Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability. Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -5 -5 -0.3 -0.3 0 -25 VCC to GND BST, UG to SW SW to GND LG to GND TON, SW to GND (<100ns) BST to GND (<100ns) UG to SW (<100ns) LG to SW (<100ns) AGND to GND All other pins to GND Operating Junction Temperature Storage Junction Temperature Package Peak Temp for Solder Reflow (40 seconds maximum exposure) Max 7 7 27 VCC + 0.3 40 47 7 VCC + 0.3 0.3 VCC + 0.3 150 150 Units V V V V V V V V V V °C °C 260 °C Operating Ratings Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. Min 4.5 5 0.6 0 VCC VIN VOUT Ambient Temperature Max 5.5 26 2.5 85 Units V V V °C Note: Corresponding Absolute Max Junction Temperature is 125°C. Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 7 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Electrical Characteristics The following specifications apply over the operating ambient temperature of 0C TA 85C except where otherwise noted with the following test conditions: VIN=12V, VCC =5V, AGND = GND, RRT = 49.9k, VCSN = 0V. Typical parameter refers to TJ = 25°C. Symbol Parameter Operating Current VCC Input IccS Current at no switching VCC Input IccQ Current at Switching Input Current at IccSD Shutdown VCC UVLO Under Voltage VCC Lockout UVLO VCC Hysteresis TUVLO Filter REFIN Shutdown REFIN Enable VRS1 Threshold VRSH Hysteresis FB Accuracy FB OFFSET in VFBR REFIN Mode FB Voltage in VFBV VID MODE FB Pin Input IFB Current Feedback VFB Voltage range Start up Timing Sequence TD Copyright © 2012 Rev. 1.0, 12/17/2012 Start-up Delay Conditions Min Typ Max Units FB is 110% higher than V(RSET1) 1.8 2.5 mA Switching, HDrv and LDrv has no capacitive load 3 6 mA EN = GND (including BST current) 70 120 µA 4.1 3.9 4.5 4.3 V V 200 300 mV VCC rising VCC falling 3.9 3.7 2 Measured relative to GND When MODE/RSET2 = AGND, RS1 = 1.00V VID0 = X, VID1 = X. RRT = RRS0 = RRS1 = RRS2 = RRS3 From the application of enable until sampling RS2 for mode detection. 300 µS 375 450 mV 75 120 mV 0.980 1.00 1.010 V 1.225 1.250 1.275 V -30 0.1 µA 0.5 2.2 V 1 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 ms Page 8 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Symbol Parameter Conditions Soft-start Rate dVFB/dt of Change Total Start-up TTRP TD + TSS; To VFB = 1V Time Power On Delay after completion of softTDF Default Voltage start until VID programming Period becomes active Reference Programming Slew Rate Limit VID change dVFB/dt Slew rate Adaptive On-time Control TON Operating ITON Current Minimum TONMIN Controllable On-time TON On-time Control VIN = 9V, VOUT = 0.75V; RTON = 1M Minimum Off TOFF VFB = 90% of VREG Time EN/PSM Off-to-FCCM enable (threshold Off to FCCM rising) Mode FCCM-to-off hysteresis VES/P FCCM-to-PSM enable (threshold FCCM Mode to rising) PSM mode PSM-to-FCCM hysteresis State with EN/PSM Enabled and in FCCM mode Floating IES/P Input Current VID Logic VVID# Logic Threshold VID Input VVID#H Hysteresis IVID# Pin Current REFIN RS1 Current in IRS1 REFIN MODE Copyright © 2012 Rev. 1.0, 12/17/2012 Min Typ Max Units 703 965 1227 mV/ms 5 ms 14.6 25.8 37.0 ms 6.88 9.5 12.12 mV/μs 5 15 25 µA 35 65 ns 312 390 468 ns 220 430 640 ns 6.7 10 14.2 0.3 1.65 3.0 29.6 33.3 37.1 3 3.5 0.9 1 1.1 V -3 0 3 µA 0.7 0.9 1.1 V 15 40 65 mV -5 5 µA -100 100 nA Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 %VCC Page 9 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Symbol Parameter Power-good Power-good VPG Transition High Threshold Power GOOD ZPOK Internal FET Rdson Power Good Leakage Current Output Driver High-side Driver RUGH Upper Impedance High-side Driver RUGL Pull Low Impedance Low-side Driver RLGH Pull High impedance Low side driver RLGL pull low Impedance Deadband Time from SW Going tDBLH Low to LDrv Going High Deadband Time from LDrv Going tDBHL Low to High Side Going High Zero Crossing Comparator VZCC Built-in Offset Comparator TZCC Delay Comparator AZCC Overall DC gain Copyright © 2012 Rev. 1.0, 12/17/2012 Conditions Min Typ Max Units VFB rising, In percentage of output voltage set-point 87 90 93 %VREG 60 -5 1 Ω 5 µA 1.5 Ω 1.5 Ω 1.5 Ω 0.5 Ω 10 ns 30 ns 5 mV 20 ns 80 DB Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 10 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Symbol Parameter Conditions Min Current Limit Comparator Current Limit VOCP -8 Threshold OCP Pin IOCP Programming 11.5 Current Comparator TZCC Delay Droop Amplifier (Droop Disable Resistor removed for this section) ADRP = ∆VFB / ∆ (VDRP – VCSN); Droop Amplifier ADRP RCSP = 4.7k; VCSN > 500mV 1.5 Gain RSNS = 1.2k Droop Amplifier (Positive offset cannot result in VCSP-VCSN -7 Input Offset positive FB shift); VCSN > 500mV ICSN Input Current VCSN = 1V; VCSP = 0.95V -100 ICSP Input Current VCSN = 1V; VCSP = 0.95V Droop Enable Rising threshold with 2% typical VCSN 6 Threshold hysteresis FB UV/OV Detect FB UV VFB-UV Falling 40 Threshold FB OV VFB-OV Rising 100 Threshold TFB-FILT Analog Filter TFB-DF Digital Filter Soft Shutdown Soft Shutdown RSSD Resistance BST Pin VccVBST BST Pin Voltage With VSW = GND 0.5 Thermal Shut Down Thermal TJ Shutdown TJ rising Threshold Threshold TJ Hysteresis Copyright © 2012 Rev. 1.0, 12/17/2012 Typ Max Units 0 8 mV 13.5 15.5 µA 20 2.75 ns 4 V/V 7 mV -7.5 -25 +100 nA nA 8 10 %VCC 50 60 %VREG 130 150 %VREG 2 6 µS CLK 30 Ω V 160 °C 15 °C Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 11 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Typical Performance Curves EN/P FB EN/P Soft Start VID Lock Out Turn On Delay FB Soft Start VID Lock Out Turn On Delay Td VID Control Permitted External Ref EN/P Tss Dynamic VID Mode Tdf Td Figure 5. VID Mode Power On Timing Tss Dynamic REFIN Mode Tdf Figure 6. REFIN Power On Timing – Case 1 EN/P Efficiency vs. Output Current VOUT = 1V 100% FB 95% Soft Start VID Lock Out 90% Dynamic Change Permitted 85% Efficiency Turn On Delay External Ref 80% 75% 70% 65% VIN = 12V VIN = 5V VIN = 20V 60% 0.4V 55% Td Tss Dynamic Change Permitted Tdf Dynamic REFIN Mode 50% 0 5 10 15 20 25 30 Output Current (A) Figure 7. REFIN Power On Timing – Case 2 Copyright © 2012 Rev. 1.0, 12/17/2012 Figure 8. Efficiency Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 12 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Typical Performance Curves (Continued) Load Regulation; VOUT = 1.2V 1.00% 100% 95% 90% 85% 80% 75% 70% 65% 60% 55% 50% % Variation Efficiency Efficiency; FCCM vs PSM PSM 0.50% 0.00% -0.50% FCCM -1.00% 0 1 2 3 4 0 5 5 10 15 20 25 30 35 Output Current (A) Output Current (A) Figure 9. PSM vs. FCCM Efficiency Figure 10. Load Regulation VOUT – 1.21V VOUT – 1.21V LOAD STEP – 5A/DIV LOAD RELEASE – 5A/DIV Figure 11. Transient Response – Load Step Figure 12. Transient Response – Load Release Typical Performance Curves (Continued) Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 13 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet VOUT VID 0 & VID 1 SWITCH NODE Figure 13. VID Change – Low to High Copyright © 2012 Rev. 1.0, 12/17/2012 Figure 14. VID Change – High to Low Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 14 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Operation Theory DC-DC Switching Step Down Controller The DC-DC converter is a voltage mode hysteretic controller that uses a calculated constant “ontime” for the upper MOSFET switch. The constant on-time is a function of VIN. The switching frequency is a function of VOUT; the value of the resistor at TON scales the switching frequency and inversely scales the on-time. The lower MOSFET switch or synchronous rectifier turns on after the upper MOSFET switch turns off. The lower MOSFET remains on until the output voltage drops below the feedback threshold or when in PSM, the current in the inductor changes direction and begins to flow into ground. A new turn on cycle for the upper MOSFET begins when the output voltage drops below the feedback threshold. The hysteretic nature of the DC-DC converter responds very quickly to load transients. There is no error amp integrator to introduce a response delay and there is no loop compensation necessary since the loop responds on a cycle-bycycle basis. The cycle-by-cycle calculated on-time and frequency results in a nearly constant switching frequency under static loading conditions. On-Time And Frequency Calculation An internal one-shot timer turns on the high side driver with an on-time which is proportional to the input supply, VIN and inversely proportional to the output voltage, VOUT. Copyright © 2012 Rev. 1.0, 12/17/2012 The equation for the on-time is: 4.45 10 12 RTON VOUT TON VIN 0.5V The equation for the switching frequency is: FSW VOUT VIN TON Light Load Operation There are two possible modes of light load operation that are selectable using the EN/P pin: Forced Continuous Conduction Mode (FCCM) and Power Saving Mode (PSM). Under light loading, the current in the inductor can discharge to zero current and if allowed to, even reverse direction (start flowing into ground). This current flow into ground is unnecessary from a power conversion standpoint and results in some light load efficiency loss. In FCCM, the synchronous rectifier switch is held on for nearly the entire rectification portion of the switching period. Allowing current to flow into ground will effectively discharge the output capacitor which when sensed by the feedback comparator will cause the switching cycle to remain repetitive at the desired switching frequency. In PSM, a zero-crossing detector senses the reverse current flow and turns off the synchronous rectifier. There may be a significant delay time for the output capacitor to discharge when the synchronous rectifier has been shut off; the start of the next switch cycle is delayed until this occurs. In FCCM, the switching frequency remains continuous under light loading, but in PSM, the switching frequency will reduce under light loading. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 15 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Operation Theory (Continued) Ripple Offset Cancellation The Constant On-Time control triggers the start of a new switch cycle based on the output ripple voltage crossing the feedback threshold. This would result in a positive offset to the output equal to the ripple voltage divided by 2. The ripple correction provides a small offset to the feedback reference to shift the output voltage slightly such that the average feedback voltage is set nearly equal to the reference voltage. LP Filter Feedback + X3.5 - + REF Modes: Internal or External Reference There are two possible modes of operation for the LX7302 depending on the voltage applied to the RS2 pin when the LX7302 is enabled with UVLO de-asserted. The table below indicates which mode is selected: Mode Programming RS2 Pin Voltage Mode Selected VRS2 < 0.3V External Reference (REFIN) VRS2 > 0.5V Self Referenced (VID) When the REFIN mode is selected, the reference voltage for the regulator and protection functions is applied to the RS1 pin. The current source to RS1 is shut off when in the REFIN mode. For REFIN changes, the slew rate must be limited by an external RC filter at the RS1 pin. Copyright © 2012 Rev. 1.0, 12/17/2012 When the VID mode is selected, the LX7302 generates its own reference which can be one of four resistor programmable levels (using pins RS0, RS1, RS2 and RS3) selectable using the VID pins (VID0 and VID1). The table below shows the VID programming selections available in VID mode. VID Mode Reference Programming VID1 VID0 Reference Level 0 0 VREF0 = (1.25 x (RRS0 + 1000))/50.9 x 103 0 1 VREF1 = (1.25 x (RRS1 + 1000))/50.9 x 103 1 0 VREF2 = (1.25 x (RRS2 + 1000))/50.9 x 103 ; VREF2 > 0.4V 1 1 VREF3 = (1.25 x (RRS3 + 1000))/50.9 x 103 Note: The reference voltages must be programmed such that RRS1 || RRS2 > 17.5k. When the VID voltage is changed, the slew rate of change is controlled by an internal DAC that is clocked by an internal oscillator. The DAC steps the output in 20mV steps. For VID changes the DAC steps at a clock rate that is 10x faster than the clock rate used for the soft start slew rate. When the DAC has finished stepping, it will apply the RS# input so that there is no quantization error in the final value. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 16 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Operation Theory (Continued) Soft Start EN/P Voltage IC State Mode Soft start is implemented using a digital soft-start technique. In this method the reference voltage for the feedback comparator is increased in 20mV steps at a fixed rate until the programmed output voltage level is reached. Soft-start does not begin unless the UVLO start up criterion is met and the device is enabled via the EN/P pin. Low < 0.3V Disable No Output Switching Mid (float) >0.5V;<1.6V Enable FCCM High >1.8V Enable PSM The soft-start process in VID mode initially selects the voltage programmed at the RS2 pin as the reference. After the output is up and settled for delay of “Power On Default Voltage Period”, the VID selection inputs are then activated. The LX7302 monitors internal IC temperature and generates an over temperature fault if the temperature threshold is exceeded. If an over temperature fault occurs, the DC-DC converter will stop switching and the UG and LG outputs will turn the external MOSFET switches off. The driven MOSFETs remain turned off until the VCC power or EN/P pin is cycled. The soft-start process in REFIN mode will not begin until the external reference (applied to the RS1 pin) is at least 0.4V. The soft-start process ramps at a fixed dV/dt rate such that higher output voltages take longer to reach. REFIN Mode Shutdown If operating in REFIN mode and if the voltage on the RS1 pin is brought below 0.4V, the controller will shutdown (switches become off state; driving external MOSFET VGS = 0). The controller will remain latched off unless VCC is cycled above and below the UVLO threshold or the Enable pin is cycled off, then on. Output Over/Under Voltage Protection If an over-voltage fault or under-voltage fault occurs on the output as sensed at the feedback input, the DC-DC converter will stop switching and the UG and LG outputs will turn the external MOSFET switches off. A UVP condition must exist for 3 consecutive PWM cycles, but an OVP condition is triggered immediately. The driven MOSFETs remain turned off until the VCC power or EN/P pin is cycled. Input Under Voltage Lockout Protection EN/P Enable/Power Save Mode The EN/P input programming pin is a dual purpose pin; it provides the enable/disable function and also provides the means to select between the PSM mode/FCCM mode. If allowed to float, the enabled and FCCM mode is selected. The table below describes the function: Copyright © 2012 Rev. 1.0, 12/17/2012 Over Temperature Protection If there is a loss of IC input power (VCC) such that VCC drops below the UVLO threshold, the DC-DC converter will stop switching and the UG and LG outputs will turn the external MOSFET switches off. The driven MOSFETs remain turned off until the VCC power recovers. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 17 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Operation Theory (Continued) Over Current Protection Droop Over current protection is achieved by sensing current through the low side MOSFET. A bias current equal to ½ IRT flows through an external resistor connected to the OCP pin to the SW pin; this sets the current limit threshold. The current limit is set by the equation: The output current is monitored by sensing the current flow in the DCR of the inductor. The voltage across the DCR can be measured across the capacitor if the following relationship exists: Cs x Rs = L/DCR I LIMIT 0.5 I RT R OCP RDSON VSW Rs DCR Vcc VOUT Cs RCSN Where: ILIMIT = Output inductor ripple current peak; the magnitude of the inductor peak to peak current is determined by the value of TON, VIN, VOUT, and the output inductor value. The DC current level will be approximately ½ the inductor peak to peak current less than ILIMIT. SOFT SHUTDOWN When the output is disabled or shutdown as the result of a fault condition, a soft shutdown switch will close across the output and allow the output capacitor to discharge to GND. Dynamic Changes of Reference Voltage When a reference voltage change is detected on REFIN or the VID0 or VID1 pin, the protections for OVP, UVP and OCP are temporarily suspended while the DAC transitions to the new value. Switching mode is forced to FCCM during reference changes. When the digital stepper has transitioned between the initial and final levels, the protection functions are re-enabled, and if active, PSM mode is restored. The DAC does not control the REFIN slew rate, but it does track it and ensures the protection features are disabled and FCCM mode is active when the REFIN is transitioning. Copyright © 2012 Rev. 1.0, 12/17/2012 L RCSP CSN CSP VDroop 15k + Increasing Rs and Cs will result in lower ripple and a slower response time for the sensed voltage across Cs. The droop function simulates a resistor in series with the output that provides a voltage drop proportional to the loading current. The droop amplifies the voltage across the sense capacitor with a programmable gain that is determined by the value of RCSP: VDROOP VCS 15k RCSP The value of RCSN should be set equal to RCSP to minimize offset error due to op amp bias current. For temperature compensation, a PTC resistor can be used in place of RCSP. The Droop function can be disabled by grounding the CSN pin. Power Good The power good signal is an open drain output that is latched to high impedance when the feedback voltage becomes greater than 90% of the steady state internal reference voltage. POK becomes low impedance to GND if a fault condition occurs. Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 18 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Application Example As an example for calculating the component values, assume the following situation: VIN = 12VDC; FSW = 215kHz; L = 560nH; LDCR = 1mΩ Outputs: VID0 = 1.25V, VID1 = 1.036V, VID2 = 0.943V, VID3 = 0.840V Switching Frequency The requirement for on time at a 1.25V output is: TON VOUT 1.25 484ns FSW VIN 215 103 12 Consider a case requiring an additional droop of 50mV when there is 20A of inductor current. With an inductor DCR of 1mΩ, there will be a corresponding DCR voltage drop of 20A x 1mΩ = 20mV. The droop function gain required is 50mV/20mV = 2.5. Using the equations below, the sum of RS and RCSP must equal 6kΩ. It is desirable to keep Rs greater than 400Ω to keep its power dissipation low. The value of RCSP should reflect a standard PTC value. Also keeping RCSP >> Rs helps minimize the offset error by maximizing the Cs voltage. A good compromise is to use RCSP = 4.7kΩ and Rs = 1.3kΩ. VDCR 15k RS RCSP VDROOP We can then calculate RTON: RTON Droop Calculations (refer to DROOP section above) 20 15k 6k RS RCSP 50 For this case: TON VIN 0.5V 4.45 10 12 VOUT 484 10 9 12 0.5 1.0M 4.45 10 12 1.25 RCSP = 4.7kΩ for a PTC consider Panasonic ERAS27J472V. Use a 1M, 1% resistor. RCSN = RCSP = 4.7kΩ NOTE: In cases with short values for TON, there can be timing issues created by the additional delays associated with the responsiveness of the MOSFETs, particularly during start up. For these cases it may be necessary to increase TON. Rs = 1.3kΩ L 560nH 0.43F DCR Rs 1m 1.3k Cs = 0.47µF Cs To temperature compensate for the rise in DCR with temperature it is necessary to match the temperature coefficient of the inductor DCR (winding resistance) to that of RCSP. The copper resistance is about 3500PPM/°C. A PTC like the Panasonic ERA-S27J472V gives a tempco of 2700PPM/°C, which is close to the required tempco in an economical PTC 0805 resistor style. Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 19 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Application Example (Continued) VID Calculations The value of RRT is used to scale the IC reference current which affects the VID programming, slew rate control, and the OCP pin programming current. VID programming voltages are trimmed by the factory with RRT = 49.9kΩ: RRS 0 VRS 0 50.9 103 1000 50.9k 1000 49.9k 1.25 RRS1 VRS 1 50.9 103 1000 42.2k 1000 41.2k 1.25 RRS 2 VRS 2 50.9 103 1000 38.4k 1000 37.4k 1.25 VRS 3 50.9 103 RRS 3 1000 34.2k 1000 33.2k 1.25 Current Limit Calculations Over current protection is achieved by sensing current through the low side MOSFET. Therefore, the output DC current limit threshold requires knowledge of the RDSON value for the lower MOSFET. RDSON increases with temperature, which must be considered to avoid false current limit detection. Also considered is the inductor ripple current, which will play a role in determining the DC level at the current limit threshold. Inductor ripple current is determined by the value of the output inductor, TON, VIN, and VOUT. The exact value of the current limit threshold is difficult to predict due to the number of variables involved; however, a reasonable approximation can be made using worse case conditions. . Copyright © 2012 Rev. 1.0, 12/17/2012 Using the application schematic as an example, the BSC030N03LS FETs have a specified maximum RDSON of 4.7mΩ with a 4.5V gate voltage and 25°C junction temperature. Based on the datasheet, the RDSON increase at 100°C junction is 30%. 4.7mΩ x 1.3 = 6.1mΩ. Two of these FETs in parallel give a combined RDSON of 3.1mΩ The inductor is specified as 560nH +/- 20%. Increasing the inductance by 20% gives an inductance value of 672nH. Based on earlier calculations, TON = 484ns. VIN and VOUT are 12V and 1.25V, respectively. For a 30A DC current limit, we set the threshold to 30A plus ½ the inductor peak to peak ripple current: (V VOUT ) TON I LIMIT IDCLIMIT IN 2 L 12 1.25 484ns 30 A 34 A 2 672nH We use 34A to set ILIMIT: ROCP I LIMIT 0.5 I RT RDS ON 34 0.003 8.5k 0.5 24 10 6 Where: IRT = 1.25V/50.9kΩ Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 20 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Application Example (Continued) The above example is using one voltage operating point only; In an application where a range of input/output voltages are required, the VIN, VOUT, and TON values that generates the smallest ripple current (highest ILIMIT) would be used in the calculations. Note that the above method takes into account worse case conditions to avoid false current limit detection; under typical conditions the actual current limit will be much higher. Output Inductor Selection The output inductor is selected based on the desired amount of ripple current, generally determined as a percentage of maximum output current. The Ripple Factor, or percentage amount, is typically set for 30% to 50% of the maximum output current. For a Ripple Factor of 30%, and a load current of 30A, the inductor is selected: Lout Where: The input capacitor selected is based on the desired minimum input ripple voltage seen by the converter. 500mV or less ripple is recommended. Input ripple voltage magnitude is dependent on both the input capacitor’s capacitance and ESR values. For the most part the ESR will dominate, as long as the capacitance value is large enough. To determine the minimum input capacitance and maximum ESR required at VIN = 10V, a good rule of thumb would be to establish minimum capacitance and increase this value by 10x : CMIN T (VIN VOUT ) ON k * I OUT IOUTDC I INDC TON 10 VRIPPLE 30 4.17 586ns 10 310F 0.5 484ns (12 1.25) 578nH 0.3 * 30 Where: Where: k = 30% ripple factor Input Capacitor Selection The input capacitor is selected for minimum ripple voltage and ripple current capability at minimum input voltage. With a minimum input voltage of 10V, calculate the capacitor ripple current as follows: I INRIPPLE I OUT D 1 D 30 0.147 0.853 10.6 ARMS Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 21 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Application Example (Continued) 330μF is the closest standard value that will satisfy the above equation. Next the maximum ESR is determined. For margin decrease the desired ripple voltage by 10%: C ESR VRIPPLE 0.9 I OUTDC I INDC 0.5 0.9 17m 30 4.17 Output MOSFET Selection The LX7302 gate drivers output a maximum voltage of VCC; therefore logic-level FETs should be used. When selecting the output MOSFETs, the power dissipation should be considered. For the Synchronous FET, power dissipation is mostly in conduction loss, so the MOSFET’s RDSON rating will be of primary concern. To determine the power dissipation in the synchronous FET: PSYNC 1 D I OUTDC RDSON 2 Use the maximum specified RDSON of the MOSFET at 100°C. This number can be derived from the manufacturer’s graph of RDSON vs. Temperature. For the Control FET, both switching losses and conduction losses must be considered. Usually a trade-off between low gate charge and low RDSON is considered. Many manufacturers provide a Figure Of Merit (FOM) on their datasheets, which is simply the product of RDSON and gate charge. Consider the lowest FOM when choosing the Control MOSFET. Copyright © 2012 Rev. 1.0, 12/17/2012 To determine switching losses, the Control FET’s on and off switching times must first be determined. Switching times are dependent on the LX7302’s drive current available during the MOSFET on and off switching period. Each period is divided into two distinct time periods based on gate charge values, QGD and QGS2. QGS2 is the Gate to Source charge that occurs between the MOSFET gate threshold voltage (VTH) and the Miller Plateau voltage. Note that QGS2 is not to be confused with QGS. Most manufacturers do not specify QGS2 or Miller Plateau voltage; however they can be derived easily from the manufacturer’s graph of gate voltage vs. charge. See Figure 3 for details. Once the values for QGS2, Miller Plateau Voltage, and QGD are known, the two switching periods are calculated and then added together for the total switching period: QGS 2 RGD RG Q RGD RG GD VCC VPLATEAU V VPlateau VCC TH 2 Q RGD RG QGD RGD RG TFALL GS 2 VPLATEAU VTH VPlateau 2 Where: VTH = MOSFET Threshold Voltage VPlateau = MOSFET Miller Plateau Voltage RGD = LX7302 Drive On Resistance RG = MOSFET Gate Resistance TRISE Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 22 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Application Example (Continued) Switching losses are calculated: T T PSW VIN I OUTDC FSW RISE FALL 2 To determine the conduction losses, use the following formula: RDSON (100°C) = 11mΩ VTH = 1.7V VPlateau = 3.2V QGS2 = 3.7nC QGD = 3.7nC RG = 1.3Ω RGD = 1.5Ω Using the BSC030N03LS FET as a Synchronous FET example, we use the following datasheet specification: PCOND D I OUTDC RDSON 2 Use the maximum specified RDSON of the MOSFET at 100°C. This number can be derived from the manufacturer’s graph of RDSON vs. Temperature. RDSON (100°C) = 6mΩ The total Control MOSFET’s power dissipation is the sum of the switching and conduction losses: First determine the power dissipation in the Synchronous FET. For this application we use 2 MOSFETs in parallel for a combined RDSON of 3.1mΩ: PCONTROL PCOND P SW PSYNC 1 D I OUTDC RDSON 2 1 0.098 252 3m As an example, assume the following: VIN = 12V VOUT = 1V Duty Cycle = 0.098 FSW = 215kHz Continuous Output Load = 25A 1.69W The power dissipation is spread across two FETs, which equals 0.85W each FET. Using the BSC057N03LS FET as a Control FET example, we use the following datasheet specifications: Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 23 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Application Example Next determine the losses in the Control FET. The total losses are the sum of the switching loss Using the example values, determine the switching and conduction loss: losses. First determine the switching time period: PCONTROL PCOND P SW 0.56 0.67 1.23W QGS 2 RGD RG Q RGD RG GD VCC VPLATEAU V VPlateau VCC TH 2 3.7 n 1.5 1.3 3.7 n 1.5 1.3 9.8ns 5.0 3.2 1.7 3.2 5.0 2 Q RGD RG QGD RGD RG TFALL GS 2 VPLATEAU VTH VPlateau 2 3.7n 1.5 1.3 3.7n 1.5 1.3 7.5ns 3.2 1.7 3.2 2 TRISE Vgs Qg VPlateau VTH Qgs1 Gate Charge Qgs2 Switching loss is determined: TRISE TFALL 2 12 25 215kHz 8.6ns 555mW Qgs PSW VIN I OUTDC FSW Qgd Figure 15. Gate Charge Definitions Next, determine conduction loss: 2 PCOND D I OUTDC RDSON 0.098 252 11m 674mW Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 24 LX7302 5V to 26V Synchronous Step Down DC-DC Controller Production Datasheet Package Dimensions QFN 3x3mm 20L Exposed Pad D b K D2 E e E2 L A A1 Dim A A1 A3 b D D2 e E E2 K L MILLIMETERS MIN MAX 0.70 0.80 0 0.05 0.20 REF 0.15 0.25 3.00 BSC 1.55 1.80 0.40 BSC 3.00 BSC 1.55 1.80 0.2 0.20 0.50 INCHES MIN MAX 0.027 0.031 0 0.002 0.008 REF 0.006 0.010 0.118 BSC 0.061 0.071 0.016 BSC 0.118 BSC 0.061 0.071 0.008 0.012 0.020 A3 Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2012 Rev. 1.0, 12/17/2012 Microsemi Analog Mixed Signal Group One Enterprise Aliso Viejo, CA 92656 USA, 1-800-713-4113, 949-380-6100, fax 949-215-4996 Page 25