TI DP83848QSQ/NOPB

DP83848Q
DP83848Q PHYTER Extended Temperature Single Port 10/100 Mb/s Ethernet
Physical Layer Transceiver
Literature Number: SNLS341A
DP83848Q
PHYTER Extended Temperature Single Port 10/100 Mb/s
Ethernet Physical Layer Transceiver
1.0 General Description
3.0 Features
The number of applications requiring Ethernet connectivity
continues to increase, driving Ethernet enabled devices into
harsher environments.
The DP83848Q was designed to meet the challenge of these
new applications with an extended temperature performance
that goes beyond the typical Industrial temperature range.
The DP83848Q is a highly reliable, feature rich, robust device
which meets IEEE 802.3u standards over an EXTENDED
temperature range of -40°C to 105°C. This device is ideally
suited for harsh environments such as automotive/transportation, wireless remote base stations,and industrial control applications.
It offers enhanced ESD protection and the choice of an MII or
RMII interface for maximum flexibility in MPU selection; all in
a 40 pin LLP package.
The DP83848Q extends the leadership position of the
PHYTER family of devices with a wide operating temperature
range. The National Semiconductor line of PHYTER
transceivers builds on decades of Ethernet expertise to offer
the high performance and flexibility that allows the end user
an easy implementation tailored to meet these application
needs.
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2.0 Applications
■ Automotive/Transportation
■ Industrial Controls and Factory Automation
■ General Embedded Applications
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AEC-Q100 Grade 2
Extreme Temperature from -40°C to 105°C
Low-power 3.3V, 0.18µm CMOS technology
Low power consumption <270mW Typical
3.3V MAC Interface
Auto-MDIX for 10/100 Mb/s
Energy Detection Mode
25 MHz clock out
RMII Rev. 1.2 Interface (configurable)
MII Serial Management Interface (MDC and MDIO)
IEEE 802.3u MII
IEEE 802.3u Auto-Negotiation and Parallel Detection
IEEE 802.3u ENDEC, 10BASE-T transceivers and filters
IEEE 802.3u PCS, 100BASE-TX transceivers and filters
IEEE 1149.1 JTAG
Integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander
compensation
Error-free Operation up to 150 meters
Programmable LED support for Link and Activity
Single register access for complete PHY status
10/100 Mb/s packet BIST (Built in Self Test)
Lead free 40-pin LLP package (6mm) x (6mm) ADC
4.0 System Diagram
30152551
PHYTER® is a registered trademark of National Semiconductor.
© 2011 National Semiconductor Corporation
301525
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DP83848Q PHYTER Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer
Transceiver
September 19, 2011
DP83848Q
4.0 Block Diagram
30152501
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1.0 General Description ......................................................................................................................... 1
2.0 Applications .................................................................................................................................... 1
3.0 Features ........................................................................................................................................ 1
4.0 System Diagram .............................................................................................................................. 1
4.0 Block Diagram ................................................................................................................................ 2
6.0 Pin Layout ...................................................................................................................................... 6
7.0 Pin Descriptions .............................................................................................................................. 7
7.1 SERIAL MANAGEMENT INTERFACE ........................................................................................ 7
7.2 MAC DATA INTERFACE ........................................................................................................... 7
7.3 CLOCK INTERFACE ................................................................................................................ 8
7.4 LED INTERFACE ..................................................................................................................... 9
7.5 RESET ................................................................................................................................... 9
7.6 STRAP OPTIONS .................................................................................................................. 10
7.7 10 Mb/s AND 100 Mb/s PMD INTERFACE ................................................................................ 11
7.8 SPECIAL CONNECTIONS ...................................................................................................... 11
7.9 POWER SUPPLY PINS .......................................................................................................... 11
7.10 PACKAGE PIN ASSIGNMENTS ............................................................................................. 12
8.0 Configuration ................................................................................................................................ 13
8.1 AUTO-NEGOTIATION ............................................................................................................ 13
8.1.1 Auto-Negotiation Pin Control .......................................................................................... 13
8.1.2 Auto-Negotiation Register Control ................................................................................... 13
8.1.3 Auto-Negotiation Parallel Detection ................................................................................. 13
8.1.4 Auto-Negotiation Restart ............................................................................................... 14
8.1.5 Enabling Auto-Negotiation via Software ........................................................................... 14
8.1.6 Auto-Negotiation Complete Time .................................................................................... 14
8.2 AUTO-MDIX .......................................................................................................................... 14
8.3 PHY ADDRESS ..................................................................................................................... 14
8.3.1 MII Isolate Mode ........................................................................................................... 14
8.4 LED INTERFACE ................................................................................................................... 15
8.4.1 LEDs .......................................................................................................................... 15
8.4.2 LED Direct Control ........................................................................................................ 16
8.5 HALF DUPLEX vs. FULL DUPLEX ........................................................................................... 16
8.6 INTERNAL LOOPBACK .......................................................................................................... 16
8.7 BIST ..................................................................................................................................... 16
9.0 Functional Description .................................................................................................................... 17
9.1 MII INTERFACE ..................................................................................................................... 17
9.1.1 Nibble-wide MII Data Interface ....................................................................................... 17
9.1.2 Collision Detect ............................................................................................................ 17
9.1.3 Carrier Sense .............................................................................................................. 17
9.2 REDUCED MII INTERFACE .................................................................................................... 17
9.3 802.3u MII SERIAL MANAGEMENT INTERFACE ...................................................................... 18
9.3.1 Serial Management Register Access ............................................................................... 18
9.3.2 Serial Management Access Protocol ............................................................................... 18
9.3.3 Serial Management Preamble Suppression ...................................................................... 19
10.0 Architecture ................................................................................................................................ 20
10.1 100BASE-TX TRANSMITTER ................................................................................................ 20
10.1.1 Code-group Encoding and Injection ............................................................................... 21
10.1.2 Scrambler .................................................................................................................. 21
10.1.3 NRZ to NRZI Encoder ................................................................................................. 22
10.1.4 Binary to MLT-3 Convertor ........................................................................................... 22
10.2 100BASE-TX RECEIVER ...................................................................................................... 22
10.2.1 Analog Front End ........................................................................................................ 22
10.2.2 Digital Signal Processor ............................................................................................... 22
10.2.2.1 Digital Adaptive Equalization and Gain Control ..................................................... 23
10.2.2.2 Base Line Wander Compensation ....................................................................... 24
10.2.3 Signal Detect ............................................................................................................. 25
10.2.4 MLT-3 to NRZI Decoder .............................................................................................. 25
10.2.5 NRZI to NRZ .............................................................................................................. 25
10.2.6 Serial to Parallel ......................................................................................................... 25
10.2.7 Descrambler .............................................................................................................. 25
10.2.8 Code-group Alignment ................................................................................................ 25
10.2.9 4B/5B Decoder ........................................................................................................... 25
10.2.10 100BASE-TX Link Integrity Monitor ............................................................................. 25
10.2.11 Bad SSD Detection ................................................................................................... 25
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DP83848Q
Table of Contents
DP83848Q
10.3 10BASE-T TRANSCEIVER MODULE .....................................................................................
10.3.1 Operational Modes .....................................................................................................
10.3.2 Smart Squelch ...........................................................................................................
10.3.3 Collision Detection and SQE ........................................................................................
10.3.4 Carrier Sense .............................................................................................................
10.3.5 Normal Link Pulse Detection/Generation ........................................................................
10.3.6 Jabber Function .........................................................................................................
10.3.7 Automatic Link Polarity Detection and Correction ............................................................
10.3.8 Transmit and Receive Filtering .....................................................................................
10.3.9 Transmitter ................................................................................................................
10.3.10 Receiver ..................................................................................................................
11.0 Design Guidelines .......................................................................................................................
11.1 TPI NETWORK CIRCUIT ......................................................................................................
11.2 ESD PROTECTION ..............................................................................................................
11.3 CLOCK IN (X1) REQUIREMENTS ..........................................................................................
11.4 POWER FEEDBACK CIRCUIT ..............................................................................................
11.5 ENERGY DETECT MODE .....................................................................................................
12.0 Reset Operation ..........................................................................................................................
12.1 HARDWARE RESET ............................................................................................................
12.2 SOFTWARE RESET .............................................................................................................
13.0 Register Block .............................................................................................................................
13.1 REGISTER DEFINITION .......................................................................................................
13.1.1 Basic Mode Control Register (BMCR) ............................................................................
13.1.2 Basic Mode Status Register (BMSR) .............................................................................
13.1.3 PHY Identifier Register #1 (PHYIDR1) ...........................................................................
13.1.4 PHY Identifier Register #2 (PHYIDR2) ...........................................................................
13.1.5 Auto-Negotiation Advertisement Register (ANAR) ...........................................................
13.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) .............................
13.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) ...............................
13.1.8 Auto-Negotiate Expansion Register (ANER) ...................................................................
13.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) ...............................................
13.2 EXTENDED REGISTERS ......................................................................................................
13.2.1 PHY Status Register (PHYSTS) ...................................................................................
13.2.2 False Carrier Sense Counter Register (FCSCR) .............................................................
13.2.3 Receiver Error Counter Register (RECR) .......................................................................
13.2.4 100 Mb/s PCS Configuration and Status Register (PCSR) ................................................
13.2.5 RMII and Bypass Register (RBR) ..................................................................................
13.2.6 LED Direct Control Register (LEDCR) ...........................................................................
13.2.7 PHY Control Register (PHYCR) ....................................................................................
13.2.8 10 Base-T Status/Control Register (10BTSCR) ...............................................................
13.2.9 CD Test and BIST Extensions Register (CDCTRL1) ........................................................
13.2.10 Energy Detect Control (EDCR) ...................................................................................
14.0 Absolute Maximum Ratings ...........................................................................................................
15.0 AC and DC Specifications .............................................................................................................
15.1 DC SPECIFICATIONS ..........................................................................................................
15.2 AC SPECIFICATIONS ..........................................................................................................
15.2.1 Power Up Timing ........................................................................................................
15.2.2 Reset Timing .............................................................................................................
15.2.3 MII Serial Management Timing .....................................................................................
15.2.4 100 Mb/s MII Transmit Timing ......................................................................................
15.2.5 100 Mb/s MII Receive Timing .......................................................................................
15.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing ................................
15.2.7 100BASE-TX Transmit Packet Deassertion Timing ..........................................................
15.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) ....................................................................
15.2.9 100BASE-TX Receive Packet Latency Timing ................................................................
15.2.10 100BASE-TX Receive Packet Deassertion Timing ........................................................
15.2.11 10 Mb/s MII Transmit Timing ......................................................................................
15.2.12 10 Mb/s MII Receive Timing .......................................................................................
15.2.13 10 Mb/s Serial Mode Transmit Timing ..........................................................................
15.2.14 10 Mb/s Serial Mode Receive Timing ..........................................................................
15.2.15 10BASE-T Transmit Timing (Start of Packet) ................................................................
15.2.16 10BASE-T Transmit Timing (End of Packet) .................................................................
15.2.17 10BASE-T Receive Timing (Start of Packet) .................................................................
15.2.18 10BASE-T Receive Timing (End of Packet) ..................................................................
15.2.19 10 Mb/s Heartbeat Timing .........................................................................................
15.2.20 10 Mb/s Jabber Timing .............................................................................................
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26
27
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28
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29
30
31
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32
35
36
37
38
38
38
39
40
41
41
42
42
44
44
45
45
46
46
47
49
49
51
51
51
53
53
54
55
55
56
56
57
57
58
58
59
59
60
60
61
61
62
62
63
63
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64
64
65
65
66
67
68
69
69
70
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DP83848Q
15.2.21 10BASE-T Normal Link Pulse Timing ...........................................................................
15.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing .............................................................
15.2.23 100BASE-TX Signal Detect Timing .............................................................................
15.2.24 100 Mb/s Internal Loopback Timing ............................................................................
15.2.25 10 Mb/s Internal Loopback Timing ..............................................................................
15.2.26 RMII Transmit Timing ...............................................................................................
15.2.27 RMII Receive Timing .................................................................................................
15.2.28 Isolation Timing ........................................................................................................
15.2.29 25 MHz_OUT Timing .................................................................................................
15.2.30 100 Mb/s X1 to TX_CLK Timing ..................................................................................
16.0 Physical Dimensions ....................................................................................................................
17.0 Ordering Information ....................................................................................................................
DP83848Q
6.0 Pin Layout
30152555
Top View
NS Package Number SQA40A
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The DP83848Q pins are classified into the following interface
categories (each interface is described in the sections that
follow):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• Reset
• Strap Options
• 10/100 Mb/s PMD Interface
• Special Connect Pins
• Power and Ground pins
Type: I
Type: O
Type: I/O
Type OD
Type: PD,PU
Type: S
Note: Strapping pin option. Please see Section Section 7.6 STRAP OPTIONS for strap definitions.
Input
Output
Input/Output
Open Drain
Internal Pulldown/Pullup
Strapping Pin (All strap pins have weak
internal pull-ups or pull-downs. If the default
strap value is to be changed then an external
2.2 kΩ resistor should be used. Please see
Section Section 7.6 STRAP OPTIONS for
details.)
7.1 SERIAL MANAGEMENT INTERFACE
Signal
Name
Type
Pin #
Description
MDC
I
25
MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/
output serial interface which may be asynchronous to transmit and receive clocks. The
maximum clock rate is 25 MHz with no minimum clock rate.
MDIO
I/O
24
MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
7.2 MAC DATA INTERFACE
Signal Name
Type
Pin #
Description
TX_CLK
O
2
MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10
Mb/s mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference
for both transmit and receive.
TX_EN
I, PD
3
MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD
[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
TXD_0
TXD_1
TXD_2
TXD_3
I
I, PD
4
5
6
7
MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous
to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous
to the 50 MHz reference clock.
RX_CLK
O
31
MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and
2.5 MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference
for both transmit and receive.
RX_DV
S, O, PD
32
MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid
indication independent of Carrier Sense.
RX_ER
S, O, PU
34
MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid
symbol has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is
detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required
to corrupt data on a receive error.
RXD_0
RXD_1
RXD_2
RXD_3
S, O, PD
36
37
38
39
MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK,
25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data
when RX_DV is asserted.
RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1
clock, 50 MHz.
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DP83848Q
All DP83848Q signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of
the I/O cells for each pin.
7.0 Pin Descriptions
DP83848Q
Signal Name
Type
Pin #
Description
CRS/
CRS_DV
S, O, PU
33
MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and
Receive Data Valid indications. For a detailed description of this signal, see the RMII
Specification.
COL
S, O, PU
35
MII COLLISION DETECT: Asserted high to indicate detection of a collision condition
(simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.
While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a
duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is
no heartbeat function during 10 Mb/s full duplex operation.
RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC
will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine
collision.
7.3 CLOCK INTERFACE
Signal Name
Type
Pin #
Description
X1
I
28
CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the
DP83848Q and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The
DP83848Q supports either an external crystal resonator connected across pins X1 and X2,
or an external CMOS-level oscillator source connected to pin X1 only.
RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode
and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.
X2
O
27
CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external
25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS
oscillator clock source is used.
25MHz_OUT
O
21
MII 25 MHz CLOCK OUTPUT: This pin provides a 25 MHz clock output to the system. This
allows other devices to use the reference clock without requiring additional clock sources.
RMII 50 MHz CLOCK OUTPUT: Tthis pin provides a 50 MHz clock output to the system.
For RMII mode, it is not recommended that the system clock out be used as the reference
clock to the MAC without first verifying the interface timing. See AN-1405 for more details.
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DP83848Q
7.4 LED INTERFACE
See Table 3 for LED Mode Selection.
Signal Name
LED_LINK
Type
Pin #
Description
S, O, PU
22
LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be
ON when Link is good.
LINK/ACT LED: In Mode 2, this pin indicates transmit and receive activity in
addition to the status of the Link. The LED will be ON when Link is good. It will
blink when the transmitter or receiver is active.
7.5 RESET
Signal Name
RESET_N
Type
Pin #
Description
I, PU
23
RESET: Active Low input that initializes or re-initializes the DP83848Q. Asserting
this pin low for at least 1 µs will force a reset process to occur. All internal registers
will re-initialize to their default states as specified for each bit in the Register Block
section. All strap options are re-initialized as well.
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DP83848Q
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is required, then there is no need for external pull-up or pull down
resistors. Since these pins may have alternate functions after
reset is deasserted, they should not be connected directly to
VCC or GND.
7.6 STRAP OPTIONS
The DP83848Q uses many of the functional pins as strap options. The values of these pins are sampled during reset and
used to strap the device into specific modes of operation. The
strap option pin assignments are defined below. The functional pin name is indicated in parentheses.
Type
Pin #
Description
PHYAD0 (COL)
PHYAD1 (RXD1_0)
PHYAD2 (RXD0_1)
PHYAD3 (RXD1_2)
PHYAD4 (RXD1_3)
Signal Name
S, O, PU
S, O, PD
35
36
37
38
39
PHY ADDRESS [4:0]: The DP83848Q provides five PHY address pins, the
state of which are latched into the PHYCTRL register at system HardwareReset.
The DP83848Q supports PHY Address strapping values 0 (<00000>)
through 31 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate
Mode. The Mll isolate mode must be selected by strapping Phy Address 0;
changing to Address 0 by register write will not put the Phy in the Mll isolate
mode. Please refer to section Section 8.3 PHY ADDRESS for additional
information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-up resistors.
AN_0 (LED_LINK)
S, O, PU
22
AN0: This input pin controls the advertised operating mode of the
DP83848Q according to the following table. The value on this pin is set by
connecting the input pin to GND (0) or VCC (1) through 2.2 kΩ resistors. This
pin should NEVER be connected directly to GND or VCC.
The value set at this input is latched into the DP83848Q at Hardware-Reset.
The float/pull-down status of this pin is latched into the Basic Mode Control
Register and the Auto_Negotiation Advertisement Register during
Hardware-Reset.
The default is 1 since the this pin has an internal pull-up.
AN0
MII_MODE (RX_DV)
S, O, PD
32
Advertised Mode
0
10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
1
10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
MII MODE SELECT: This strapping option determines the operating mode
of the MAC Data Interface. Default operation (No pull-ups) will enable normal
MII Mode of operation. Strapping MII_MODE high will cause the device to
be in the RMII mode of operation. Since the pin includes an internal pulldown, the default value is 0.
The following table details the configurations:
MII_MODE
MAC Interface Mode
0
MII Mode
1
RMII Mode
LED_CFG (CRS/CRS_DV)
S, O, PU
33
LED CONFIGURATION: This strapping option determines the mode of
operation of the LED pin. Default is Mode 1. Mode 1 and Mode 2 can be
controlled via the strap option. All modes are configurable via register
access.
See Table 3 for LED Mode Selection.
MDIX_EN (RX_ER)
S, O, PU
34
MDIX ENABLE: Default is to enable MDIX. This strapping option disables
Auto-MDIX. An external pull-down will disable Auto-MDIX mode.
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Signal Name
Type
Pin #
Description
TD-, TD+
I/O
14
15
Differential common driver transmit output (PMD Output Pair). These differential outputs
are automatically configured to either 10BASE-T or 100BASE-TX signaling.
IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3V bias for operation.
RD-, RD+
I/O
11
12
Differential receive input (PMD Input Pair). These differential inputs are automatically
configured to accept either 100BASE-TX or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3V bias for operation.
7.8 SPECIAL CONNECTIONS
Type
Pin #
Description
RBIAS
Signal Name
I
20
Bias Resistor Connection: A 4.87 kΩ 1% resistor should be connected from RBIAS to
GND.
PFBOUT
O
19
Power Feedback Output: Parallel caps, 10µF (Tantalum preferred) and 0.1µF, should
be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin
37). See Section Section 11.4 POWER FEEDBACK CIRCUIT for proper placement pin.
PFBIN1
PFBIN2
I
16
30
Power Feedback Input: These pins are fed with power from PFBOUT pin. A small
capacitor of 0.1µF should be connected close to each pin.
Note: Do not supply power to these pins other than from PFBOUT.
I/O
8, 9, 10
RESERVED
RESERVED: These pins must be left unconnected.
7.9 POWER SUPPLY PINS
Signal Name
IOVDD33
Pin #
1, 26
Description
I/O 3.3V Supply
IOGND
40
I/O Ground
DGND
29
Digital Ground
AVDD33
18
Analog 3.3V Supply
AGND
GNDPAD
13, 17
DAP
11
Analog Ground
No connect or connect to Ground
See (Note 1)
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DP83848Q
7.7 10 Mb/s AND 100 Mb/s PMD INTERFACE
DP83848Q
7.10 PACKAGE PIN ASSIGNMENTS
SQA40A Pin #
Pin Name
SQA40A Pin #
Pin Name
1
IO_VDD
22
LED_LINK/AN0
2
TX_CLK
23
RESET_N
3
TX_EN
24
MDIO
4
TXD_0
25
MDC
5
TXD_1
26
IOVDD33
6
TXD_2
27
X2
7
TXD_3
28
X1
8
RESERVED
29
DGND
9
RESERVED
30
PFBIN2
10
RESERVED
31
RX_CLK
11
RD -
32
RX_DV/MII_MODE
12
RD +
33
CRS/CRS_DV/LED_CFG
13
AGND
34
RX_ER/MDIX_EN
14
TD -
35
COL/PHYAD0
15
TD +
36
RXD_0/PHYAD1
16
PFBIN1
37
RXD_1/PHYAD2
17
AGND
38
RXD_2/PHYAD3
18
AVDD33
39
RXD_3/PHYAD4
19
PFBOUT
40
IOGND
20
RBIAS
21
25MHz_OUT
DAP
Note 1: Die Attach Pad (DAP) provides thermal dissipation. Connection to GND plane recommended.
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NC or GND
See (Note 1)
This section includes information on the various configuration
options available with the DP83848Q. The configuration options described below include:
— Auto-Negotiation
— PHY Address and LED
— Half Duplex vs. Full Duplex
— Isolate mode
— Loopback mode
— BIST
8.1 AUTO-NEGOTIATION
The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link
segment and automatically selecting the highest performance
mode of operation supported by both devices. Fast Link Pulse
(FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a
link segment. For further detail regarding Auto-Negotiation,
refer to Clause 28 of the IEEE 802.3u specification. The
DP83848Q supports four different Ethernet protocols (10 Mb/
s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex,
and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be
selected based on the advertised ability of the Link Partner.
The Auto-Negotiation function within the DP83848Q can be
controlled either by internal register access or by the use of
the AN0 pin.
8.1.1 Auto-Negotiation Pin Control
The state of AN0 determines the specific mode advertised by
the DP83848Q as given in Table 1. This pin allows configuration options to be selected without requiring internal register
access.
The state of AN0 upon power-up/reset, determines the state
of bits [8:5] of the ANAR register.
The Auto-Negotiation function selected at power-up or reset
can be changed at any time by writing to the Basic Mode
Control Register (BMCR) at address 0x00h.
TABLE 1. Auto-Negotiation Modes
AN0
0
1
Advertised Mode
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
8.1.3 Auto-Negotiation Parallel Detection
The DP83848Q supports the Parallel Detection function as
defined in the IEEE 802.3u specification. Parallel Detection
requires both the 10 Mb/s and 100 Mb/s receivers to monitor
the receive signal and report link status to the Auto-Negotiation function. Auto-Negotiation uses this information to configure the correct technology in the event that the Link Partner
does not support Auto-Negotiation but is transmitting link signals that the 100BASE-TX or 10BASE-T PMAs recognize as
valid link signals.
If the DP83848Q completes Auto-Negotiation as a result of
Parallel Detection, bits 5 and 7 within the ANLPAR register
will be set to reflect the mode of operation present in the Link
Partner. Note that bits 4:0 of the ANLPAR will also be set to
00001 based on a successful parallel detection to indicate a
valid 802.3 selector field. Software may determine that negotiation completed via Parallel Detection by reading a zero in
the Link Partner Auto-Negotiation Able bit once the Auto-Negotiation Complete bit is set. If configured for parallel detect
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
8.1.2 Auto-Negotiation Register Control
When Auto-Negotiation is enabled, the DP83848Q transmits
the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any
combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected.
Auto-Negotiation Priority Resolution:
1. 100BASE-TX Full Duplex (Highest Priority)
2. 100BASE-TX Half Duplex
3. 10BASE-T Full Duplex
4. 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control for enabling, disabling, and restarting the
Auto-Negotiation process. When Auto-Negotiation is disabled, the Speed Selection bit in the BMCR controls switching
13
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DP83848Q
between 10 Mb/s or 100 Mb/s operation, and the Duplex
Mode bit controls switching between full duplex operation and
half duplex operation. The Speed Selection and Duplex Mode
bits have no effect on the mode of operation when the AutoNegotiation Enable bit is set.
The Link Speed can be examined through the PHY Status
Register (PHYSTS) at address 10h after a Link is achieved.
The Basic Mode Status Register (BMSR) indicates the set of
available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83848Q
(only the 100BASE-T4 bit is not set since the DP83848Q does
not support that function).
The BMSR also provides status on:
• Whether or not Auto-Negotiation is complete
• Whether or not the Link Partner is advertising that a
remote fault has occurred
• Whether or not valid link has been established
• Support for Management Frame Preamble suppression
The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the
DP83848Q. All available abilities are transmitted by default,
but any ability can be suppressed by writing to the ANAR.
Updating the ANAR to suppress an ability is one way for a
management agent to change (restrict) the technology that is
used.
The Auto-Negotiation Link Partner Ability Register (ANLPAR)
at address 0x05h is used to receive the base link code word
as well as all next page code words during the negotiation.
Furthermore, the ANLPAR will be updated to either 0081h or
0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively.
The Auto-Negotiation Expansion Register (ANER) indicates
additional Auto-Negotiation status. The ANER provides status on:
• Whether or not a Parallel Detect Fault has occurred
• Whether or not the Link Partner supports the Next Page
function
• Whether or not the DP83848Q supports the Next Page
function
• Whether or not the current page being exchanged by AutoNegotiation has been received
• Whether or not the Link Partner supports Auto-Negotiation
8.0 Configuration
DP83848Q
mode and any condition other than a single good link occurs
then the parallel detect fault bit will be set.
TABLE 2. PHY Address Mapping
8.1.4 Auto-Negotiation Restart
Once Auto-Negotiation has completed, it may be restarted at
any time by setting bit 9 (Restart Auto-Negotiation) of the BMCR to one. If the mode configured by a successful AutoNegotiation loses a valid link, then the Auto-Negotiation
process will resume and attempt to determine the configuration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.
A renegotiation request from any entity, such as a management agent, will cause the DP83848Q to halt any transmit
data and link pulse activity until the break_link_timer expires
(~1500 ms). Consequently, the Link Partner will go into link
fail and normal Auto-Negotiation resumes. The DP83848Q
will resume Auto-Negotiation after the break_link_timer has
expired by issuing FLP (Fast Link Pulse) bursts.
PHYAD Function
RXD Function
42
PHYAD0
COL
43
PHYAD1
RXD_0
44
PHYAD2
RXD_1
45
PHYAD3
RXD_2
46
PHYAD4
RXD_3
The DP83848Q can be set to respond to any of 32 possible
PHY addresses via strap pins. The information is latched into
the PHYCR register (address 19h, bits [4:0]) at device powerup and hardware reset. The PHY Address pins are shared
with the RXD and COL pins. Each DP83848Q or port sharing
an MDIO bus in a system must have a unique physical address.
The DP83848Q supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). Strapping PHY Address 0
puts the part into Isolate Mode. It should also be noted that
selecting PHY Address 0 via an MDIO write to PHYCR will
not put the device in Isolate Mode. See Section Section 8.3.1
MII Isolate Mode for more information.
For further detail relating to the latch-in timing requirements
of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in Section Section 12.0 Reset Operation.
Since the PHYAD[0] pin has weak internal pull-up resistor and
PHYAD[4:1] pins have weak internal pull-down resistors, the
default setting for the PHY address is 00001 (0x01h).
Refer to Figure 1 for an example of a PHYAD connection to
external components. In this example, the PHYAD strapping
results in address 000101 (0x03h).
8.1.5 Enabling Auto-Negotiation via Software
It is important to note that if the DP83848Q has been initialized
upon power-up as a non-auto-negotiating device (forced
technology), and it is then required that Auto-Negotiation or
re-Auto-Negotiation be initiated via software, bit 12 (Auto-Negotiation Enable) of the Basic Mode Control Register (BMCR)
must first be cleared and then set for any Auto-Negotiation
function to take effect.
8.1.6 Auto-Negotiation Complete Time
Parallel detection and Auto-Negotiation take approximately
2-3 seconds to complete. In addition, Auto-Negotiation with
next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent.
Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation.
8.3.1 MII Isolate Mode
The DP83848Q can be put into MII Isolate mode by writing to
bit 10 of the BMCR register or by strapping in Physical Address 0. It should be noted that selecting Physical Address 0
via an MDIO write to PHYCR will not put the device in the MII
isolate mode.
When in the MII isolate mode, the DP83848Q does not respond to packet data present at TXD[3:0], TX_EN inputs and
presents a high impedance on the TX_CLK, RX_CLK,
RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in
Isolate mode, the DP83848Q will continue to respond to all
management transactions.
While in Isolate mode, the PMD output pair will not transmit
packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses.
The DP83848Q can Auto-Negotiate or parallel detect to a
specific technology depending on the receive signal at the
PMD input pair. A valid link can be established for the receiver
even when the DP83848Q is in Isolate mode.
8.2 AUTO-MDIX
When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair
for MDI/MDIX operation. The function uses a random seed to
control switching of the crossover circuitry. This implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications.
Auto-MDIX is enabled by default and can be configured via
strap or via PHYCR (19h) register, bits [15:14].
Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs. Forced crossover
can be achieved through the FORCE_MDIX bit, bit 14 of
PHYCR (19h) register.
Note: Auto-MDIX will not work in a forced mode of operation.
8.3 PHY ADDRESS
The 5 PHY address inputs pins are shared with the RXD[3:0]
pins and COL pin are shown below.
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Pin #
14
DP83848Q
30152502
FIGURE 1. PHYAD Strapping Example
CR) for the LEDs can also be selected through address 19h,
bits [6:5].
8.4 LED INTERFACE
The DP83848Q supports a configurable Light Emitting Diode
(LED) pin link and activity. The PHY Control Register (PHY-
See Table 3 for LED Mode selection.
TABLE 3. LED Mode Selection
Mode
LED_CFG (bit 5) or
(pin 33)
1
1
ON for Good Link
OFF for No Link
2
0
ON for Good Link
BLINK for Activity
The LED_LINK pin in Mode 1 indicates the link status of the
port. In 100BASE-T mode, link is established as a result of
input receive amplitude compliant with the TP-PMD specifications which will result in internal generation of signal detect.
A 10 Mb/s Link is established as a result of the reception of
at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the assertion
of LED_LINK. LED_LINK will deassert in accordance with the
Link Loss Timer as specified in the IEEE 802.3 specification.
The LED_LINK pin in Mode 1 will be OFF when no LINK is
present.
The LED_LINK pin in Mode 2 will be ON to indicate Link is
good and BLINK to indicate activity is present on activity.
Since the LED pin is also used as a strap option, the polarity
of the LED is dependent on whether the pin is pulled up or
down.
LED_LINK
Refer to Figure 2 for an example of an AN0 connection to
external components. In this example, the AN0 strapping results in Auto-Negotiation enabled with 10/100 Half/Full-Duplex advertised .
The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose pins.
8.4.1 LEDs
Since the Auto-Negotiation (AN) strap option shares the LED
output pin, the external components required for strapping
and LED usage must be considered in order to avoid contention.
Specifically, when the LED output is used to drive the LED
directly, the active state of the output driver is dependent on
the logic level sampled by the AN0 input upon power-up/reset.
For example, if the AN0 input is resistively pulled low then the
output will be configured as an active high driver. Conversely,
if the AN0 input is resistively pulled high, then the output will
be configured as an active low driver.
30152503
FIGURE 2. AN0 Strapping and LED Loading Example
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DP83848Q
8.4.2 LED Direct Control
The DP83848Q provides another option to directly control the
LED output through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access
to the LED.
8.6 INTERNAL LOOPBACK
The DP83848Q includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected
through bit 14 (Loopback) of the Basic Mode Control Register
(BMCR). Writing 1 to this bit enables MII transmit data to be
routed to the MII receive outputs. Loopback status may be
checked in bit 3 of the PHY Status Register (PHYSTS). While
in Loopback mode the data will not be transmitted onto the
media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting
the Loopback mode.
8.5 HALF DUPLEX vs. FULL DUPLEX
The DP83848Q supports both half and full duplex operation
at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex relies on the CSMA/CD protocol to handle collisions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to
maintain compliance with the IEEE 802.3 specification.
Since the DP83848Q is designed to support simultaneous
transmit and receive activity it is capable of supporting fullduplex switched applications with a throughput of up to 200
Mb/s per port when operating in either 100BASE-TX or
100BASE-FX. Because the CSMA/CD protocol does not apply to full-duplex operation, the DP83848Q disables its own
internal collision sensing and reporting functions and modifies
the behavior of Carrier Sense (CRS) such that it indicates only
receive activity. This allows a full-duplex capable MAC to operate properly.
All modes of operation (100BASE-TX, and 10BASE-T) can
run either half-duplex or full-duplex. Additionally, other than
CRS and Collision reporting, all remaining MII signaling remains the same regardless of the selected duplex mode.
It is important to understand that while Auto-Negotiation with
the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and half-duplex from a fixed
10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.3u specification, if a far-end link partner is
configured to a forced full duplex 100BASE-TX ability, the
parallel detection state machine in the partner would be unable to detect the full duplex capability of the far-end link
partner. This link segment would negotiate to a half duplex
100BASE-TX configuration (same scenario for 10 Mb/s).
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8.7 BIST
The DP83848Q incorporates an internal Built-in Self Test
(BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be utilized to test the integrity of the
transmit and receive data paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture.
The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous
stream of a pseudo random sequence. The user can select a
9 bit or 15 bit pseudo random sequence from the PSR_15 bit
in the PHY Control Register (PHYCR). The received data is
compared to the generated pseudo-random data by the BIST
Linear Feedback Shift Register (LFSR) to determine the BIST
pass/fail status.
The pass/fail status of the BIST is stored in the BIST status
bit in the PHYCR register. The status bit defaults to 0 (BIST
fail) and will transition on a successful comparison. If an error
(mis-compare) occurs, the status bit is latched and is cleared
upon a subsequent write to the Start/Stop bit.
For transmit VOD testing, the Packet BIST Continuous Mode
can be used to allow continuous data transmission, setting
BIST_CONT_MODE, bit 5, of CDCTRL1 (0x1Bh).
The number of BIST errors can be monitored through the
BIST Error Count in the CDCTRL1 (0x1Bh), bits [15:8].
16
The DP83848Q supports two modes of operation using the
MII interface pins. The options are defined in the following
sections and include:
— MII Mode
— RMII Mode
The modes of operation can be selected by strap options or
register control. For RMII mode, it is required to use the strap
option, since it requires a 50 MHz clock instead of the normal
25 MHz.
In each of these modes, the IEEE 802.3 serial management
interface is operational for device configuration and status.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gathering
of status, error information, and the determination of the type
and capabilities of the attached PHY(s).
9.1.3 Carrier Sense
Carrier Sense (CRS) is asserted due to receive activity, once
valid data is detected via the squelch function during
10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and two non-contiguous zeros are
detected on the line.
For 10 or 100 Mb/s Half Duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 or 100 Mb/s Full Duplex operation, CRS is asserted
only due to receive activity.
CRS is deasserted following an end of packet.
9.1 MII INTERFACE
The DP83848Q incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY devices
to a MAC in 10/100 Mb/s systems. This section describes the
nibble wide MII data interface.
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate data
transfer between the PHY and the upper layer (MAC).
9.2 REDUCED MII INTERFACE
The DP83848Q incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification
(rev1.2) from the RMII Consortium. This interface may be
used to connect PHY devices to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is
transferred 2-bits at a time using the 50 MHz RMII_REF clock
for both transmit and receive. The following pins are used in
RMII mode:
— TX_EN
— TXD[1:0]
— RX_ER (optional for MAC)
— CRS_DV
— RXD[1:0]
— X1 (RMII Reference clock is 50 MHz)
In addition, the RMII mode supplies an RX_DV signal which
allows for a simpler method of recovering receive data without
having to separate RX_DV from the CRS_DV indication. This
is especially useful for diagnostic testing where it may be desirable to externally loop Receive MII data directly to the
transmitter.
Since the reference clock operates at 10 times the data rate
for 10 Mb/s operation, transmit data is sampled every 10
clocks. Likewise, receive data will be generated every 10th
clock so that an attached device can sample the data every
10 clocks.
RMII mode requires a 50 MHz oscillator be connected to the
device X1 pin. A 50 MHz crystal is not supported.
To tolerate potential frequency differences between the 50
MHz reference clock and the recovered receive clock, the receive RMII function includes a programmable elasticity buffer.
The elasticity buffer is programmable to minimize propagation
delay based on expected packet size and clock accuracy.
This allows for supporting a range of packet sizes including
jumbo frames.
The elasticity buffer will force Frame Check Sequence errors
for packets which overrun or underrun the FIFO. Underrun
and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The following table indicates how to
program the elasticity buffer fifo (in 4-bit increments) based
on expected max packet size and clock accuracy. It assumes
both clocks (RMII Reference clock and far-end Transmitter
clock) have the same accuracy.
9.1.1 Nibble-wide MII Data Interface
Clause 22 of the IEEE 802.3u specification defines the Media
Independent Interface. This interface includes a dedicated
receive bus and a dedicated transmit bus. These two data
buses, along with various control and status signals, allow for
the simultaneous exchange of data between the DP83848Q
and the upper layer agent (MAC).
The receive interface consists of a nibble wide data bus RXD
[3:0], a receive error signal RX_ER, a receive data valid flag
RX_DV, and a receive clock RX_CLK for synchronous transfer of the data. The receive clock operates at either 2.5 MHz
to support 10 Mb/s operation modes or at 25 MHz to support
100 Mb/s operational modes.
The transmit interface consists of a nibble wide data bus TXD
[3:0], a transmit enable control signal TX_EN, and a transmit
clock TX_CLK which runs at either 2.5 MHz or 25 MHz.
Additionally, the MII includes the carrier sense signal CRS, as
well as a collision detect signal COL. The CRS signal asserts
to indicate the reception of data from the network or as a
function of transmit data in Half Duplex mode. The COL signal
asserts as an indication of a collision which can occur during
half-duplex operation when both a transmit and receive operation occur simultaneously.
9.1.2 Collision Detect
For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active
simultaneously. Collisions are reported by the COL signal on
the MII.
If the DP83848Q is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits
have been received while in the collision state. This prevents
a collision being reported incorrectly due to noise on the network. The COL signal remains set for the duration of the
collision.
If a collision occurs during a receive operation, it is immediately reported by the COL signal.
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DP83848Q
When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit
times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the
MII.
9.0 Functional Description
DP83848Q
TABLE 4. Supported Packet Sizes at +/-50ppm +/-100ppm For Each Clock
Start Threshold RBR[1:0]
Latency Tolerance
Recommended Packet Size
at +/- 50ppm
Recommended Packet Size
at +/- 100ppm
1 (4-bits)
2 bits
2,400 bytes
1,200 bytes
2 (8-bits)
6 bits
7,200 bytes
3,600 bytes
3 (12-bits)
10 bits
12,000 bytes
6,000 bytes
0 (16-bits)
14 bits
16,800 bytes
8,400 bytes
provided. In addition 32 MDC clock cycles should be used to
re-sync the device if an invalid start, opcode, or turnaround
bit is detected.
The DP83848Q waits until it has received this preamble sequence before responding to any other transaction. Once the
DP83848Q serial management port has been initialized no
further preamble sequencing is required until after a poweron/reset, invalid Start, invalid Opcode, or invalid turnaround
bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between the
Register Address field and the Data field. To avoid contention
during a read transaction, no device shall actively drive the
MDIO signal during the first bit of Turnaround. The addressed
DP83848Q drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 3
shows the timing relationship between MDC and the MDIO as
driven/received by the Station (STA) and the DP83848Q
(PHY) for a typical register read access.
For write transactions, the station management entity writes
data to the addressed DP83848Q thus eliminating the requirement for MDIO Turnaround. The Turnaround time is
filled by the management entity by inserting <10>. Figure 4
shows the timing relationship for a typical MII register write
access.
9.3 802.3u MII SERIAL MANAGEMENT INTERFACE
9.3.1 Serial Management Register Access
The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are accessible
through the management interface pins MDC and MDIO. The
DP83848Q implements all the required MII registers as well
as several optional registers. These registers are fully described in Section 13.0 Register Block. A description of the
serial management access protocol follows.
9.3.2 Serial Management Access Protocol
The serial control interface consists of two pins, Management
Data Clock (MDC) and Management Data Input/Output
(MDIO). MDC has a maximum clock rate of 25 MHz and no
minimum rate. The MDIO line is bi-directional and may be
shared by up to 32 devices. The MDIO frame format is shown
below in Table 5.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83848Q with a sequence that can be used to
establish synchronization. This preamble may be generated
either by driving MDIO high for 32 consecutive MDC clock
cycles, or by simply allowing the MDIO pull-up resistor to pull
the MDIO pin high during which time 32 MDC clock cycles are
TABLE 5. Typical MDIO Frame Format
MII Management Serial Protocol
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
30152504
FIGURE 3. Typical MDC/MDIO Read Operation
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DP83848Q
30152505
FIGURE 4. Typical MDC/MDIO Write Operation
quirement is generally met by the mandatory pull-up resistor
on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported.
While the DP83848Q requires an initial preamble sequence
of 32 bits for management initialization, it does not require a
full 32-bit sequence between each subsequent transaction. A
minimum of one idle bit between management transactions is
required as specified in the IEEE 802.3u specification.
9.3.3 Serial Management Preamble Suppression
The DP83848Q supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Register
(BMSR, address 01h.) If the station management entity (i.e.
MAC or other management controller) determines that all
PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity
need not generate preamble for each management transaction.
The DP83848Q requires a single initialization sequence of 32
bits of preamble following hardware/software reset. This re-
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DP83848Q
The block diagram in Figure 5. provides an overview of each
functional block within the 100BASE-TX transmit section.
The Transmitter section consists of the following functional
blocks:
— Code-group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The
DP83848Q implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Standard,
Clause 24.
10.0 Architecture
This section describes the operations within each transceiver
module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following:
— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 10BASE-T Transceiver Module
10.1 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, as provided by the MII, to a scrambled MLT-3 125 Mb/s serial data
stream. Because the 100BASE-TX TP-PMD is integrated, the
differential output pins, PMD Output Pair, can be directly routed to the magnetics.
30152506
FIGURE 5. 100BASE-TX Transmit Block Diagram
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DP83848Q
TABLE 6. 4B5B Code-Group Encoding/Decoding
DATA CODES
0
11110
0000
1
01001
0001
2
10100
0010
3
10101
0011
4
01010
0100
5
01011
0101
6
01110
0110
7
01111
0111
8
10010
1000
9
10011
1001
A
10110
1010
B
10111
1011
C
11010
1100
D
11011
1101
E
11100
1110
F
11101
1111
IDLE AND CONTROL CODES
H
00100
HALT code-group - Error code
I
11111
Inter-Packet IDLE - 0000 (Note 1)
J
11000
First Start of Packet - 0101 (Note 1)
K
10001
Second Start of Packet - 0101 (Note 1)
T
01101
First End of Packet - 0000 (Note 1)
R
00111
Second End of Packet - 0000 (Note 1)
INVALID CODES
V
00000
V
00001
V
00010
V
00011
V
00101
V
00110
V
01000
V
01100
Note 1: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.
10.1.1 Code-group Encoding and Injection
The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be
combined with packet data code-groups. Refer to Table 6 for
4B to 5B code-group mapping details.
The code-group encoder substitutes the first 8-bits of the
MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with
corresponding 5B code-groups. At the end of the transmit
packet, upon the deassertion of Transmit Enable signal from
the MAC, the code-group encoder injects the T/R code-group
pair (01101 00111) indicating the end of the frame.
After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the
next transmit packet is detected (reassertion of Transmit Enable).
10.1.2 Scrambler
The scrambler is required to control the radiated emissions at
the media connector and on the twisted pair cable (for
100BASE-TX applications). By scrambling the data, the total
energy launched onto the cable is randomly distributed over
a wide frequency range. Without the scrambler, energy levels
at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e.,
continuous transmission of IDLEs).
The scrambler is configured as a closed loop linear feedback
shift register (LFSR) with an 11-bit polynomial. The output of
the closed loop LFSR is X-ORd with the serial NRZ data from
the code-group encoder. The result is a scrambled data
stream with sufficient randomization to decrease radiated
emissions at certain frequencies by as much as 20 dB. The
DP83848Q uses the PHY_ID (pins PHYAD [4:1]) to set a
unique seed value.
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DP83848Q
See Figure 6 for a block diagram of the 100BASE-TX receive
function. This provides an overview of each functional block
within the 100BASE-TX receive section.
The Receive section consists of the following functional
blocks:
— Analog Front End
— Digital Signal Processor
— Signal Detect
— MLT-3 to Binary Decoder
— NRZI to NRZ Decoder
— Serial to Parallel
— Descrambler
— Code Group Alignment
— 4B/5B Decoder
— Link Integrity Monitor
— Bad SSD Detection
10.1.3 NRZ to NRZI Encoder
After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with
the TP-PMD standard for 100BASE-TX transmission over
Category-5 Unshielded twisted pair cable.
10.1.4 Binary to MLT-3 Convertor
The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased
logic one events. These two binary streams are then fed to
the twisted pair output driver which converts the voltage to
current and alternately drives either side of the transmit transformer primary winding, resulting in a MLT-3 signal.
The 100BASE-TX MLT-3 signal sourced by the PMD Output
Pair common driver is slew rate controlled. This should be
considered when selecting AC coupling magnetics to ensure
TP-PMD Standard compliant transition times (3 ns < Tr < 5
ns).
The 100BASE-TX transmit TP-PMD function within the
DP83848Q is capable of sourcing only MLT-3 encoded data.
Binary output from the PMD Output Pair is not possible in 100
Mb/s mode.
10.2.1 Analog Front End
In addition to the Digital Equalization and Gain Control, the
DP83848Q includes Analog Equalization and Gain Control in
the Analog Front End. The Analog Equalization reduces the
amount of Digital Equalization required in the DSP.
10.2 100BASE-TX RECEIVER
The 100BASE-TX receiver consists of several functional
blocks which convert the scrambled MLT-3 125 Mb/s serial
data stream to synchronous 4-bit nibble data that is provided
to the MII. Because the 100BASE-TX TP-PMD is integrated,
the differential input pins, RD±, can be directly routed from
the AC coupling magnetics.
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10.2.2 Digital Signal Processor
The Digital Signal Processor includes Adaptive Equalization
with Gain Control and Base Line Wander Compensation.
22
DP83848Q
30152507
FIGURE 6. 100BASE-TX Receive Block Diagram
sation or equalization must be adaptive to ensure proper
conditioning of the received signal independent of the cable
length.
The DP83848Q utilizes an extremely robust equalization
scheme referred as ‘Digital Adaptive Equalization.’
The Digital Equalizer removes ISI (inter symbol interference)
from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. Equalization is combined with an adaptive gain control
stage. This enables the receive 'eye pattern' to be opened
sufficiently to allow very reliable data recovery.
The curves given in Figure 8 illustrate attenuation at certain
frequencies for given cable lengths. This is derived from the
worst case frequency vs. attenuation figures as specified in
the EIA/TIA Bulletin TSB-36. These curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit.
10.2.2.1 Digital Adaptive Equalization and Gain Control
When transmitting data at high speeds over copper twisted
pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency
content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the
scrambled data stream. This variation in signal attenuation
caused by frequency variations must be compensated to ensure the integrity of the transmission.
In order to ensure quality transmission when employing
MLT-3 encoding, the compensation must be able to adapt to
various cable lengths and cable types depending on the installed environment. The selection of long cable lengths for a
given implementation, requires significant compensation
which will over-compensate for shorter, less attenuating
lengths. Conversely, the selection of short or intermediate
cable lengths requiring less compensation will cause serious
under-compensation for longer length cables. The compen-
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DP83848Q
30152508
FIGURE 7. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 Meters of CAT 5 Cable
10.2.2.2 Base Line Wander Compensation
30152509
FIGURE 8. 100BASE-TX BLW Event
The DP83848Q is completely ANSI TP-PMD compliant and
includes Base Line Wander (BLW) compensation. The BLW
compensation block can successfully recover the TP-PMD
defined “killer” pattern.
BLW can generally be defined as the change in the average
DC content, relatively short period over time, of an AC cou-
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pled digital transmission over a given transmission medium.
(i.e., copper wire).
BLW results from the interaction between the low frequency
components of a transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission system. If the low frequency content of the digital bit
stream goes below the low frequency pole of the AC coupling
24
10.2.8 Code-group Alignment
The code-group alignment module operates on unaligned 5bit data from the descrambler (or, if the descrambler is bypassed, directly from the NRZI/NRZ decoder) and converts it
into 5B code-group data (5 bits). Code-group alignment occurs after the J/K code-group pair is detected. Once the J/K
code-group pair (11000 10001) is detected, subsequent data
is aligned on a fixed boundary.
10.2.3 Signal Detect
The signal detect function of the DP83848Q is incorporated
to meet the specifications mandated by the ANSI FDDI TPPMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters.
Note that the reception of normal 10BASE-T link pulses and
fast link pulses per IEEE 802.3u Auto-Negotiation by the
100BASE-TX receiver do not cause the DP83848Q to assert
signal detect.
10.2.9 4B/5B Decoder
The code-group decoder functions as a look up table that
translates incoming 5B code-groups into 4B nibbles. The
code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC
preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B
code-groups are converted to the corresponding 4B nibbles
for the duration of the entire packet. This conversion ceases
upon the detection of the T/R code-group pair denoting the
End of Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
10.2.4 MLT-3 to NRZI Decoder
The DP83848Q decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data.
10.2.10 100BASE-TX Link Integrity Monitor
The 100 Base TX Link monitor ensures that a valid and stable
link is established before enabling both the Transmit and Receive PCS layer.
Signal detect must be valid for 395us to allow the link monitor
to enter the 'Link Up' state, and enable the transmit and receive functions.
10.2.5 NRZI to NRZ
In a typical application, the NRZI to NRZ decoder is required
in order to present NRZ formatted data to the descrambler.
10.2.6 Serial to Parallel
The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols to the PCS Rx
state machine.
10.2.11 Bad SSD Detection
A Bad Start of Stream Delimiter (Bad SSD) is any transition
from consecutive idle code-groups to non-idle code-groups
which is not prefixed by the code-group pair /J/K.
If this condition is detected, the DP83848Q will assert RX_ER
and present RXD[3:0] = 1110 to the MII for the cycles that
correspond to received 5B code-groups until at least two IDLE
code groups are detected. In addition, the False Carrier
Sense Counter register (FCSCR) will be incremented by one.
Once at least two IDLE code groups are detected, RX_ER
and CRS become de-asserted.
10.2.7 Descrambler
A serial descrambler is used to de-scramble the received NRZ
data. The descrambler has to generate an identical data
scrambling sequence (N) in order to recover the original unscrambled data (UD) from the scrambled data (SD) as represented in the equations:
30152553
10.3 10BASE-T TRANSCEIVER MODULE
The 10BASE-T Transceiver Module is IEEE 802.3 compliant.
It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the
standard. An external filter is not required on the 10BASE-T
interface since this is integrated inside the DP83848Q. This
section focuses on the general 10BASE-T system level operation.
Synchronization of the descrambler to the original scrambling
sequence (N) is achieved based on the knowledge that the
incoming scrambled data stream consists of scrambled IDLE
data. After the descrambler has recognized 12 consecutive
IDLE code-groups, where an unscrambled IDLE code-group
in 5B NRZ is equal to five consecutive ones (11111), it will
synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5B code-groups.
In order to maintain synchronization, the descrambler must
continuously monitor the validity of the unscrambled data that
it generates. To ensure this, a line state monitor and a hold
timer are used to constantly monitor the synchronization status. Upon synchronization of the descrambler the hold timer
starts a 722 µs countdown. Upon detection of sufficient IDLE
code-groups (58 bit times) within the 722 µs period, the hold
timer will reset and begin a new countdown. This monitoring
operation will continue indefinitely given a properly operating
network connection with good signal integrity. If the line state
monitor does not recognize sufficient unscrambled IDLE
code-groups within the 722 µs period, the entire descrambler
will be forced out of the current state of synchronization and
reset in order to re-acquire synchronization.
10.3.1 Operational Modes
The DP83848Q has two basic 10BASE-T operational modes:
— Half Duplex mode
— Full Duplex mode
Half Duplex Mode
In Half Duplex mode the DP83848Q functions as a standard
IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD
protocol.
Full Duplex Mode
In Full Duplex mode the DP83848Q is capable of simultaneously transmitting and receiving without asserting the collision
signal. The DP83848Q's 10 Mb/s ENDEC is designed to encode and decode simultaneously.
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DP83848Q
transformers then the droop characteristics of the transformers will dominate resulting in potentially serious BLW.
The digital oscilloscope plot provided in Figure 9 illustrates
the severity of the BLW event that can theoretically be generated during 100BASE-TX packet transmission. This event
consists of approximately 800 mV of DC offset for a period of
120 ms. Left uncompensated, events such as this can cause
packet loss.
DP83848Q
the opposite squelch level must then be exceeded within 150
ns. Finally the signal must again exceed the original squelch
level within 150 ns to ensure that the input waveform will not
be rejected. This checking procedure results in the loss of
typically three preamble bits at the beginning of each packet.
Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the
circuitry that valid data is present. At this time, the smart
squelch circuitry is reset.
Valid data is considered to be present until the squelch level
has not been generated for a time longer than 150 ns, indicating the End of Packet. Once good data has been detected,
the squelch levels are reduced to minimize the effect of noise
causing premature End of Packet detection.
10.3.2 Smart Squelch
The smart squelch is responsible for determining when valid
data is present on the differential receive inputs. The
DP83848Q implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be
mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode.
The squelch circuitry employs a combination of amplitude and
timing measurements (as specified in the IEEE 802.3 10BSET standard) to determine the validity of data on the twisted
pair inputs (refer to Figure 9).
The signal at the start of a packet is checked by the smart
squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be
rejected. Once this first squelch level is overcome correctly,
30152510
FIGURE 9. 10BASE-T Twisted Pair Smart Squelch Operation
10.3.3 Collision Detection and SQE
When in Half Duplex, a 10BASE-T collision is detected when
the receive and transmit channels are active simultaneously.
Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected.
The COL signal remains set for the duration of the collision.
If the PHY is receiving when a collision is detected it is reported immediately (through the COL pin).
When heartbeat is enabled, approximately 1 µs after the
transmission of each packet, a Signal Quality Error (SQE)
signal of approximately 10-bit times is generated to indicate
successful transmission. SQE is reported as a pulse on the
COL signal of the MII.
The SQE test is inhibited when the PHY is set in full duplex
mode. SQE can also be inhibited by setting the
HEARTBEAT_DIS bit in the 10BTSCR register.
10.3.5 Normal Link Pulse Detection/Generation
The link pulse generator produces pulses as defined in the
IEEE 802.3 10BASE-T standard. Each link pulse is nominally
100 ns in duration and transmitted every 16 ms in the absence
of transmit data.
Link pulses are used to check the integrity of the connection
with the remote end. If valid link pulses are not received, the
link detector disables the 10BASE-T twisted pair transmitter,
receiver and collision detection functions.
When the link integrity function is disabled (FORCE_LINK_10
of the 10BTSCR register), a good link is forced and the
10BASE-T transceiver will operate regardless of the presence of link pulses.
10.3.6 Jabber Function
The jabber function monitors the DP83848Q's output and disables the transmitter if it attempts to transmit a packet of
longer than legal size. A jabber timer monitors the transmitter
and disables the transmission if the transmitter is active for
approximately 85 ms.
Once disabled by the Jabber function, the transmitter stays
disabled for the entire time that the ENDEC module's internal
transmit enable is asserted. This signal has to be de-asserted
for approximately 500 ms (the “unjab” time) before the Jabber
function re-enables the transmit outputs.
The Jabber function is only relevant in 10BASE-T mode.
10.3.4 Carrier Sense
Carrier Sense (CRS) may be asserted due to receive activity
once valid data is detected via the squelch function.
For 10 Mb/s Half Duplex operation, CRS is asserted during
either packet transmission or reception.
For 10 Mb/s Full Duplex operation, CRS is asserted only during receive activity.
CRS is deasserted following an end of packet.
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26
harmonics in the transmit signal are attenuated by at least 30
dB.
10.3.8 Transmit and Receive Filtering
External 10BASE-T filters are not required when using the
DP83848Q, as the required signal conditioning is integrated
into the device.
Only isolation transformers and impedance matching resistors are required for the 10BASE-T transmit and receive
interface. The internal transmit filtering ensures that all the
10.3.10 Receiver
The decoder detects the end of a frame when no additional
mid-bit transitions are detected. Within one and a half bit times
after the last bit, carrier sense is de-asserted. Receive clock
stays active for five more bit times after CRS goes low, to
guarantee the receive timings of the controller.
10.3.9 Transmitter
The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data to pre-emphasized Manchester data for the transceiver. For the
duration of TX_EN, the serialized Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD
must be valid on the rising edge of Transmit Clock (TX_CLK).
Transmission ends when TX_EN deasserts. The last transition is always positive; it occurs at the center of the bit cell if
the last bit is a one, or at the end of the bit cell if the last bit is
a zero.
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DP83848Q
10.3.7 Automatic Link Polarity Detection and Correction
The DP83848Q's 10BASE-T transceiver module incorporates an automatic link polarity detection circuit. When three
consecutive inverted link pulses are received, bad polarity is
reported.
A polarity reversal can be caused by a wiring error at either
end of the cable, usually at the Main Distribution Frame (MDF)
or patch panel in the wiring closet.
The bad polarity condition is latched in the 10BTSCR register.
The DP83848Q's 10BASE-T transceiver module corrects for
this error internally and will continue to decode received data
correctly. This eliminates the need to correct the wiring error
immediately.
DP83848Q
that the application be tested to ensure that the circuit meets
the requirements of the intended application.
Pulse H1102
Pulse H2019
Pulse J0011D21
Pulse J0011D21B
11.0 Design Guidelines
11.1 TPI NETWORK CIRCUIT
Figure 10 shows the recommended circuit for a 10/100 Mb/s
twisted pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that
variations with PCB and component characteristics requires
30152511
FIGURE 10. 10/100 Mb/s Twisted Pair Interface
11.2 ESD PROTECTION
Typically, ESD precautions are predominantly in effect when
handling the devices or board before being installed in a system. In those cases, strict handling procedures need be implemented during the manufacturing process to greatly
reduce the occurrences of catastrophic ESD events. After the
system is assembled, internal components are less sensitive
from ESD events.
See section Section 15.0 AC and DC Specifications for ESD
rating.
Crystal
A 25 MHz, parallel, 20 pF load crystal resonator should be
used if a crystal source is desired. Figure 12 shows a typical
connection for a crystal resonator circuit. The load capacitor
values will vary with the crystal vendors; check with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel resonance
AT cut crystal with a minimum drive level of 100mW and a
maximum of 500 µW. If a crystal is specified for a lower drive
level, a current limiting resistor should be placed in series between X2 and the crystal.
As a starting point for evaluating an oscillator circuit, if the
requirements for the crystal are not known, CL1 and CL2
should be set at 33 pF, and R1 should be set at 0Ω.
Specification for 25 MHz crystal are listed in Table 9.
11.3 CLOCK IN (X1) REQUIREMENTS
The DP83848Q supports an external CMOS level oscillator
source or a crystal resonator device.
Oscillator
If an external clock source is used, X1 should be tied to the
clock source and X2 should be left floating.
Specifications for CMOS oscillators: 25 MHz in MII Mode and
50 MHz in RMII Mode are listed in Table 7 and Table 8.
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DP83848Q
30152512
FIGURE 11. Crystal Oscillator Circuit
TABLE 7. 25 MHz Oscillator Specification
Parameter
Min
Frequency
Typ
Max
25
Units
Condition
MHz
Frequency Tolerance
±50
ppm
Operational Temperature
Frequency Stability
Rise / Fall Time
±50
ppm
1 year aging
6
nsec
20% - 80%
Jitter
8001
psec
Short term
Jitter
8001
psec
Symmetry
40%
60%
Long term
Duty Cycle
1. This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to AN-1548,
“PHYTER 100 Base-TX Reference Clock Jitter Tolerance,” for details on jitter performance.
TABLE 8. 50 MHz Oscillator Specification
Parameter
Min
Frequency
Typ
Max
50
Units
Condition
MHz
Frequency Tolerance
±50
ppm
Operational Temperature
Frequency Stability
±50
ppm
Operational Temperature
Rise / Fall Time
6
nsec
20% - 80%
Jitter
8001
psec
Short term
Jitter
8001
psec
Long term
Symmetry
40%
60%
Duty Cycle
1. This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to AN-1548,
“PHYTER 100 Base-TX Reference Clock Jitter Tolerance,” for details on jitter performance.
TABLE 9. 25 MHz Crystal Specification
Parameter
Min
Frequency
Typ
Max
25
Units
Condition
MHz
Frequency Tolerance
±50
ppm
Operational Temperature
Frequency Stability
±50
ppm
1 year aging
40
pF
Load Capacitance
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11.4 POWER FEEDBACK CIRCUIT
To ensure correct operation for the DP83848Q, parallel caps
with values of 10 µF and 0.1 µF should be placed close to pin
23 (PFBOUT) of the device.
Pin 18(PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin
54 (PFBIN4) must be connected to pin 31 (PFBOUT), each
pin requires a small capacitor (.1 µF). See Figure 12 below
for proper connections.
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DP83848Q
11.5 ENERGY DETECT MODE
When Energy Detect is enabled and there is no activity on the
cable, the DP83848Q will remain in a low power mode while
monitoring the transmission line. Activity on the line will cause
the DP83848Q to go through a normal power up sequence.
Regardless of cable activity, the DP83848Q will occasionally
wake up the transmitter to put ED pulses on the line, but will
otherwise draw as little power as possible. Energy detect
functionality is controlled via register Energy Detect Control
(EDCR), address 0x1Dh.
30152513
FIGURE 12. Power Feedback Connection
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30
The DP83848Q includes an internal power-on reset (POR)
function and does not need to be explicitly reset for normal
operation after power up. If required during normal operation,
the device can be reset by a hardware or software reset.
12.1 HARDWARE RESET
A hardware reset is accomplished by applying a low pulse
(TTL level), with a duration of at least 1 µs, to the RESET_N
pin. This will reset the device such that all registers will be
reinitialized to default values and the hardware configuration
values will be re-latched into the device (similar to the powerup/reset operation).
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DP83848Q
12.2 SOFTWARE RESET
A software reset is accomplished by setting the reset bit (bit
15) of the Basic Mode Control Register (BMCR). The period
from the point in time when the reset bit is set to the point in
time when software reset has concluded is approximately
1 µs.
A software reset will reset the device such that all registers
will be reset to default values and the hardware configuration
values will be maintained. Software driver code must wait 3
µs following a software reset before allowing further serial MII
operations with the DP83848Q.
12.0 Reset Operation
DP83848Q
13.0 Register Block
TABLE 10. Register Map
Offset
Access
Tag
Description
Hex
Decimal
00h
0
RW
BMCR
Basic Mode Control Register
01h
1
RO
BMSR
Basic Mode Status Register
02h
2
RO
PHYIDR1
PHY Identifier Register #1
03h
3
RO
PHYIDR2
PHY Identifier Register #2
04h
4
RW
ANAR
Auto-Negotiation Advertisement Register
05h
5
RW
ANLPAR
Auto-Negotiation Link Partner Ability Register (Base Page)
05h
5
RW
ANLPARNP
Auto-Negotiation Link Partner Ability Register (Next Page)
06h
6
RW
ANER
Auto-Negotiation Expansion Register
07h
7
RW
ANNPTR
Auto-Negotiation Next Page TX
08h - Fh
8 - 15
RESERVED
RESERVED
Extended Registers
10h
16
RO
PHYSTS
PHY Status Register
11h - 13h
17 - 19
RO
RESERVED
RESERVED
14h
20
RO
FCSCR
False Carrier Sense Counter Register
15h
21
RO
RECR
Receive Error Counter Register
16h
22
RW
PCSR
PCS Sub-Layer Configuration and Status Register
17h
23
RW
RBR
RMII and Bypass Register
18h
24
RW
LEDCR
LED Direct Control Register
19h
25
RW
PHYCR
PHY Control Register
1Ah
26
RW
10BTSCR
10Base-T Status/Control Register
1Bh
27
RW
CDCTRL1
CD Test Control Register and BIST Extensions Register
1Ch
28
RW
RESERVED
RESERVED
1Dh
29
RW
EDCR
Energy Detect Control Register
1Eh - 1Fh
30 - 31
RW
RESERVED
RESERVED
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02h
03h
04h
05h
05h
PHY Identifier
Register 1
PHY Identifier
Register 2
Auto-Negotiation
Advertisement
Register
Auto-Negotiation
Link Partner Ability
Register (Base
Page)
Auto-Negotiation
Link Partner Ability
Register (Next
Page)
08-0fh
10h
11–13h
14h
15h
16h
17h
18h
19h
1Ah
RESERVED
PHY Status
Register
RESERVED
False Carrier
Sense Counter
Register
Receive Error
Counter Register
PCS Sub-Layer
Configuration and
Status Register
RMII and Bypass
Register
LED Direct Control
Register
PHY Control
Register
10Base-T Status/
Control Register
Reserved
Reserved
Reserved
Reserved
MDIX
mode
Reserved
Reserved
Reserved
ACK
ACK
Reserved
OUI LSB
OUI MSB
100BaseTX FDX
Loopback
Bit 14
MDIX_EN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Polarity
Status
Reserved
ACK2
Reserved
ACK2
Reserved
Reserved
OUI LSB
FREE_CL
K
Reserved
Reserved
Reserved
False
Carrier
Sense
Reserved
TOG_TX
Reserved
Toggle
ASM_DIR
ASM_DIR
OUI LSB
OUI MSB
HDX
OUI MSB
10Base-T
FDX
Power
Down
Bit 11
10Base-T
Auto-Neg
Enable
Bit 12
Reserved
Reserved
Reserved
PAUSE_T
X
Reserved
Bit 9
Bit 8
Reserved
CODE
Reserved
Code
T4
Reserved
CODE
Reserved
Code
TX_FD
TX_FD
MDL
T4
VNDR_
MDL
OUI MSB
Reserved
Duplex
Mode
VNDR_
OUI MSB
Reserved
Restart
Auto-Neg
PSR_15
Reserved
TX_SOUR
CE
TQ_EN
Reserved
Reserved
Reserved
Signal
Detect
SQUELCH
STATUS
BIST_
Reserved
TX_SOUR
CE
SD_FORC
E_PMA
Reserved
Reserved
Reserved
Descrambl
er Lock
LOOPBAC
K_10_DIS
BIST_STA
RT
Reserved
PMD_LOO
P
OPTION
SD_
Reserved
Reserved
Reserved
Receive
Page
EXTENDED REGISTERS
Reserved
CODE
Reserved
Code
PAUSE
PAUSE
OUI LSB
OUI MSB
Reserved
Isolate
Bit 10
TABLE 11. Register Table
SQUELCH SQUELCH
BIST_FE
Reserved
DIS_TX_O RX_PORT RX_PORT
PT
Reserved
Reserved
Reserved
Reserved
Rx Err
Latch
Reserved
Message
Page
Reserved
Message
Page
Remote
Fault
Remote
Fault
OUI LSB
OUI MSB
100BaseTX HDX
Speed
Selection
Bit 13
FORCE_M PAUSE_R
DIX
X
Reserved
SIM_WRIT Reserved
E
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Next Page
Ind
Reserved
Next Page
Ind
Next Page
Ind
Next Page
Ind
OUI LSB
OUI MSB
100BaseT4
Reset
Bit 15
10BT_SER Reserved
IAL
PHYCR
LEDCR
RBR
PCSR
RECR
FCSCR
Reserved
PHYSTS
Reserved
ANNPTR
Auto-Negotiation
Next Page TX
Register
07h
ANER
Auto-Negotiation
06h
Expansion Register
ANLPARN
P
ANLPAR
ANAR
PHYIDR2
PHYIDR1
BMSR
01h
Basic Mode Status
Register
Tag
BMCR
Addr
Basic Mode Control 00h
Register
Register Name
Bit 7
LP_DIS
BP_STRE
TCH
Reserved
SCMII_RX
DESC_TIM
E
RXERCNT
FCSCNT
Reserved
Reserved
Reserved
CODE
Reserved
Code
TX
TX
MDL
VNDR_
OUI MSB
Reserved
Collision
Test
Bit 6
LINK_10
FORCE_
Reserved
Reserved
SCMII_TX
FX_EN
RXERCNT
FCSCNT
Reserved
Remote
Fault
Reserved
CODE
Reserved
Code
10_FD
10_FD
MDL
VNDR_
OUI MSB
MF
Preamble
Suppress
Reserved
Bit 5
Reserved
CFG
LED_
Reserved
RMII_MOD
E
100_OK
FORCE_
RXERCNT
FCSCNT
Reserved
Jabber
Detect
Reserved
CODE
Reserved
Code
10
10
MDL
VNDR_
OUI MSB
Complete
Auto-Neg
Reserved
Bit 4
Bit 3
POLARITY
ADDR
PHY
DRV_LNKL
ED
Bit 2
FEFI_EN
RXERCNT
FCSCNT
Reserved
Loopback
Status
Reserved
CODE
Reserved
ADDR
PHY
Reserved
Reserved
ADDR
PHY
Reserved
RX_UNF_S
TS
BYPASS
NRZI_
RXERCNT
FCSCNT
Reserved
Duplex
Status
Reserved
CODE
NP_
ABLE
ABLE
Code
Protocol
Selection
Protocol
Selection
REV
MDL_
OUI MSB
Status
Link
Reserved
LP_NP_
Code
Protocol
Selection
Protocol
Selection
REV
MDL_
OUI MSB
Ability
Auto-Neg
Reserved
RMII_REV1 RX_OVF_S
_0
TS
Reserved
RXERCNT
FCSCNT
Reserved
Complete
Auto-Neg
Reserved
CODE
PDF
Code
Protocol
Selection
Protocol
Selection
MDL
VNDR_
OUI MSB
Remote
Fault
Reserved
Bit 1
HEARTBEA
T_DIS
ADDR
PHY
LNKLED
ELAST_BU
F
BYPASS
SCRAM_
RXERCNT
FCSCNT
Reserved
Speed
Status
Reserved
CODE
RX
PAGE_
Code
Protocol
Selection
Protocol
Selection
REV
MDL_
OUI MSB
Jabber
Detect
Reserved
Bit 0
JABBER_
DIS
ADDR
PHY
Reserved
ELAST_B
UF
SCRAM_
BYPASS
DE
RXERCN
T
FCSCNT
Reserved
Status
Link
Reserved
CODE
ABLE
LP_AN_
Code
Protocol
Selection
Protocol
Selection
REV
MDL_
OUI MSB
Extended
Capability
Reserved
DP83848Q
33
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34
Addr
1Bh
1Ch
1Dh
1Eh-1Fh
Register Name
CD Test Control
and BIST
Extensions
Register
RESERVED
Energy Detect
Control Register
RESERVED
Reserved
EDCR
Reserved
CDCTRL1
Tag
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Reserved
ED_EN
Reserved
Reserved
Reserved
Reserved
ED_AUTO ED_AUTO
_UP
_DOWN
Reserved
Reserved
ED_MAN
Reserved
Reserved
Reserved
Reserved
ED_BURS ED_PWR_
T_DIS
STATE
Reserved
Reserved
ED_ERR_
MET
Reserved
Reserved
ED_DATA
_MET
Reserved
BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR BIST_ERR
OR_COU OR_COU OR_COU
OR_COU OR_COU OR_COUN OR_COUN OR_COUN
NT
NT
NT
NT
NT
T
T
T
Bit 15
Bit 7
Reserved
ED_ERR_
COUNT
Reserved
Reserved
Bit 6
Reserved
ED_ERR_
COUNT
Reserved
Reserved
Bit 5
Reserved
ED_ERR_C
OUNT
Reserved
BIST_CON
T_MODE
Bit 4
Bit 3
Reserved
Reserved
Reserved
Reserved
ED_ERR_C ED_DATA_
OUNT
COUNT
Reserved
CDPattEN_
10
Bit 2
Reserved
ED_DATA_
COUNT
Reserved
10Meg_Pat
t_Gap
Reserved
ED_DATA_
COUNT
Reserved
CDPattSel
Bit 1
Reserved
ED_DATA
_COUNT
Reserved
CDPattSel
Bit 0
DP83848Q
DP83848Q
13.1 REGISTER DEFINITION
In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW = Read Write access
— SC = Register sets on event occurrence and Self-Clears when event ends
— RW/SC = ReadW rite access/Self Clearing bit
— RO = Read Only access
— COR = Clear On Read
— RO/COR = Read Only, Clear On Read
— RO/P = Read Only, Permanently set to a default value
— LL = Latched Low and held until read, based upon the occurrence of the corresponding event
— LH = Latched High and held until read, based upon the occurrence of the corresponding event
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DP83848Q
13.1.1 Basic Mode Control Register (BMCR)
TABLE 12. Basic Mode Control Register (BMCR), address 0x00h
Bit
Bit Name
Default
15
RESET
0, RW/SC
14
LOOPBACK
0, RW
13
SPEED SELECTION
Strap, RW
Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be
selected.
1 = 100 Mb/s.
0 = 10 Mb/s.
12
AUTO-NEGOTIATION
ENABLE
Strap, RW
Auto-Negotiation Enable:
Strap controls initial value at reset.
If FX is enabled (FX_EN = 1), then this bit will be reset to 0.
1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit
is set.
0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex
mode.
11
POWER DOWN
0, RW
Power Down:
1 = Power down.
0 = Normal operation.
Setting this bit powers down the PHY. Only the register block is enabled during a
power down condition.
10
ISOLATE
0, RW
Isolate:
1 = Isolates the Port from the MII with the exception of the serial management.
0 = Normal operation.
9
RESTART
AUTO-NEGOTIATION
0, RW/SC
Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will
return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear.
Operation of the Auto-Negotiation process is not affected by the management entity
clearing this bit.
0 = Normal operation.
8
DUPLEX MODE
Strap, RW
Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability
to be selected.
1 = Full Duplex operation.
0 = Half Duplex operation.
7
COLLISION TEST
0, RW
Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response to the assertion
of TX_EN within 512-bit times. The COL signal will be de-asserted within 4-bit times
in response to the de-assertion of TX_EN.
6:0
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
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Description
Reset:
1 = Initiate software Reset / Reset in Process.
0 = Normal operation.
This bit, which is self-clearing, returns a value of one until the reset process is
complete. The configuration is re-strapped.
Loopback:
1 = Loopback enabled.
0 = Normal operation.
The loopback function enables MII transmit data to be routed to the MII receive data
path.
Setting this bit may cause the descrambler to lose synchronization and produce a 500
µs “dead time” before any valid data will appear at the MII receive outputs.
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DP83848Q
13.1.2 Basic Mode Status Register (BMSR)
TABLE 13. Basic Mode Status Register (BMSR), address 0x01h
Bit
Bit Name
Default
15
100BASE-T4
0, RO/P
100BASE-T4 Capable:
0 = Device not able to perform 100BASE-T4 mode.
Description
14
100BASE-TX
FULL DUPLEX
1, RO/P
100BASE-TX Full Duplex Capable:
1 = Device able to perform 100BASE-TX in full duplex mode.
13
100BASE-TX
HALF DUPLEX
1, RO/P
100BASE-TX Half Duplex Capable:
1 = Device able to perform 100BASE-TX in half duplex mode.
12
10BASE-T
FULL DUPLEX
1, RO/P
10BASE-T Full Duplex Capable:
1 = Device able to perform 10BASE-T in full duplex mode.
11
10BASE-T
HALF DUPLEX
1, RO/P
10BASE-T Half Duplex Capable:
1 = Device able to perform 10BASE-T in half duplex mode.
10:7
RESERVED
0, RO
6
MF PREAMBLE
SUPPRESSION
1, RO/P
5
AUTO-NEGOTIATION
COMPLETE
0, RO
4
REMOTE FAULT
0, RO/LH
3
AUTO-NEGOTIATION
ABILITY
1, RO/P
Auto Negotiation Ability:
1 = Device is able to perform Auto-Negotiation.
0 = Device is not able to perform Auto-Negotiation.
2
LINK STATUS
0, RO/LL
Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
The criteria for link validity is implementation specific. The occurrence of a link failure
condition will causes the Link Status bit to clear. Once cleared, this bit may only be set
by establishing a good link condition and a read via the management interface.
1
JABBER DETECT
0, RO/LH
Jabber Detect: This bit only has meaning in 10 Mb/s mode.
1 = Jabber condition detected.
0 = No Jabber.
This bit is implemented with a latching function, such that the occurrence of a jabber
condition causes it to set until it is cleared by a read to this register by the management
interface or by a reset.
0
EXTENDED
CAPABILITY
1, RO/P
RESERVED: Write as 0, read as 0.
Preamble suppression Capable:
1 = Device able to perform management transaction with preamble suppressed, 32-bits
of preamble needed only once after reset, invalid opcode or invalid turnaround.
0 = Normal management operation.
Auto-Negotiation Complete:
1 = Auto-Negotiation process complete.
0 = Auto-Negotiation process not complete.
Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far
End Fault Indication or notification from Link Partner of Remote Fault.
0 = No remote fault condition detected.
Extended Capability:
1 = Extended register capabilities.
0 = Basic register set capabilities only.
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DP83848Q
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848Q. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may
return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network
management. National's IEEE assigned OUI is 080017h.
13.1.3 PHY Identifier Register #1 (PHYIDR1)
TABLE 14. PHY Identifier Register #1 (PHYIDR1), address 0x02h
Bit
Bit Name
Default
Description
15:0
OUI_MSB
<0010 0000 0000
0000>, RO/P
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored in bits 15
to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE
standard refers to these as bits 1 and 2).
13.1.4 PHY Identifier Register #2 (PHYIDR2)
TABLE 15. PHY Identifier Register #2 (PHYIDR2), address 0x03h
Bit
Bit Name
15:10
OUI_LSB
Default
9:4
VNDR_MDL
3:0
MDL_REV
Description
<0101 11>, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register
respectively.
<00 1010>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit
to bit 9).
<0010>, RO/P
Model Revision Number:
Four bits of the vendor model revision number are mapped from bits 3 to 0 (most
significant bit to bit 3). This field will be incremented for all major device changes.
13.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation.
TABLE 16. Negotiation Advertisement Register (ANAR), address 0x04h
Bit
Bit Name
Default
15
NP
0, RW
14
RESERVED
0, RO/P
13
RF
0, RW
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12
RESERVED
0, RW
RESERVED for Future IEEE use: Write as 0, Read as 0
11
ASM_DIR
0, RW
Asymmetric PAUSE Support for Full Duplex Links:
The ASM_DIR bit indicates that asymmetric PAUSE is supported.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B,
Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in
PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the optional MAC
control sublayer and the pause function as specified in clause 31 and annex 31B
of 802.3u.
0= No MAC based full duplex flow control.
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Description
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
RESERVED by IEEE: Writes ignored, read as 0.
38
Bit Name
Default
Description
10
PAUSE
0, RW
PAUSE Support for Full Duplex Links:
The PAUSE bit indicates that the device is capable of providing the symmetric
PAUSE functions as defined in Annex 31B.
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B,
Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in
PHYCR[13:12].
1 = Advertise that the DTE (MAC) has implemented both the optional MAC
control sublayer and the pause function as specified in clause 31 and annex 31B
of 802.3u.
0= No MAC based full duplex flow control.
9
T4
0, RO/P
8
TX_FD
Strap, RW
100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device.
0 = 100BASE-TX Full Duplex not supported.
7
TX
Strap, RW
100BASE-TX Support:
1 = 100BASE-TX is supported by the local device.
0 = 100BASE-TX not supported.
6
10_FD
Strap, RW
10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the local device.
0 = 10BASE-T Full Duplex not supported.
5
10
Strap, RW
10BASE-T Support:
1 = 10BASE-T is supported by the local device.
0 = 10BASE-T not supported.
4:0
SELECTOR
<00001>, RW
100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device.
0 = 100BASE-T4 not supported.
Protocol Selection Bits:
These bits contain the binary encoded protocol selector supported by this port.
<00001> indicates that this device supports IEEE 802.3u.
13.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after
the successful auto-negotiation if Next-pages are supported.
TABLE 17. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05h
Bit
Bit Name
Default
15
NP
0, RO
Next Page Indication:
0 = Link Partner does not desire Next Page Transfer.
1 = Link Partner desires Next Page Transfer.
Description
14
ACK
0, RO
Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Auto-Negotiation state machine will automatically control the this bit based on
the incoming FLP bursts.
13
RF
0, RO
Remote Fault:
1 = Remote Fault indicated by Link Partner.
0 = No Remote Fault indicated by Link Partner.
12
RESERVED
0, RO
RESERVED for Future IEEE use:
Write as 0, read as 0.
11
ASM_DIR
0, RO
ASYMMETRIC PAUSE:
1 = Asymmetric pause is supported by the Link Partner.
0 = Asymmetric pause is not supported by the Link Partner.
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DP83848Q
Bit
DP83848Q
Bit
Bit Name
Default
Description
10
PAUSE
0, RO
PAUSE:
1 = Pause function is supported by the Link Partner.
0 = Pause function is not supported by the Link Partner.
9
T4
0, RO
100BASE-T4 Support:
1 = 100BASE-T4 is supported by the Link Partner.
0 = 100BASE-T4 not supported by the Link Partner.
8
TX_FD
0, RO
100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the Link Partner.
0 = 100BASE-TX Full Duplex not supported by the Link Partner.
7
TX
0, RO
100BASE-TX Support:
1 = 100BASE-TX is supported by the Link Partner.
0 = 100BASE-TX not supported by the Link Partner.
6
10_FD
0, RO
10BASE-T Full Duplex Support:
1 = 10BASE-T Full Duplex is supported by the Link Partner.
0 = 10BASE-T Full Duplex not supported by the Link Partner.
5
10
0, RO
10BASE-T Support:
1 = 10BASE-T is supported by the Link Partner.
0 = 10BASE-T not supported by the Link Partner.
4:0
SELECTOR
<0 0000>, RO
Protocol Selection Bits:
Link Partners binary encoded protocol selector.
13.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page)
TABLE 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05h
Bit
Bit Name
Default
15
NP
0, RO
Next Page Indication:
1 = Link Partner desires Next Page Transfer.
0 = Link Partner does not desire Next Page Transfer.
14
ACK
0, RO
Acknowledge:
1 = Link Partner acknowledges reception of the ability data word.
0 = Not acknowledged.
The Auto-Negotiation state machine will automatically control the this bit based on
the incoming FLP bursts. Software should not attempt to write to this bit.
13
MP
0, RO
Message Page:
1 = Message Page.
0 = Unformatted Page.
12
ACK2
0, RO
Acknowledge 2:
1 = Link Partner does have the ability to comply to next page message.
0 = Link Partner does not have the ability to comply to next page message.
11
TOGGLE
0, RO
Toggle:
1 = Previous value of the transmitted Link Code word equalled 0.
0 = Previous value of the transmitted Link Code word equalled 1.
10:0
CODE
<000 0000 0000>,
RO
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Description
Code:
This field represents the code field of the next page transmission. If the MP bit is
set (bit 13 of this register), then the code shall be interpreted as a Message Page,
as defined in annex 28C of Clause 28. Otherwise, the code shall be interpreted as
an Unformatted Page, and the interpretation is application specific.
40
DP83848Q
13.1.8 Auto-Negotiate Expansion Register (ANER)
This register contains additional Local Device and Link Partner status information.
TABLE 19. Auto-Negotiate Expansion Register (ANER), address 0x06h
Bit
Bit Name
Default
Description
15:5
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
4
PDF
0, RO
Parallel Detection Fault:
1 = A fault has been detected via the Parallel Detection function.
0 = A fault has not been detected.
3
LP_NP_ABLE
0, RO
Link Partner Next Page Able:
1 = Link Partner does support Next Page.
0 = Link Partner does not support Next Page.
2
NP_ABLE
1, RO/P
1
PAGE_RX
0, RO/COR
0
LP_AN_ABLE
0, RO
Next Page Able:
1 = Indicates local device is able to send additional Next Pages.
Link Code Word Page Received:
1 = Link Code Word has been received, cleared on a read.
0 = Link Code Word has not been received.
Link Partner Auto-Negotiation Able:
1 = indicates that the Link Partner supports Auto-Negotiation.
0 = indicates that the Link Partner does not support Auto-Negotiation.
13.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR)
This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.
TABLE 20. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07h
Bit
Bit Name
Default
15
NP
0, RW
Next Page Indication:
0 = No other Next Page Transfer desired.
1 = Another Next Page desired.
Description
14
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
13
MP
1, RW
Message Page:
1 = Message Page.
0 = Unformatted Page.
12
ACK2
0, RW
Acknowledge2:
1 = Will comply with message.
0 = Cannot comply with message.
Acknowledge2 is used by the next page function to indicate that Local Device
has the ability to comply with the message received.
11
TOG_TX
0, RO
Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word was 0.
0 = Value of toggle bit in previously transmitted Link Code Word was 1.
Toggle is used by the Arbitration function within Auto-Negotiation to ensure
synchronization with the Link Partner during Next Page exchange. This bit shall
always take the opposite value of the Toggle bit in the previously exchanged
Link Code Word.
10:0
CODE
<000 0000 0001>, RW Code:
This field represents the code field of the next page transmission. If the MP bit
is set (bit 13 of this register), then the code shall be interpreted as a "Message
Page”, as defined in annex 28C of IEEE 802.3u. Otherwise, the code shall be
interpreted as an "Unformatted Page”, and the interpretation is application
specific.
The default value of the CODE represents a Null Page as defined in Annex 28C
of IEEE 802.3u.
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DP83848Q
13.2 EXTENDED REGISTERS
13.2.1 PHY Status Register (PHYSTS)
This register provides a single location within the register set for quick access to commonly accessed information.
TABLE 21. PHY Status Register (PHYSTS), address 10h
Bit
Bit Name
Default
15
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
14
MDIX MODE
0, RO
MDIX mode as reported by the Auto-Negotiation logic:
This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX
bits in the PHYCR register. When MDIX is enabled, but not forced, this bit will
update dynamically as the Auto-MDIX algorithm swaps between MDI and
MDIX configurations.
1 = MDI pairs swapped
(Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal
(Receive on TRD pair, Transmit on TPTD pair)
13
RECEIVE ERROR
LATCH
0, RO/LH
Receive Error Latch:
This bit will be cleared upon a read of the RECR register.
1 = Receive error event has occurred since last read of RXERCNT (address
15h, Page 0).
0 = No receive error event has occurred.
12
POLARITY STATUS
0, RO
Polarity Status:
This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared
upon a read of the 10BTSCR register, but not upon a read of the PHYSTS
register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
11
FALSE CARRIER
SENSE LATCH
0, RO/LH
False Carrier Sense Latch:
This bit will be cleared upon a read of the FCSR register.
1 = False Carrier event has occurred since last read of FCSCR (address 14h).
0 = No False Carrier event has occurred.
10
SIGNAL DETECT
0, RO/LL
100Base-TX qualified Signal Detect from PMA:
This is the SD that goes into the link monitor. It is the AND of raw SD and
descrambler lock, when address 16h, bit 8 (page 0) is set. When this bit is
cleared, it will be equivalent to the raw SD from the PMD.
9
DESCRAMBLER LOCK
0, RO/LL
100Base-TX Descrambler Lock from PMD.
8
PAGE RECEIVED
0, RO
Link Code Word Page Received:
This is a duplicate of the Page Received bit in the ANER register, but this bit
will not be cleared upon a read of the PHYSTS register.
1 = A new Link Code Word Page has been received. Cleared on read of the
ANER (address 06h, bit 1).
0 = Link Code Word Page has not been received.
7
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
6
REMOTE FAULT
0, RO
Remote Fault:
1 = Remote Fault condition detected (cleared on read of BMSR (address 01h)
register or by reset). Fault criteria: notification from Link Partner of Remote
Fault via Auto-Negotiation.
0 = No remote fault condition detected.
5
JABBER DETECT
0, RO
Jabber Detect: This bit only has meaning in 10 Mb/s mode.
This bit is a duplicate of the Jabber Detect bit in the BMSR register, except
that it is not cleared upon a read of the PHYSTS register.
1 = Jabber condition detected.
0 = No Jabber.
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Description
42
DP83848Q
Bit
Bit Name
Default
Description
4
AUTO-NEG COMPLETE
0, RO
Auto-Negotiation Complete:
1 = Auto-Negotiation complete.
0 = Auto-Negotiation not complete.
3
LOOPBACK STATUS
0, RO
Loopback:
1 = Loopback enabled.
0 = Normal operation.
2
DUPLEX STATUS
0, RO
Duplex:
This bit indicates duplex status and is determined from Auto-Negotiation or
Forced Modes.
1 = Full duplex mode.
0 = Half duplex mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
1
SPEED STATUS
0, RO
Speed10:
This bit indicates the status of the speed and is determined from AutoNegotiation or Forced Modes.
1 = 10 Mb/s mode.
0 = 100 Mb/s mode.
Note: This bit is only valid if Auto-Negotiation is enabled and complete and
there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
0
LINK STATUS
0, RO
Link Status:
This bit is a duplicate of the Link Status bit in the BMSR register, except that
it will not be cleared upon a read of the PHYSTS register.
1 = Valid link established (for either 10 or 100 Mb/s operation).
0 = Link not established.
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DP83848Q
13.2.2 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of
Clause 30 of the IEEE 802.3u specification.
TABLE 22. False Carrier Sense Counter Register (FCSCR), address 0x14h
Bit
Bit Name
Default
15:8
RESERVED
0, RO
7:0
FCSCNT[7:0]
0, RO/COR
Description
RESERVED: Writes ignored, read as 0
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter sticks
when it reaches its max count (FFh).
13.2.3 Receiver Error Counter Register (RECR)
This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY managed object
class of Clause 30 of the IEEE 802.3u specification.
TABLE 23. Receiver Error Counter Register (RECR), address 0x15h
Bit
Bit Name
Default
15:8
RESERVED
0, RO
7:0
RXERCNT[7:0]
0, RO/COR
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Description
RESERVED: Writes ignored, read as 0.
RX_ER Counter:
When a valid carrier is present and there is at least one occurrence of an invalid
data symbol, this 8-bit counter increments for each receive error detected. This
event can increment only once per valid carrier event. If a collision is present, the
attribute will not increment. The counter sticks when it reaches its max count.
44
DP83848Q
13.2.4 100 Mb/s PCS Configuration and Status Register (PCSR)
This register contains control and status information for the 100BASE Physical Coding Sublayer.
TABLE 24. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16h
Bit
Bit Name
Default
Description
15:13
RESERVED
<00>, RO
12
RESERVED
0
11
FREE_CLK
0, RW
Receive Clock:
10
TQ_EN
0, RW
100Mbs True Quiet Mode Enable:
1 = Transmit True Quiet Mode.
0 = Normal Transmit Mode.
9
SD FORCE PMA
0, RW
Signal Detect Force PMA:
1 = Forces Signal Detection in PMA.
0 = Normal SD operation.
8
SD_OPTION
1, RW
Signal Detect Option:
1 = Default operation. Link will be asserted following detection of valid signal level
and Descrambler Lock. Link will be maintained as long as signal level is valid. A
loss of Descrambler Lock will not cause Link Status to drop.
0 = Modified signal detect algorithm. Link will be asserted following detection of
valid signal level and Descrambler Lock. Link will be maintained as long as signal
level is valid and Descrambler remains locked.
7
DESC_TIME
0, RW
Descrambler Timeout:
Increase the descrambler timeout. When set this should allow the device to
receive larger packets (>9k bytes) without loss of synchronization.
1 = 2ms.
0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).
RESERVED: Writes ignored, read as 0.
RESERVED:Must be zero.
6
RESERVED
0
5
FORCE_100_OK
0, RW
RESERVED: Must be zero.
4
RESERVED
0
RESERVED:Must be zero.
3
RESERVED
0
RESERVED:Must be zero.
2
NRZI_BYPASS
0, RW
NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1
RESERVED
0
RESERVED:Must be zero.
0
RESERVED
0
RESERVED:Must be zero.
Force 100 Mb/s Good Link:
1 = Forces 100 Mb/s Good Link.
0 = Normal 100 Mb/s operation.
13.2.5 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
TABLE 25. RMII and Bypass Register (RBR), addresses 0x17h
Bit
Bit Name
Default
15:6
RESERVED
0, RO
5
RMII_MODE
Strap, RW
4
RMII_REV1_0
0, RW
Description
RESERVED: Writes ignored, read as 0.
Reduced MII Mode:
0 = Standard MII Mode.
1 = Reduced MII Mode.
Reduced MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate
deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
CRS_DV will not toggle at the end of a packet.
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DP83848Q
Bit
Bit Name
Default
Description
3
RX_OVF_STS
0, RO
RX FIFO Over Flow Status:
0 = Normal.
1 = Overflow detected.
2
RX_UNF_STS
0, RO
RX FIFO Under Flow Status:
0 = Normal.
1 = Underflow detected.
1:0
ELAST_BUF[1:0]
01, RW
Receive Elasticity Buffer:
This field controls the Receive Elasticity Buffer which allows for frequency
variation tolerance between the 50 MHz RMII clock and the recovered data. The
following values indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accuracy for both
RMII and Receive clocks. For greater frequency tolerance the packet lengths may
be scaled (i.e. for +/-100ppm, the packet lenths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2bit tolerance (up to 2400 byte packets)
10 = 6bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
13.2.6 LED Direct Control Register (LEDCR)
This register provides the ability to directly control the LED output. It does not provide read access to the LED.
TABLE 26. LED Direct Control Register (LEDCR), address 0x18h
Bit
Bit Name
Default
Description
15:5
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
4
DRV_LNKLED
0, RW
1 = Drive value of LNKLED bit onto LED_LINK output.
0 = Normal operation.
3:2
RESERVED
0, RO
RESERVED: Writes ignored, read as 0. Value to force on LED_LINK output.
1
LNKLED
0, RW
Value to force on LED_LINK output.
0
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
13.2.7 PHY Control Register (PHYCR)
This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause
Negotiation status.
TABLE 27. PHY Control Register (PHYCR), address 0x19h
Bit
Bit Name
Default
Description
15
MDIX_EN
Strap, RW
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit
in the BMCR register to be set. If Auto-Negotiation is not enabled, AutoMDIX should be disabled as well.
14
FORCE_MDIX
0, RW
Force MDIX:
1 = Force MDI pairs to cross.
(Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation.
13
PAUSE_RX
0, RO
Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based on
ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest
Common Denominator is a full duplex technology.
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46
Bit Name
Default
Description
12
PAUSE_TX
0, RO
Pause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based on
ANAR[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B
Table 28B-3, Pause Resolution, only if the Auto-Negotiated Highest
Common Denominator is a full duplex technology.
11
BIST_FE
0, RW/SC
10
PSR_15
0, RW
9
BIST_STATUS
0, LL/RO
8
BIST_START
0, RW
BIST Start:
1 = BIST start.
0 = BIST stop.
7
BP_STRETCH
0, RW
Bypass LED Stretching:
This will bypass the LED stretching and the LED will reflect the internal
value.
1 = Bypass LED stretching.
0 = Normal operation.
6
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
5
LED_CFG
Strap, RW
BIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the
CDCTRL1 register.
LED Configuration
LED_CFG
Mode Description
1
Mode 1
0
Mode 2
In Mode 1, LED is configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
In Mode 2, LED is configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
4:0
PHYADDR[4:0]
Strap, RW
PHY Address: PHY address for port.
13.2.8 10 Base-T Status/Control Register (10BTSCR)
This register is used for control and status for 10BASE-T device operation.
TABLE 28. 10Base-T Status/Control Register (10BTSCR), address 1Ah
Bit
Bit Name
Default
15:12
RESERVED
0, RW
11:9
SQUELCH
100, RW
Description
RESERVED: Must be zero.
Squelch Configuration:
Used to set the Squelch ON threshold for the receiver.
Default Squelch ON is 330mV peak.
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DP83848Q
Bit
DP83848Q
Bit
Bit Name
Default
Description
8
LOOPBACK_10_DIS
0, RW
10Base-T Loopback Disable:
In half-duplex mode, default 10BASE-T operation loops Transmit data to the
Receive data in addition to transmitting the data on the physical medium. This
is for consistency with earlier 10BASE2 and 10BASE5 implementations which
used a shared medium. Setting this bit disables the loopback function.
This bit does not affect loopback due to setting BMCR[14].
7
LP_DIS
0, RW
Normal Link Pulse Disable:
1 = Transmission of NLPs is disabled.
0 = Transmission of NLPs is enabled.
6
FORCE_LINK_10
0, RW
Force 10Mb Good Link:
1 = Forced Good 10Mb Link.
0 = Normal Link Status.
5
RESERVED
0, RW
RESERVED: Must be zero.
4
POLARITY
RO/LH
10Mb Polarity Status:
This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be
cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS
register.
1 = Inverted Polarity detected.
0 = Correct Polarity detected.
3
RESERVED
0, RW
RESERVED: Must be zero.
2
RESERVED
1, RW
RESERVED: Must be set to one.
1
HEARTBEAT_DIS
0, RW
Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode.
1 = Heartbeat function disabled.
0 = Heartbeat function enabled.
When the device is operating at 100Mb or configured for full duplex
operation, this bit will be ignored - the heartbeat function is disabled.
0
JABBER_DIS
0, RW
Jabber Disable:
Applicable only in 10BASE-T.
1 = Jabber function disabled.
0 = Jabber function enabled.
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This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the
packet BIST function.
TABLE 29. CD Test and BIST Extensions Register (CDCTRL1), address 0x1Bh
Bit
Bit Name
Default
Description
15:8
BIST_ERROR_COUNT
0, RO
BIST ERROR Counter:
Counts number of errored data nibbles during Packet BIST. This value
will reset when Packet BIST is restarted. The counter sticks when it
reaches its max count.
7:6
RESERVED
0, RW
RESERVED: Must be zero.
5
BIST_CONT_MODE
0, RW
Packet BIST Continuous Mode:
Allows continuous pseudo random data transmission without any break
in transmission. This can be used for transmit VOD testing. This is used
in conjunction with the BIST controls in the PHYCR Register (19h). For
10Mb operation, jabber function must be disabled, bit 0 of the
10BTSCR (1Ah), JABBER_DIS = 1.
4
CDPATTEN_10
0, RW
CD Pattern Enable for 10Mb:
1 = Enabled.
0 = Disabled.
3
RESERVED
0, RW
RESERVED: Must be zero.
2
10MEG_PATT_GAP
0, RW
Defines gap between data or NLP test sequences:
1 = 15 µs.
0 = 10 µs.
1:0
CDPATTSEL[1:0]
00, RW
CD Pattern Select[1:0]:
If CDPATTEN_10 = 1:
00 = Data, EOP0 sequence.
01 = Data, EOP1 sequence.
10 = NLPs.
11 = Constant Manchester 1s (10 MHz sine wave) for harmonic
distortion testing.
13.2.10 Energy Detect Control (EDCR)
This register provides control and status for the Energy Detect function.
TABLE 30. Energy Detect Control (EDCR), address 0x1Dh
Bit
Bit Name
Default
15
ED_EN
0, RW
Energy Detect Enable:
Allow Energy Detect Mode.
When Energy Detect is enabled and Auto-Negotiation is disabled via
the BMCR register, Auto-MDIX should be disabled via the PHYCR
register.
Description
14
ED_AUTO_UP
1, RW
Energy Detect Automatic Power Up:
Automatically begin power up sequence when Energy Detect Data
Threshold value (EDCR[3:0]) is reached. Alternatively, device could be
powered up manually using the ED_MAN bit (ECDR[12]).
13
ED_AUTO_DOWN
1, RW
Energy Detect Automatic Power Down:
Automatically begin power down sequence when no energy is detected.
Alternatively, device could be powered down using the ED_MAN bit
(EDCR[12]).
12
ED_MAN
0, RW/SC
Energy Detect Manual Power Up/Down:
Begin power up/down sequence when this bit is asserted. When set,
the Energy Detect algorithm will initiate a change of Energy Detect state
regardless of threshold (error or data) and timer values.
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DP83848Q
13.2.9 CD Test and BIST Extensions Register (CDCTRL1)
DP83848Q
Bit
Bit Name
Default
Description
11
ED_BURST_DIS
0, RW
Energy Detect Burst Disable:
Disable bursting of energy detect data pulses. By default, Energy Detect
(ED) transmits a burst of 4 ED data pulses each time the CD is powered
up. When bursting is disabled, only a single ED data pulse will be send
each time the CD is powered up.
10
ED_PWR_STATE
0, RO
Energy Detect Power State:
Indicates current Energy Detect Power state. When set, Energy Detect
is in the powered up state. When cleared, Energy Detect is in the
powered down state. This bit is invalid when Energy Detect is not
enabled.
9
ED_ERR_MET
0, RO/COR
Energy Detect Error Threshold Met:
No action is automatically taken upon receipt of error events. This bit is
informational only and would be cleared on a read.
8
ED_DATA_MET
0, RO/COR
Energy Detect Data Threshold Met:
The number of data events that occurred met or surpassed the Energy
Detect Data Threshold. This bit is cleared on a read.
7:4
ED_ERR_COUNT
0001, RW
Energy Detect Error Threshold:
Threshold to determine the number of energy detect error events that
should cause the device to take action. Intended to allow averaging of
noise that may be on the line. Counter will reset after approximately 2
seconds without any energy detect data events.
3:0
ED_DATA_COUNT
0001, RW
Energy Detect Data Threshold:
Threshold to determine the number of energy detect events that should
cause the device to take actions. Intended to allow averaging of noise
that may be on the line. Counter will reset after approximately 2 seconds
without any energy detect data events.
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50
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Storage Temperature (TSTG )
Maximum Case
Temperature for TA = 105 °C
-0.5 V to 4.2 V
-0.5V to VCC + 0.5V
-0.5V to VCC + 0.5V
-65 °C to 150 °C
115 °C
150 °C
260 °C
4.0 kV
Recommended Operating Conditions
Supply voltage (VCC)
Ambient Temperature (TA)
Power Dissipation (PD)
3.3 Volts ± 0.3V
-40 to 105 °C
267 mW
15.0 AC and DC Specifications
Note: All parameters are guaranteed by test, statistical analysis or design.
Theta Junction to Case (Tjc)
Thermal Characteristic
Max
8.8
Units
°C / W
Theta Junction to Ambient (Tja) degrees Celsius/Watt - No Airflow @ 1.0W
31.7
°C / W
15.1 DC SPECIFICATIONS
Symbol
Pin
Types
Parameter
VIH
I,
I/O
Input High Voltage
VIL
I,
I/O
Input Low Voltage
IIH
I,
I/O
Input High Current
IIL
I,
I/O
VOL
Conditions
Nominal VCC
Min
Typ
Max
2.0
Units
V
0.8
V
VIN = VCC
10
µA
Input Low Current
VIN = GND
10
µA
O,
I/O
Output Low
Voltage
IOL = 4 mA
0.4
V
VOH
O,
I/O
Output High
Voltage
IOH = -4 mA
IOZ
I/O,
TRI-STATE
VOUT = VCC
Leakage
VOUT = GND
O
VTPTD_100
PMD
100M Transmit Voltage
Output Pair
VTPTDsym
PMD
100M Transmit Voltage
Output Pair Symmetry
VTPTD_10
PMD
10M Transmit Voltage
Output Pair
VCC - 0.5
0.95
2.2
V
1
2.5
±10
µA
1.05
V
±2
%
2.8
V
CIN1
I
CMOS Input
Capacitance
5
pF
COUT1
O
CMOS Output
Capacitance
5
pF
SDTHon
PMD Input 100BASE-TX
Pair
Signal detect turn-on threshold
SDTHoff
PMD Input 100BASE-TX
Pair
Signal detect turn-off threshold
VTH1
PMD Input 10BASE-T Receive Threshold
Pair
1000
200
mV diff pk-pk
585
51
mV diff pk-pk
mV
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DP83848Q
Maximum Die Temperature
(Tj)
Lead Temp. (TL)
(Soldering, 10 sec.)
ESD Rating
(RZAP = 1.5k, CZAP = 100 pF)
14.0 Absolute Maximum Ratings (Note
DP83848Q
Symbol
Pin
Types
Parameter
Conditions
Min
Typ
Max
Units
Idd100
Supply
100BASE-TX
(Full Duplex)
81
mA
Idd10
Supply
10BASE-T
(Full Duplex)
92
mA
Idd
Supply
Power Down Mode
14
mA
CLK2MAC disabled
Note 2: Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
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DP83848Q
15.2 AC SPECIFICATIONS
15.2.1 Power Up Timing
30152520
Parameter
Description
Notes
Min
Typ
Max
Units
T2.1.1
Post Power Up Stabilization time
prior to MDC preamble for register
accesses
MDIO is pulled high for 32-bit serial
management initialization
X1 Clock must be stable for a min.
of 167ms at power up.
167
ms
T2.1.2
Hardware Configuration Latch-in
Time from power up
Hardware Configuration Pins are
described in the Pin Description
section.
X1 Clock must be stable for a min.
of 167ms at power up.
167
ms
T2.1.3
Hardware Configuration pins
transition to output drivers
50
ns
Note: In RMII Mode, the minimum Post Power up Stabilization and Hardware Configuration Latch-in times are 84ms.
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DP83848Q
15.2.2 Reset Timing
30152521
Parameter
Description
Notes
Min
Typ
Max
Units
T2.2.1
Post RESET Stabilization time prior to MDIO is pulled high for 32-bit serial
MDC preamble for register accesses management initialization
3
µs
T2.2.2
Hardware Configuration Latch-in Time Hardware Configuration Pins are
from the Deassertion of RESET (either described in the Pin Description
soft or hard)
section
3
µs
T2.2.3
Hardware Configuration pins transition
to output drivers
50
ns
T2.2.4
RESET pulse width
X1 Clock must be stable for at min.
of 1us during RESET pulse low
time.
1
µs
Note: It is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast RC time constants in order to latchin the proper value prior to the pin transitioning to an output driver.
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DP83848Q
15.2.3 MII Serial Management Timing
30152522
Parameter
Description
Notes
Min
Typ
Max
Units
30
ns
T2.3.1
MDC to MDIO (Output) Delay Time
0
T2.3.2
MDIO (Input) to MDC Setup Time
10
ns
T2.3.3
MDIO (Input) to MDC Hold Time
10
ns
T2.3.4
MDC Frequency
2.5
25
MHz
15.2.4 100 Mb/s MII Transmit Timing
30152523
Parameter
Description
Notes
Min
Typ
Max
Units
20
24
ns
T2.4.1
TX_CLK High/Low Time
100 Mb/s Normal mode
16
T2.4.2
TXD[3:0], TX_EN Data Setup to
TX_CLK
100 Mb/s Normal mode
10
ns
T2.4.3
TXD[3:0], TX_EN Data Hold from
TX_CLK
100 Mb/s Normal mode
0
ns
55
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DP83848Q
15.2.5 100 Mb/s MII Receive Timing
30152524
Min
Typ
Max
Units
T2.5.1
Parameter
RX_CLK High/Low Time
Description
100 Mb/s Normal mode
Notes
16
20
24
ns
T2.5.2
RX_CLK to RXD[3:0], RX_DV, RX_ER 100 Mb/s Normal mode
Delay
10
30
ns
Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will
not be violated.
15.2.6 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing
30152525
Parameter
T2.6.1
Description
TX_CLK to PMD Output Pair Latency
Notes
100BASE-TX and 100BASE-FX modes
Min
Typ
6
Max
Units
bits
Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit
of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
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DP83848Q
15.2.7 100BASE-TX Transmit Packet Deassertion Timing
30152526
Parameter
T2.7.1
Description
Notes
Min
TX_CLK to PMD Output Pair Deassertion 100BASE-TX and 100BASE-FX modes
Typ
Max
5
Units
bits
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T”
code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
15.2.8 100BASE-TX Transmit Timing (tR/F & Jitter)
30152527
Parameter
T2.8.1
T2.8.2
Description
Notes
Min
Typ
Max
Units
3
4
5
ns
100 Mb/s tR and tF Mismatch
500
ps
100 Mb/s PMD Output Pair Transmit Jitter
1.4
ns
100 Mb/s PMD Output Pair tR and tF
Note: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
Note: Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude
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DP83848Q
15.2.9 100BASE-TX Receive Packet Latency Timing
30152528
Parameter
Description
Notes
Min
Typ
Max
Units
T2.9.1
Carrier Sense ON Delay
100 Mb/s Normal mode
20
bits
T2.9.2
Receive Data Latency
100 Mb/s Normal mode
24
bits
Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
Note: 1 bit time = 10 ns in 100 Mb/s mode.
Note: PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
15.2.10 100BASE-TX Receive Packet Deassertion Timing
30152529
Parameter
T2.10.1
Description
Carrier Sense OFF Delay
Notes
100 Mb/s Normal mode
Min
Typ
Max
24
Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
Note: 1 bit time = 10 ns in 100 Mb/s mode.
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58
Units
bits
DP83848Q
15.2.11 10 Mb/s MII Transmit Timing
30152530
Parameter
Description
Notes
Min
Typ
Max
Units
200
210
ns
T2.11.1
TX_CLK High/Low Time
10 Mb/s MII mode
190
T2.11.2
TXD[3:0], TX_EN Data Setup to
TX_CLK fall
10 Mb/s MII mode
25
ns
T2.11.3
TXD[3:0], TX_EN Data Hold from
TX_CLK rise
10 Mb/s MII mode
0
ns
Note: An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on the falling edge
of TX_CLK.
15.2.12 10 Mb/s MII Receive Timing
30152531
Parameter
Description
Notes
Min
Typ
Max
Units
160
200
240
ns
T2.12.1
RX_CLK High/Low Time
T2.12.2
RX_CLK TO RXD[3:0}, RX_DV Delay
10 Mb/s MII mode
100
ns
T2.12.3
RX_CLK rising edge delay from RXD[3:0], RX_DV 10 Mb/s MII mode
Valid
100
ns
Note: RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be
violated.
59
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DP83848Q
15.2.13 10 Mb/s Serial Mode Transmit Timing
30152532
Parameter
Description
Notes
Min
Typ
Max
Units
T2.13.1
TX_CLK High Time
10 Mb/s Serial mode
20
25
30
ns
T2.13.2
TX_CLK Low Time
10 Mb/s Serial mode
70
75
80
ns
T2.13.3
TXD_0, TX_EN Data Setup to
TX_CLK rise
10 Mb/s Serial mode
25
ns
T2.13.4
TXD_0, TX_EN Data Hold from
TX_CLK rise
10 Mb/s Serial mode
0
ns
15.2.14 10 Mb/s Serial Mode Receive Timing
30152533
Parameter
Description
Notes
Min
Typ
Max
Units
50
65
ns
10
ns
T2.14.1
RX_CLK High/Low Time
35
T2.14.2
RX_CLK fall to RXD_0, RX_DV Delay 10 Mb/s Serial mode
-10
Note: RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be
violated.
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60
DP83848Q
15.2.15 10BASE-T Transmit Timing (Start of Packet)
30152534
Parameter
Description
Notes
Min
Typ
Max
Units
T2.15.1
Transmit Output Delay from the
Falling Edge of TX_CLK
10 Mb/s MII mode
3.5
bits
T2.15.2
Transmit Output Delay from the
Rising Edge of TX_CLK
10 Mb/s Serial mode
3.5
bits
Note: 1 bit time = 100 ns in 10 Mb/s.
15.2.16 10BASE-T Transmit Timing (End of Packet)
30152535
Min
Typ
T2.16.1
Parameter
End of Packet High Time
(with '0' ending bit)
Description
Notes
250
300
ns
T2.16.2
End of Packet High Time
(with '1' ending bit)
250
300
ns
61
Max
Units
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DP83848Q
15.2.17 10BASE-T Receive Timing (Start of Packet)
30152536
Parameter
Description
T2.17.1
Carrier Sense Turn On Delay (PMD
Input Pair to CRS)
T2.17.2
RX_DV Latency
T2.17.3
Receive Data Latency
Notes
Min
Typ
Max
Units
630
1000
ns
Measurement shown from SFD
10
bits
8
bits
Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on the wire to the assertion of RX_DV
Note: 1 bit time = 100 ns in 10 Mb/s mode.
15.2.18 10BASE-T Receive Timing (End of Packet)
30152537
Parameter
T2.18.1
Description
Notes
Carrier Sense Turn Off Delay
www.national.com
62
Min
Typ
Max
Units
1
µs
DP83848Q
15.2.19 10 Mb/s Heartbeat Timing
30152538
Parameter
Description
Notes
Min
Typ
Max
Units
T2.19.1
CD Heartbeat Delay
10 Mb/s half-duplex mode
1200
ns
T2.19.2
CD Heartbeat Duration
10 Mb/s half-duplex mode
1000
ns
15.2.20 10 Mb/s Jabber Timing
30152539
Parameter
Description
Notes
Min
Typ
Max
Units
T2.20.1
Jabber Activation Time
85
ms
T2.20.2
Jabber Deactivation Time
500
ms
63
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DP83848Q
15.2.21 10BASE-T Normal Link Pulse Timing
30152540
Parameter
Description
Notes
Min
Typ
Max
Units
T2.21.1
Pulse Width
100
ns
T2.21.2
Pulse Period
16
ms
Note: These specifications represent transmit timings.
15.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing
30152541
Parameter
Description
Notes
Min
Typ
Max
Units
T2.22.1
Clock, Data Pulse Width
100
ns
T2.22.2
Clock Pulse to Clock Pulse
Period
125
µs
T2.22.3
Clock Pulse to Data Pulse
Period
62
µs
T2.22.4
Burst Width
2
ms
T2.22.5
FLP Burst to FLP Burst Period
16
ms
Data = 1
Note: These specifications represent transmit timings.
www.national.com
64
DP83848Q
15.2.23 100BASE-TX Signal Detect Timing
30152542
Max
Units
T2.23.1
Parameter
SD Internal Turn-on Time
Description
Notes
Min
Typ
1
ms
T2.23.2
SD Internal Turn-off Time
350
µs
Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
15.2.24 100 Mb/s Internal Loopback Timing
30152543
Parameter
T2.24.1
Description
TX_EN to RX_DV Loopback
Notes
100 Mb/s internal loopback mode
Min
Typ
Max
Units
240
ns
Note: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data
will be present at the receive MII outputs. The 100BASE-TX timing specified is based on device delays after the initial 550µs “dead-time”.
Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
65
www.national.com
DP83848Q
15.2.25 10 Mb/s Internal Loopback Timing
30152544
Parameter
T2.25.1
Description
TX_EN to RX_DV Loopback
Notes
10 Mb/s internal loopback mode
Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
www.national.com
66
Min
Typ
Max
Units
2
µs
DP83848Q
15.2.26 RMII Transmit Timing
30152545
Parameter
Description
T2.26.1
X1 Clock Period
T2.26.2
TXD[1:0], TX_EN, Data Setup to X1 rising
T2.26.3
TXD[1:0], TX_EN, Data Hold from X1 rising
T2.26.4
X1 Clock to PMD Output Pair Latency
Notes
Min
50 MHz Reference Clock
Typ
20
4
67
Units
ns
ns
2
From X1 Rising edge to first bit of
symbol
Max
ns
17
bits
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DP83848Q
15.2.27 RMII Receive Timing
30152546
Parameter
Description
Notes
Min
50 MHz Reference Clock
Typ
Max
20
Units
T2.27.1
X1 Clock Period
T2.27.2
RXD[1:0], CRS_DV, RX_DV and
RX_ER output delay from X1 rising
T2.27.3
CRS ON delay (100Mb)
From JK symbol on PMD
Receive Pair to initial assertion of
CRS_DV
18.5
bits
T2.27.4
CRS OFF delay (100Mb)
From TR symbol on PMD
Receive Pair to initial deassertion
of CRS_DV
27
bits
T2.27.5
RXD[1:0] and RX_ER latency
(100Mb)
From symbol on Receive Pair.
Elasticity buffer set to default
value (01)
38
bits
2
ns
14
ns
Note: Per the RMII Specification, output delays assume a 25pF load.
Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle synchronously at the end of the
packet to indicate CRS deassertion.
Note: RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
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68
DP83848Q
15.2.28 Isolation Timing
30152549
Max
Units
T2.28.1
Parameter
From software clear of bit 10 in the
BMCR register to the transition from
Isolate to Normal mode
Description
Notes
Min
Typ
100
µs
T2.28.2
From Deassertion of S/W or H/W
Reset to transition from Isolate to
Normal mode
500
µs
15.2.29 25 MHz_OUT Timing
30152550
Parameter
T2.29.1
T2.29.2
Description
25 MHz_OUT High/Low Time
25 MHz_OUT propagation delay
Notes
Min
Typ
MII mode
20
RMII mode
10
Relative to X1
Max
Units
ns
ns
8
ns
Note: 25 MHz_OUT characteristics are dependent upon the X1 input characteristics.
69
www.national.com
DP83848Q
15.2.30 100 Mb/s X1 to TX_CLK Timing
30152552
Parameter
T2.30.1
Description
X1 to TX_CLK delay
Notes
100 Mb/s Normal mode
Min
Typ
0
Note: X1 to TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data.
www.national.com
70
Max
Units
5
ns
DP83848Q
16.0 Physical Dimensions inches (millimeters) unless otherwise noted
40–Lead LLP Plastic Quad Package (LLP)
NS Package Number SQA40A
17.0 Ordering Information
Order Number
Package Marking
Supplied As
DP83848QSQE/NOPB
DP83848QSQ
Reel of 250
DP83848QSQ/NOPB
DP83848QSQ
Reel of 1000
DP83848QSQX/NOPB
DP83848QSQ
Reel of 2500
71
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DP83848Q PHYTER Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer
Transceiver
Notes
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