ADS1202 SBAS275B – DECEMBER 2002 – REVISED JULY 2004 Motor Control Current Shunt 1-Bit, 10MHz, 2nd-Order, Delta-Sigma Modulator FEATURES DESCRIPTION ● 16-BIT RESOLUTION The ADS1202 is a precision, 80dB dynamic range, deltasigma (∆Σ) modulator operating from a single +5V supply. The differential inputs are ideal for direct connections to transducers or low-level signals. With the appropriate digital filter and modulator rate, the device can be used to achieve 16-bit Analog-to-Digital (A/D) conversion with no missing codes. Effective resolution of 12 bits can be maintained with a digital filter bandwidth of 10kHz at a modulator rate of 10MHz. The ADS1202 is designed for use in medium resolution measurement applications including current measurements, smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. It is available in a TSSOP-8 package. ● 13-BIT LINEARITY ● RESOLUTION/SPEED TRADE-OFF: 10-Bit Effective Resolution with 20µs Signal Delay (12-bit with 77µs) ● ±250mV INPUT RANGE WITH SINGLE 5V SUPPLY ● 2% INTERNAL REFERENCE VOLTAGE ● 2% GAIN ERROR ● FLEXIBLE SERIAL INTERFACE WITH FOUR DIFFERENT MODES ● IMPLEMENTED TWINNED BINARY CODING AS SPLIT PHASE OR MANCHESTER CODING FOR ONE LINE INTERFACING ● OPERATING TEMPERATURE RANGE: –40°C to +85°C APPLICATIONS ● MOTOR CONTROL ● CURRENT MEASUREMENT VIN+ VIN– MDAT 2nd-Order ∆∑ Modulator MCLK ● INDUSTRIAL PROCESS CONTROL ● INSTRUMENTATION ● SMART TRANSMITTERS ● PORTABLE INSTRUMENTS RC Oscillator 20MHz VDD M0 M1 GND Buffer ● WEIGHT SCALES Interface Circuit Reference Voltage 2.5V ● PRESSURE TRANSDUCERS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2002-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature (unless otherwise noted)(1) Supply Voltage, GND to VDD ................................................. –0.3V to 6V Analog Input Voltage Range ......................... GND – 0.4V to VDD + 0.3V Digital Input Voltage Range .......................... GND – 0.3V to VDD + 0.3V Power Dissipation ............................................................................ 0.25W Operating Virtual Junction Temperature Range, TJ ........ –40°C to +150°C Operating Free-Air Temperature Range, TA .................... –40°C to +85°C Storage Temperature Range, TSTG ................................ –65°C to +150°C Lead Temperature 1.6mm (1/16") from Case for 10s .................. +260°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses beyond those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) ADS1202 ADS1202 SPECIFIED MAXIMUM PACKAGE TEMPERATURE GAIN ERROR (%) PACKAGE-LEAD DESIGNATOR(1) RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS1202IPWT ADS1202IPWR Tape and Reel, 250 Tape and Reel, 2000 12 ±2 TSSOP-8 PW –40°C to +85°C ADS1202I " " " " " " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN DESCRIPTIONS PIN CONFIGURATION Top View TSSOP M0 1 8 VDD VIN+ 2 7 MCLK PIN NUMBER NAME 1 M0 Mode Input 2 VIN+ Analog Input: Noninverting Input 3 VIN– Analog Input: Inverting Input 4 M1 5 GND Power Supply Ground 6 MDAT Modulator Data Output 7 MCLK Modulator Clock Input or Output 8 VDD ADS1202 VIN– 3 6 MDAT M1 4 5 GND DESCRIPTION Mode Input Power Supply, +5V Nominal RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM MAX UNIT Supply Voltage, VDD Analog Input Voltage, VIN Operating Common-Mode Signal, VCM External Clock(1) Operating Junction Temperature Range 4.75 –250 0 16 –40 5.0 5.25 +250 5 24 105 V mV V MHz °C 20 NOTE: (1) With reduced accuracy, minimum clock can go up to 500kHz. DISSIPATION RATING PACKAGE TSSOP-8 TA < 25°C POWER RATING 483.6mW EQUIVALENT INPUT CIRCUIT DERATING FACTOR ABOVE TA = 25°C(1) 3.868mW/°C TA = 70°C POWER RATING 309.5mW TA = 85°C POWER RATING 251.4mW NOTE: (1) This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA). Thermal resistances are not production tested and are for informational purposes only. VDD VDD RON = 350Ω C(SAMPLE) = 5pF AIN DIN GND GND Diode Turn on Voltage: 0.35V Equivalent Analog Input Circuit 2 Equivalent Digital Input Circuit ADS1202 www.ti.com SBAS275B ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at –40°C to +85°C, VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. ADS1202IPW PARAMETER CONDITIONS MIN RESOLUTION DC ACCURACY Integral Nonlinearity(2) Differential Linearity(3) Input Offset(4) Input Offset Drift Gain Error(4) Gain Error Drift Power-Supply Rejection Ratio ANALOG INPUT Full-Scale Range Operating Common-Mode Signal(3) Input Capacitance Input Leakage Current Differential Input Resistance Differential Input Capacitance Common-Mode Rejection Ratio INTERNAL VOLTAGE REFERENCE Reference Voltage Accuracy(4) Reference Temperature Drift PSRR Startup Time TYP(1) MAX 16 Bits INL ±3 0.005 DNL VOS TCVOS GERR TCGERR PSRR ±300 2 ±0.25 20 80 4.75V < VDD < 5.25V FSR +In – (–In) –0.1 Common-Mode 3 Equivalent 28 5 90 85 ±12 0.018 ±1 ±1000 8 ±2 LSB % LSB µV µV/°C % ppm/°C dB ±320 5 mV V pF nA kΩ pF dB dB ±1 CMRR At DC VIN = ±1.25Vp-p at 50kHz VOUT Scale to 320mV Scale to 320mV 2.450 2.5 ±20 80 0.1 dVOUT/dT UNITS 2.550 ±2 V % ppm/°C dB ms INTERNAL CLOCK FOR MODES, 0, 1, AND 2 Clock Frequency 8 10 12 MHz EXTERNAL CLOCK FOR MODE 3 Clock Frequency 16 20 24 MHz AC ACCURACY Signal-to-Noise Ratio + Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range SINAD SNR THD SFDR DIGITAL INPUT Logic Family High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Input Capacitance VIH VIL IIH IIL CJ DIGITAL OUTPUT High-Level Digital Output VOH Low-Level Digital Output VOL Output Capacitance Load Capacitance POWER SUPPLY Supply Voltage Operating Supply Current Power Dissipation VIN VIN VIN VIN = = = = ±250mVp-p ±250mVp-p ±250mVp-p ±250mVp-p at at at at 5kHz 5kHz 5kHz 5kHz VI = VDD VI = GND VDD = 4.5V, IO = –5mA VDD = 4.5V, IO = –15mA VDD = 4.5V, IO = 5mA VDD = 4.5V, IO = 15mA 67 70 70.5 –84 84 dB dB dB dB TTL with Schmitt Trigger 2.6 VDD + 0.3 –0.3 0.8 0.005 2.5 –2.5 0.005 5 4.6 3.9 30 V V V V pF pF 5.5 9.5 7.5 47.5 37.5 V mA mA mW mW +85 °C 0.4 1.1 CO CL 5 VDD ICC 4.5 VDD VDD Mode 0 Mode 3 = 5V, Mode 0 = 5V, Mode 3 OPERATING TEMPERATURE –40 5 8 6 40 30 V V µA µA pF NOTES: (1) All typical values are at TA = +25°C. (2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the transfer curve for VIN+ = –250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV). (3) Ensured by design. (4) Maximum values, including temperature drift, are ensured over the full specified temperature range. ADS1202 SBAS275B www.ti.com 3 TIMING DIAGRAMS tC1 MCLK tW1 tD1 MDAT DIAGRAM 1: Mode 0 Operation. tC2 MCLK tD2 tW2 tD3 MDAT DIAGRAM 2: Mode 1 Operation. tC1 MCLK tw1 tC3 MDAT tw3 1 0 1 1 0 0 DIAGRAM 3: Mode 2 Operation. 4 ADS1202 www.ti.com SBAS275B TIMING DIAGRAMS (Cont.) tC4 MCLK tw4 tD4 MDAT DIAGRAM 4: Mode 3 Operation. TIMING CHARACTERISTICS over recommended operating free-air temperature range –40°C to +85°C, VDD = 5V, and MCLK = 10MHz, unless otherwise noted. SPEC MODE MIN MAX UNITS tC1 Clock Period DESCRIPTION 0 83 125 ns tW1 Clock HIGH Time 0 tC1/2 – 5 tC1/2 + 5 ns tD1 Data delay after falling edge of clock 0 –2 2 ns tC2 Clock Period 1 166 250 ns tW2 Clock HIGH Time 1 tC2/2 – 5 tC2/2 + 5 ns tD2 Data delay after rising edge of clock 1 –2 2 ns tD3 Data delay after falling edge of clock 1 –2 2 ns tC3 Clock Period 2 83 125 ns tW3 Clock HIGH Time 2 tC3/2 – 5 tC3/2 + 5 ns tC4 Clock Period 3 41 62 ns tW4 Clock HIGH Time 3 10 tC4 – 10 ns tD4 Data delay after falling edge of clock 3 0 10 ns tR1 Rise Time of Clock 3 0 10 ns t F1 Fall Time of Clock 3 0 10 ns NOTE: All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagrams 1 thru 4. ADS1202 SBAS275B www.ti.com 5 TYPICAL CHARACTERISTICS VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 3) INTEGRAL NONLINEARITY vs INPUT SIGNAL (Mode 0) 2 2 1 1 0 –2 INL (LSB) INL (LSB) 0 25°C –1 –40°C –3 +85°C –4 –1 25°C +85°C –2 –3 –40°C –5 –4 –6 –7 –320 –240 –160 –80 0 80 160 Differential Input Voltage (mV) 240 –5 –320 320 INTEGRAL NONLINEARITY vs TEMPERATURE –240 –160 –80 0 80 160 Differential Input Voltage (mV) 240 320 INTEGRAL NONLINEARITY vs TEMPERATURE 7 0.010 0.009 6 0.008 4 3 Mode 0 0.007 Mode 0 INL (%) INL (LSB) 5 Mode 3 0.006 0.005 0.004 Mode 3 0.003 2 0.002 1 0.001 0 0 –40 –20 0 20 40 Temperature (°C) 60 80 100 –40 –20 0 OFFSET vs TEMPERATURE 20 40 Temperature (°C) 60 80 100 80 100 GAIN vs TEMPERATURE 300 0.14 Mode 3 200 0.12 100 0.10 Gain (%) Offset (µV) 0 –100 –200 Mode 3 –300 –400 0.08 0.06 0.04 –500 Mode 0 –600 0 –700 –40 6 Mode 0 0.02 –20 0 20 40 Temperature (°C) 60 80 100 –40 –20 0 20 40 Temperature (°C) 60 ADS1202 www.ti.com SBAS275B TYPICAL CHARACTERISTICS (Cont.) VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. RMS NOISE vs INPUT VOLTAGE LEVEL SIGNAL-TO-NOISE RATIO vs TEMPERATURE 80 71.0 70 70.8 70.6 60 70.4 50 SNR (dB) RMS Noise (µV) Mode 0 40 30 Mode 3 70.2 70.0 69.8 69.6 20 69.4 10 69.2 0 –320 69.0 –240 –160 –80 0 80 160 Differential Input Voltage (mV) 240 320 –40 –20 SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE 0 60 80 100 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 71.0 16 14 70.6 Mode 3 Sinc3 Filter 12 70.2 ENOB SINAD (dB) 20 40 Temperature (°C) Mode 0 69.8 Sinc2 Filter 10 8 69.4 6 69.0 4 –20 0 20 40 Temperature (°C) 60 80 100 10 10000 SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 3) SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (Mode 0) –95 93 –93 91 –91 91 89 –89 89 87 –87 85 –85 SFDR (dB) 95 –93 0.5Vp-p 5kHz 93 THD (dB) –95 95 SFDR (dB) 100 1000 Decimation Ratio (OSR) –91 SFDR –89 87 –87 THD 85 –85 83 –83 –81 81 –81 –79 79 –79 77 –77 77 –77 75 –75 75 83 –83 SFDR 81 THD 79 –40 –20 0 20 40 Temperature (°C) 60 80 ADS1202 SBAS275B –75 –40 100 www.ti.com –20 0 20 40 Temperature (°C) 60 80 100 7 THD (dB) –40 TYPICAL CHARACTERISTICS (Cont.) VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 0) SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (Mode 3) 110 SFDR –100 100 –90 70 SFDR (dB) –80 –70 OSR = 256 Sinc3 Filter 60 –100 90 THD (dB) THD 80 –110 SFDR 90 SFDR (dB) 110 50 1 –90 THD 80 –80 70 –60 60 –50 50 10 –70 OSR = 256 Sinc3 Filter –60 –50 1 10 Input Frequency (kHz) Input Frequency (kHz) FREQUENCY SPECTRUM (4096 Point FFT, fIN = 1kHz, 0.5Vp-p) FREQUENCY SPECTRUM (4096 Point FFT, fIN = 5kHz, 0.5Vp-p) 0 0 Mode 0 –20 –20 –40 –40 Magnitude (dB) Magnitude (dB) Mode 0 –60 –80 –60 –80 –100 –100 –120 –120 –140 –140 0 2 4 6 8 10 12 Frequency (kHz) 14 16 18 20 0 2 4 6 8 10 12 Frequency (kHz) 14 16 18 20 COMMON-MODE REJECTION RATIO vs FREQUENCY CLOCK FREQUENCY vs TEMPERATURE 10.5 100 95 10.2 90 CMRR (dB) MCLK (MHz) 85 9.9 9.6 80 75 70 65 9.3 60 55 9.0 50 –40 8 –20 0 20 40 60 Temperature (°C) 80 100 120 1 10 Frequency of Power Supply (kHz) 100 ADS1202 www.ti.com SBAS275B THD (dB) 100 –110 TYPICAL CHARACTERISTICS (Cont.) VDD = 5V, +In = –250mV to 250mV, –In = 0V, and MCLK = 10MHz, unless otherwise noted. POWER-SUPPLY REJECTION RATIO vs FREQUENCY HISTOGRAM OF OUTPUT DATA 2000 85 1800 Number of Occurrences 90 75 70 65 60 1600 1400 1200 1000 800 600 400 55 200 50 –626 –687 –748 –809 –870 –931 100k –1114 1k 10k Frequency of Power Supply (Hz) –992 0 100 –1053 PSRR (dB) 80 ppm of FS MCLK AND MDAT TYPICAL SINK CURRENT POWER-SUPPLY CURRENT vs TEMPERATURE 70 10 5.5V 9 60 8 Output Current IOL (mA) Mode 0 Current (mA) 7 6 Mode 3 5 4 3 2 50 5V 40 4.5V 30 20 10 1 0 0 –40 –20 0 20 40 Temperature (°C) 60 80 0 100 1 2 3 4 Output Voltage VOL (V) 5 6 MCLK AND MDAT TYPICAL SOURCE CURRENT 80 Output Current IOH (mA) 70 5.5V 60 5V 50 40 30 20 4.5V 10 0 0 1 2 3 4 Output Voltage VOH (V) ADS1202 SBAS275B www.ti.com 5 6 9 GENERAL DESCRIPTION THEORY OF OPERATION The ADS1202 is a single-channel, 2nd-order, CMOS analog modulator designed for medium- to high-resolution conversions from dc to 39kHz with an oversampling ratio (OSR) of 256. The output of the converter (MDAT) provides a stream of digital ones and zeros. The time average of this serial output is proportional to the analog input voltage. The combination of an ADS1202 and a Digital Signal Processor (DSP) that is programmed to implement a digital filter results in a medium-resolution A/D converter system. This system allows flexibility with the digital filter design and is capable of A/D conversion results that have a dynamic range exceeding 85dB with OSR = 256. The differential analog input of the ADS1202 is implemented with a switched capacitor circuit. This switched capacitor circuit implements a 2nd-order modulator stage, which digitizes the input signal into a 1-bit output stream. The sample clock (MCLK) provides the switched capacitor network and modulator clock signal for the A/D conversion process, as well as the output data-framing clock. The clock source can be internal as well as external. Different frequencies for this clock allow for a variety of solutions and signal bandwidths (however, this can only be utilized in mode 3). The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream, which accurately represents the analog input voltage over time, appears at the output of the converter. +5V +5V VDDO M 0.1µF ADS1202 10nF 27Ω 27Ω 0.1µF 0.1µF DSP VDD M0 VIN+ MCLK SPICLK VIN– MDAT SPISIMO M1 GND VSSO FIGURE 1. Connection Diagram for the ADS1202 Delta-Sigma Modulator Including DSP. 10 ADS1202 www.ti.com SBAS275B ANALOG INPUT STAGE the linearity of the device is ensured only when the analog voltage applied to either input resides within the range defined by –320mV and +320mV. Analog Input The input design topology of the ADS1202 is based on a fully differential switched-capacitor architecture. This input stage provides the mechanism to achieve low system noise, high common-mode rejection (90dB), and excellent power-supply rejection. The input impedance of the analog input is dependent on the input capacitor and modulator clock frequency (MCLK), which is also the sampling frequency of the modulator. Figure 2 shows the basic input structure of the ADS1202. The relationship between the input impedance of the ADS1202 and the modulator clock frequency is: AIN (Ω) = 1012 7 • fMCLK (MHz) Modulator The modulator sampling frequency (CLK) can be operated over a range of a few MHz to 12MHz in mode 3. The frequency of MCLK can be decreased to adjust for the clock requirements of the application. The external MCLK must have double the modulator frequency. The modulator topology is fundamentally a 2nd-order, chargebalancing A/D converter, as the one conceptualized in Figure 3. The analog input voltage and the output of the 1-bit Digital-toAnalog Converter (DAC) are differentiated, providing an analog voltage at X2 and X3. The voltage at X2 and X3 are presented to their individual integrators. The output of these integrators progress in a negative or positive direction. When the value of the signal at X4 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative, depending on its original state. When the output value of the comparator switches from HIGH to LOW or vice versa, the 1-bit DAC responds on the next clock pulse by changing its analog output voltage at X6, causing the integrators to progress in the opposite direction. The feedback of the modulator to the front end of the integrators forces the value of the integrator output to track the average of the input. (1) The input impedance becomes a consideration in designs where the source impedance of the input signal is HIGH. In this case, it is possible for a portion of the signal to be lost across this external source impedance. The importance of this effect depends on the desired system performance. There are two restrictions on the analog input signal to the ADS1202. Under no conditions should the current into or out of the analog inputs exceed 10mA. The absolute input voltage range must stay in the range GND – 0.4V to VDD + 0.3V. If either of the inputs exceeds these limits, the input protection diodes on the front end of the converter will begin to turn on. In addition, RSW 350Ω (typ) High Impedance > 1GΩ AIN+ CINT 7pF (typ) 1.5pF Switching Frequency = CLK VCM 1.5pF CINT 7pF (typ) RSW 350Ω (typ) High Impedance > 1GΩ AIN– FIGURE 2. Input Impedance of the ADS1202. fCLK X(t) X2 Integrator 1 X3 Integrator 2 X4 DATA fS VREF Comparator X6 D/A Converter FIGURE 3. Block Diagram of the 2nd-Order Modulator. ADS1202 SBAS275B www.ti.com 11 DIGITAL OUTPUT The timing diagram for the ADS1202 data retrieval is shown in the Timing Diagrams. When an external clock is applied to MCLK, it is used as a system clock by the ADS1202, as well as a framing clock for data out (this procedure, however, can only be utilized in mode 3). The modulator output data, which is a serial stream, is available on the MDAT pin. Typically, MDAT is read on the falling edge of MCLK. An input differential signal of 0V will ideally produce a stream of ones and zeros that are HIGH 50% of the time and LOW 50% of the time. A differential input of 256mV will produce a stream of ones and zeros that are HIGH 80% of the time. A differential input of –256mV will produce a stream of ones and zeros that are HIGH 20% of the time. The input voltage versus the output modulator signal is shown in Figure 4. DIGITAL INTERFACE INTRODUCTION The analog signal that is connected to the input of the deltasigma modulator is converted using the clock signal (CLK) applied to the modulator. The result of the conversion, or modulation, is the output signal DATA from the delta-sigma modulator. In most applications where direct connection is realized between the delta-sigma modulator and the DSP or µC, two standard signals are provided. The MDAT and MCLK signals provide the easiest means of connection. If it is required to reduce the number of connection lines, having two signals is sometimes not an optimal solution. The receiver, DSP, or other control circuit must sample the output data signal from the modulator at the precise sampling instant. To do this, sampling a clock signal at the receiver is needed in order to synchronize with the clock signal at the transmitter. The delta-sigma modulator clock signal, receiver, filter, and clock must be synchronized. Three general methods can be used to obtain this synchronization. The first method has the delta-sigma modulator and the filter receive the clock signal from the master clock. The second method has the delta-sigma modulator transmit the clock signal together with the data signal. The third method has the filter derive the clock signal from the received waveform itself. An ideal solution is a delta-sigma modulator with a flexible interface, such as the ADS1202, which can provide flexible output format on the output lines MCLK and MDAT, thus covering different modes of operation. The signal type that can be provided is selected with control signals M0 and M1. FLEXIBLE DELTA-SIGMA INTERFACE Figure 5 illustrates the flexible interface of the ADS1202 delta-sigma converter. The control signals M0 and M1 are entered in the decoder that decodes the input code and selects the desired mode of operation. Five output signals from the decoder control the RC oscillator, multiplexer MUX1, multiplexer MUX2, multiplexer MUX3, and multiplexer MUX4. MUX1 is controlled by the decoder signal. When the internal RC oscillator is used, the control signal from the decoder enables the RC oscillator. At the same time, MUX1 uses the INTCLK signal as a source for the output signal from MUX1, which is entering the code generator. If the external clock is used, the control signal from the decoder disables the internal RC oscillator and the control signal from the decoder, and positions MUX1 so that EXTCLK provides the output signal from MUX1 as the input in the code generator. MUX2 selects the output clock, OCLK. The control signal coming from the decoder controls the output clock. Two signals come from the code generator as a half clock frequency, CLK/2, and as a quarter clock frequency, CLK/4, and provide MUX2 with the input signal. The control signal will select two different output modes on the OCLK signal as half clock or quarter clock. Modulator Output +FS (Analog Input) –FS (Analog Input) Analog Input FIGURE 4. Analog Input Versus Modulator Output of the ADS1201. 12 ADS1202 www.ti.com SBAS275B Interface Circuit M0 Decoder M1 RC Oscillator INTCLK MUX1 EXTCLK MUX4 MUX2 MCLK MUX3 Code Generator CLK/2 MDAT OCLK CLK/4 CLK DATA ∆∑ Modulator AIN FIGURE 5. Flexible Interface Block Diagram. The code generator receives the clock signal from MUX1 and generates the delta-sigma modulator clock (CLK) divided as half clock (CLK/2) and quarter clock (CLK/4). At the same time, the continuous data stream (DATA) coming from the delta-sigma modulator is elaborated by the Code Generator. Twinned binary coding (also known as split phase or Manchester coding) is implemented and then output from the code generator to MUX3. MUX3 selects the source of the output bit stream data, MDAT. The control signal coming from the decoder controls the input source of MDAT. Two signals are coming in to the MUX3, one directly from the delta-sigma modulator and the other from the code generator. The control signal from the decoder can select two different output modes on the signal MDAT: a bit stream from a delta-sigma modulator, or twinned binary coding of the same signal. The last control signal from the decoder controls MUX4. MUX2 selects the input or output clock, the MCLK signal. The control signal coming from the decoder controls the direction of the clock. One signal entering MUX4 from MUX2 comes as a clock signal OCLK. Another signal leaves MUX4 and provides an input to MUX1 as an external clock, EXTCLK. The control signal from the decoder can select two different modes on MCLK, one as an output of the internal clock signal and another as the input for the external clock signal. As a function of two control signals (M0 and M1), the decoder circuit, using five control signals, will set multiplexers in order to obtain the desired mode of operation. DIFFERENT MODES OF OPERATION Figure 5 presents mode selectors (input signals M0 and M1) that enter the flexible interface circuit and decoder that decodes the input code, and select the desired mode of operation. With two control lines it is possible to select four different modes of operation mode 0, mode 1, mode 2, and mode 3, which are shown in Table I. MODE M1 MO 0 DEFINITION Internal Clock, Synchronous Data Output LOW LOW 1 Internal Clock, Synchronous Data Output, Half Output Clock Frequency LOW HIGH 2 Internal Clock, Manchester Coded Data Output HIGH LOW 3 External Clock, Synchronous Data Output HIGH HIGH TABLE I. Mode Definition and Description. ADS1202 SBAS275B www.ti.com 13 Mode 0 Mode 1 In mode 0 both input signals, M0 and M1, are LOW. The control signal coming from the decoder enables the internal RC oscillator that provides the clock signal INTCLK as an input to MUX1. The control signal coming from the decoder also positions MUX1 so that the output signal, which is an input signal for the code generator, is INTCLK. Another control signal from the decoder circuit positions MUX3 so that the source for the output signal MDAT is the signal arriving directly from the delta-sigma modulator, DATA. MUX2 is positioned for the mode controlled by the signal coming from the decoder so output signal OCLK is CLK/2. The signal timings for mode 0 operation are presented in Figure 6. In this mode, the DSP or µC read MDAT data on every rising edge of the MCLK output clock. In mode 1, the input signal M0 is HIGH and M1 is LOW (see Table I). The first control signal coming from the decoder enables the internal RC oscillator that provides clock signal INTCLK as an input to MUX1. The second control signal coming from the decoder positions MUX1 so that the output signal that is the input signal to the code generator is INTCLK. The output signal from the delta-sigma modulator, DATA, is also the MDAT signal coming from the modulator because the control signal from the decoder positions MUX3 for that operation. MUX2 is positioned for the mode controlled by the control signal coming from the decoder with an OCLK of CLK/2. Output clock signal MCLK comes through MUX4 from MUX2 as OCLK or CLK/2. The signal timings for mode 1 operation are presented in Figure 7. In this mode, the DSP or µC read data on every edge, rising and falling, of the output clock. CLK DATA MCLK MDAT FIGURE 6. Signal Timing in Mode 0. CLK DATA MCLK MDAT FIGURE 7. Signal Timing in Mode 1. 14 ADS1202 www.ti.com SBAS275B Mode 2 Mode 3 In mode 2, M0 is low and M1 is HIGH (see Table I). The control signal coming from the decoder enables the internal RC oscillator that provides the clock signal INTCLK as an input to MUX1. Another control signal coming from the decoder positions MUX1 so that the output signal that is the input signal to the code generator is INTCLK. The output signal MDAT comes from the code generator because the control signal from the decoder positions MUX3 for that operation. The DATA signal coming from the delta-sigma modulator enters the code generator, where it combines with the clock signal, and twinned binary coding is implemented as split phase or Manchester coding, providing the output signal for MUX3. The MCLK output clock is not active, as multiplexers MUX2 and MUX4 are positioned for this mode controlled by the control signals coming from the decoder. The signals timings for mode 2 operation are presented in Figure 8. In this mode, the DSP or µC need to derive the clock signal from the received waveform itself. Different clock recovery networks can be implemented. Mode 3 is similar to mode 0; the only difference is that an external clock (EXTCLK) is provided. In mode 3, both input signals M0 and M1 are HIGH (see Table I). The control signal coming from the decoder disables the internal RC oscillator. The input signal EXTCLK provides the clock signal as an input to MUX1. The control signal coming from the decoder positions MUX1 so that the output signal that is the input signal to the code generator is EXTCLK. The output signal MDAT is the DATA signal coming directly from the delta-sigma modulator because the control signal from the decoder positions MUX3 for that operation. The signal timings for mode 3 operation are presented in Figure 9. In this mode, the DSP or µC read data on every falling edge of the input clock. CLK DATA MCLK MDAT FIGURE 8. Signal Timing in Mode 2. MCLK CLK DATA MDAT FIGURE 9. Signal Timing in Mode 3. ADS1202 SBAS275B www.ti.com 15 APPLICATIONS The DSP can be directly connected at the output of two channels of the optocoupler, C28x or C24x. In this configuration, the signals arriving at C28x or C24x are standard delta-sigma modulator signals and are connected directly to the SPICLK and SPISIMO pins. Being a delta-sigma converter, there is no need to have word sync on the serial data, so an SPI is ideal for connection. McBSP would work as well in SPI mode. Mode 0 operation in a typical application is shown in Figure 10. Measurement of the motor phase current is done via the shunt resistor. For better performance, both signals are filtered. R2 and C2 filter noise on the noninverting input signal, R3 and C3 filter noise on the inverting input signal, and C4 in combination with R2 and R3 filter the common-mode input noise. In this configuration, the shunt resistor is connected via three wires with the ADS1202. When component reduction is necessary, the ADS1202 can operate in mode 2, as shown in Figure 11. M1 is HIGH and M0 is LOW. Only the noninverting input signal is filtered. R2 and C2 filter noise on the input signal. The inverting input is directly connected to the GND pin, which is simultaneously connected to the shunt resistor. The power supply is taken from the upper gate driver power supply. A decoupling capacitor of 0.1µF is recommended for filtering the power supply. If better filtering is required, an additional 1µF to 10µF capacitor can be added. The control lines M0 and M1 are both LOW while the part is operating in mode 0. Two output signals, MCLK and MDAT, are connected directly to the optocoupler. The optocoupler can be connected to transfer a direct or inverse signal because the output stage has the capacity to source and sink the same current. The discharge resistor is not needed in parallel with optocoupler diodes because the output driver has the capacity to keep the LED diode out of the charge. HV+ The output signal from the ADS1202 is Manchester coded. In this case, only one signal is transmitted. For that reason, one optocoupler channel is used instead of two channels, as in the previous example of Figure 10. Another advantage of this configuration is that the DSP will use only one line per channel instead of two. That permits the use of smaller DSP packages in the application. Floating Power Supply Gated Drive Circuit R1 R2 27Ω D1 5.1V R3 27Ω RSENSE C1 0.1µF ADS1202 C4 10nF C2 0.1µF C3 0.1µF M0 VDD VIN+ MCLK VIN– MDAT M1 R5 R4 Optocoupler C28x or C24x SPICLK SPISIMO GND Power Supply Gated Drive Circuit HV– FIGURE 10. Application Diagram in Mode 0. 16 ADS1202 www.ti.com SBAS275B HV+ Floating Power Supply Gated Drive Circuit R1 D1 5.1V R2 27Ω RSENSE C1 0.1µF ADS1202 M0 C2 0.1µF Power Supply R4 VIN+ MCLK VIN– MDAT M1 Optocoupler VDD C28x or C24x GND Gated Drive Circuit HV– FIGURE 11. Application Diagram in Mode 2. HV+ Floating Power Supply C28x or C24x Gate Drive Circuit CVDD ADS1202 R2 27Ω RSENSE – VDD M0 + C2 0.1µF C1 0.1µF VIN+ MCLK SPICLK VIN– MDAT SPISIMO M1 GND DVDD FIGURE 12. Application Diagram without Galvanical Isolation in Mode 0. ADS1202 SBAS275B www.ti.com 17 – C1 0.1µF MCLK MDAT GND M1 C5 0.1µF VDD M0 + – VIN+ VIN– ADS1202 R2 27Ω RSENSE VDD M0 + RSENSE C4 0.1µF ADS1202 R1 27Ω C2 0.1µF VIN+ MCLK VIN– MDAT GND M1 C28x or C24x CVDD M0 + RSENSE – C6 0.1µF ADS1202 R3 27Ω C3 0.1µF VDD SPICLK VIN+ MCLK SPISIMO VIN– MDAT SPISIMO GND SPISIMO M1 DVDD CLK FIGURE 13. Parallel Operation of ADS1202 in Mode 3. LAYOUT CONSIDERATIONS used to limit the input current. Experimentation may be the best way to determine the appropriate connection between the ADS1202 and different power supplies. POWER SUPPLIES The ADS1202 requires only one power supply (VDD). If there are separate analog and digital power supplies on the board, a good design approach is to have the ADS1202 connected to the analog power supply. Another possible approach to control the noise is the use of a resistor on the power supply. The connection can be made between the ADS1202 powersupply pins via a 10Ω resistor. The combination of this resistor and the decoupling capacitors between the powersupply pins on the ADS1202 provide some filtering. The analog supply that is used must be well regulated and generate low noise. For designs requiring higher resolution from the ADS1202, power-supply rejection will be a concern. The digital power supply has high-frequency noise that can be capacitively coupled into the analog portion of the ADS1202. This noise can originate from switching power supplies, microprocessors, or digital signal processors. Highfrequency noise will generally be rejected by the external digital filter at integer multiples of MCLK. Just below and above these frequencies, noise will alias back into the passband of the digital filter, affecting the conversion result. Inputs to the ADS1202, such as VIN+, VIN–, and MCLK should not be present before the power supply is on. Violating this condition could cause latch-up. If these signals are present before the supply is on, series resistors should be 18 GROUNDING Analog and digital sections of the design must be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. Do not join the ground planes, but connect the two with a moderate signal trace underneath the converter. For multiple converters, connect the two ground planes as close as possible to one central location for all of the converters. In some cases, experimentation may be required to find the best point to connect the two planes together. DECOUPLING Good decoupling practices must be used for the ADS1202 and for all components in the design. All decoupling capacitors, specifically the 0.1µF ceramic capacitors, must be placed as close as possible to the pin being decoupled. A 1µF and 10µF capacitor, in parallel with the 0.1µF ceramic capacitor, must be used to decouple VDD to GND. At least one 0.1µF ceramic capacitor must be used to decouple VDD to GND, as well as for the digital supply on each digital component. ADS1202 www.ti.com SBAS275B PACKAGE DRAWING PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 ADS1202 SBAS275B www.ti.com 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS1202IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AZ1202 ADS1202IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AZ1202 ADS1202IPWT ACTIVE TSSOP PW 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AZ1202 ADS1202IPWTG4 ACTIVE TSSOP PW 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AZ1202 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS1202IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 ADS1202IPWT TSSOP PW 8 250 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1202IPWR TSSOP PW 8 2000 340.5 338.1 20.6 ADS1202IPWT TSSOP PW 8 250 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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