Preliminary PL611-30 Programmable Quick Turn Clock T M PIN CONFIGURATION FEATURES • • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise (< 40ps Pk-Pk typical) Output frequency up to 375MHz CMOS. Supports differential CMOS output to produce PECL, LVDS inputs. Crystal inputs: o Fundamental crystal: 10MHz-30MHz o 3 RD overtone crystal: Up to 75MHz o Reference input: Up to 200MHz Accepts <1.0V reference signal input voltage One programmable I/O pin can be configured as Output Enable (OE), or Frequency Selection input (FSEL), or Reference clock. Single 3.3V ± 10% power supply Operating temperature range from -40°C to 85°C Available in 8-pin MSOP/SOIC, 6-pin SOT Green/ RoHS compliant packages. XIN/FIN 1 GND 2 CLK0 3 CLK1 4 PL611-30 • • • • 8 XOUT 7 CLK2, OE, FSEL 6 DNC 5 VDD SOP-8 MSOP-8 DESCRIPTION The PL611-30 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s Factory Programmable ‘Quick Turn Clock (QTC)’ family. PhaseLink’s PL611-30 product family can generate any output frequency up to 375 MHz from fundamental crystal input between 10 MHz - 30 MHz, or a 3rd overtone crystal of up to 75Mhz. The PL611-30 produces differential CMOS outputs to support PECL, LVDS, and CMOS inputs. BLOCK DIAGRAM XIN/FIN XOUT Xtal OSC FRef . R- counter Phase Detector Charge Pump Loop Filter M-counter ( 6 -bit) OE CLoad Programming Logic FSEL FVCO = F Ref. * (2 * M /R) VCO P-counter (5-bit) FOut = FVCO / (2 * P) Programmable Function /1, /2 CLK[0:1] CLK2 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1 Preliminary PL611-30 Programmable Quick Turn Clock T M KEY PROGRAMMING PARAMETERS CLK[ 0:2 ] Output Frequency Fout = FIN * M / (R * P) where M= 6 bit R= 1 P= 5 bit 1. CLK[0:1]= VCO / 2 * P 2. CLK[2]= FIN or FIN/2 Output Drive Strength Std: 10mA (default) High: 24mA Crystal Load Programmable Input/Output (pin #7) # of Register Banks +/- 200ppm One output pin can be tuning. configured as 1. CLK2 = FIN or FIN/2 2. FSEL - input 3. OE - input 2 Charge-Pump Current 4 levels of pump current setting PIN DESCRIPTION Name Pin # (M)SOP-8 Type Description XIN/FIN 1 I Crystal or Reference input pin GND 2 P GND connection CLK[0:1] 3,4 O Programmable Clock Output [note:CLK0=~CLK1] VDD 5 P VDD connection DNC 6 - Do No Connect This programmable I/O pin can be configured as CLK2 (FIN or FIN/2) output, or OE input, or Frequency Selection (FSEL) input pin. This pin has an internal 60K pull up resistor. CLK2, OE, FSEL 7 B State 0 1 (default) XOUT 8 O OE FSEL Tristate Select Bank ’0’ ROM CLK[0:1] Normal mode Select Bank ‘1’ ROM Crystal output pin 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2 Preliminary PL611-30 Programmable Quick Turn Clock T M ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD - 0.5 4.6 V Input Voltage Range VI - 0.5 V DD + 0.5 V Output Voltage Range VO - 0.5 V DD + 0.5 V Supply Voltage Range Data Retention @ 85º C 10 Years 240 °C -65 150 °C -40 +85 °C Soldering Temperature Storage Temperature TS Ambient Operating Temperature* Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. AC SPECIFICATIONS PARAMETERS MAX. UNITS 30 MHz 3 rd Overtone Crystal 75 MHz Settling Time At power-up (after VDD increases over 1.62V) 10 ms VDD Sensitivity Frequency vs. VDD+/-10% 2 ppm Crystal Input Frequency Output Rise Time Output Fall Time CONDITIONS Fundamental Crystal MIN. TYP. 10 -2 15pF Load, 10/90%VDD, Standard drive 2.5 3.5 ns 15pF Load, 10/90%VDD, High drive 1.0 1.5 ns 15pF Load, 90/10%VDD, Standard drive 2.5 3.5 ns 15pF Load, 90/10%VDD, High drive 1.0 1.5 ns 50 55 % 500 ps Duty Cycle At VDD/2 Max. output skew between same frequency clocks Equal loading (15 pF). Equal frequency & drive strength Period Jitter, peak-to-peak* (measured from 10,000 samples) With capacitive decoupling between VDD and GND. Operating only one output. 45 40 ps * Note: Jitter performance depends on the programming parameters. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 3 Preliminary PL611-30 Programmable Quick Turn Clock T M DC SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 15 mA 3.63 V 0.4 V Supply Current, Dynamic, with Loaded Outputs I DD Operating Voltage V DD Output Low Voltage V OL I OL = +4mA (Standard drive) Output High Voltage V OH I OH = -4mA (Standard drive) I OSD V OL = 0.4V, V OH = 2.4V (Standard drive) 10 mA I OHD V OL = 0.4V, V OH = 2.4V (High Drive) 24 mA ± 50 mA Output Current Short-circuit Current At 10MHz, load=15pF 2.25 V DD – 0.4 IS V CRYSTAL SPECIFICATIONS PARAMETERS SYMBOL MIN. Fundamental Crystal Resonator Frequency F XIN 10 3rd Overtone Crystal Resonator Frequency F XIN Crystal Loading Rating (The IC can be programmed for any value in this range.) C L (xtal) TYP. 5 Maximum Sustainable Drive Level Operating Drive Level MAX. UNITS 30 MHz 75 MHz 20 pF 500 µW µW 100 Crystal Shunt Capacitance C0 6 pF Effective Series Resistance, Fundamental, 10-30MHz RS 30 Ω ESR 100/70 Ω Effective Series Resistance, 3 rd Overtone, 50-65MHz, [CO< 4pF, C L =5pF/8pF] ESR 60/40 Ω Effective Series Resistance, 3 rd Overtone, 65-75MHz [CO< 4pF, C L =5pF/8pF ESR 45/30 Ω Effective Series Resistance, [CO< 4pF, C L =5pF/8pF] 3 rd Overtone, 30-50MHz Note: A detailed crystal specification document is also available for this part 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 4 Preliminary PL611-30 Programmable Quick Turn Clock T M Figure 1 below describes how to terminate the differential CMOS outputs of PhaseLink’s PL611-30 Programmable QTC clock for use with PECL or LVDS inputs. The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination scheme you can use the PL611-30 for all your LVDS and PECL clock requirements up to 375MHz. +3.3V CMOS Output R1 50Ω line R2 Input R3 Complementary CMOS Output R1 50Ω line 3.3V 0V R3 R2 +3.3V Complementary Input PECL LVDS 2.35V 1.40V 1.59V 1.10V Component selection For PECL input For LVDS input Notes: Place R1 as close to the CMOS outputs as possible. R1 = 130Ω R2 = 82Ω R3 = 130Ω Place R2 and R3 as close to the PECL/LVDS inputs as possible. R1 = 360Ω R2 = 82Ω R3 = 130Ω Figure 1 The above layout allows the PL611-30 to drive either a PECL or LVDS input by simply changing the value of R1. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 5 Preliminary PL611-30 Programmable Quick Turn Clock T M PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) MSOP 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. --1.10 0.05 0.15 0.81 0.91 0.25 0.40 0.13 0.23 2.90 3.10 2.90 3.10 4.90 BSC 0.445 0.648 0.65 BSC E H D A2 A A1 C e L b SOP 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e b L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 6 Preliminary PL611-30 Programmable Quick Turn Clock T M ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL611-XXX X X-R PART NUMBER 3 DIGIT ID Code * NONE= TUBE R=TAPE and REEL PACKAGE TYPE S=SOIC M=MSOP TEMPERATURE C=COMMERCIAL I = INDUSTRIAL * PhaseLink will assign a unique 3-digit ID code for each approved programmed part number. * PhaseLink offers Green Package Only for this product family. Part / Order Number PL611-30-XXXSC PL611-30-XXXSC-R PL611-30-XXXMC PL611-30-XXXMC-R Marking C3XXX C3XXX C3XXX C3XXX Package Option 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) 8-Pin MSOP (Tube) 8-Pin MSOP (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 7