(Preliminary) PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) FEATURES • • • • • • • • • 32 mil VCXO output for the 36MHz to 130MHz range Low phase noise (-148 dBc @ 10kHz offset at 77.76MHz). CMOS output with OE tri-state control. 36 to 130MHz fundamental crystal input. Integrated high linearity variable capacitors. 8mA drive capability at TTL output. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. Single 2.5V ±10% or 3.3V ±10 power supply. Operating temperature range from -40°C to +85°C Available in Die or Wafer form. (812,986) 8 1 XIN XOUT OE^ 7 2 39 mil • • PIN AND PAD CONFIGURATION OE^ VDD 6 3 VCON CLK 5 4 GND Y (0,0) X Note: ^ denotes pull-up resistor DIE SPECIFICATIONS DESCRIPTION The PLL500-37 is a low cost, high performance and low phase noise VCXO for the 36 to 130MHz range, providing less than -148dBc at 10kHz offset at 77.76MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 36 to 130MHz (fundamental resonant mode). Name Value Size 39 x 32 mil Reverse side Pad dimensions GND 80 micron x 80 micron Thickness 12 mil BLOCK DIAGRAM XIN XOUT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 1 (Preliminary) PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) PAD ASSIGNMENT AND DESCRIPTION Name Pad # XIN Die Pad Position X (µm) Y (µm) 1 94.2 768.6 2 94.2 605.0 OE Type Description I Crystal input pin. P Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. Use only one OE signal. 7 715.5 626.7 VCON 3 94.2 331.7 I Frequency control voltage input pin. GND 4 94.2 140.4 P Ground pin. CLK 5 715.5 203.9 O Output clock pin. VDD 6 715.5 455.7 P VDD power supply pin. XOUT 8 477.0 888.8 O Crystal output pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage SYMBOL MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature* TA -40 85 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C ESD Protection, Human Body Model 2 kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 2 (Preliminary) PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) 2. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. Input Crystal Frequency TYP. 36 Output Clock Rise/Fall Time Output Clock Duty Cycle 0.8V ~ 2.0V with 10 pF load 1.15 0.3V ~ 3.0V with 15 pF load 3.7 Measured @ 1.4V 45 50 MAX. UNITS 130 MHz ns 55 ±50 Short Circuit Current % mA 3. DC Specifications PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs I DD Allowable output load capacitance Operating Voltage Output Low Voltage at CMOS level Output High Voltage at CMOS level CONDITIONS MIN. F XIN = 77.76MHz Output load of 15pF CL (Output) UNITS 7.2 9 mA 15 pF 3.63 V 0.4 V 2.25 V OLC I OL = +4mA V OHC I OH = -4mA For V OL <0.4V or V OH >2.4V V DD – 0.4 V 8 mA ±50 Short Circuit Current VCXO Control Voltage MAX. Standard drive up to 100MHz V DD Output drive current TYP. VCON 0 mA V DD V 4. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VCXOSTB CONDITIONS MIN. From power valid VCXO Tuning Range F XIN = 36 – 130MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V CLK output pullability VCON=1.65V, ±1.65V UNITS 10 ms ppm ±150 ppm 100 Pull range linearity PWSRR Frequency change with VDD varied +/- 10% VCON pin input impedance VCON modulation BW MAX. 300 VCXO Tuning Characteristic Power Supply Rejection TYP. 0V ≤ VCON ≤ 3.3V, -3dB -1 ppm/V 5 % +1 ppm 2000 kΩ 45 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 3 (Preliminary) PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) 5. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating SYMBOL CONDITIONS MIN. F XIN TYP. 36 VCON = 1.65V C L (xtal) UNITS 130 MHz 5.0 Maximum Sustainable Drive Level pF 200 Operating Drive Level RS C0 ≤ 2.0pF, F XIN up to 85MHz C0 ≤ 2.5pF, F XIN up to 80MHz C0 ≤ 3.0pF, F XIN up to 75MHz C0 ≤ 2.0pF, F XIN up to 95MHz C0 ≤ 2.5pF, F XIN up to 90MHz C0 ≤ 3.0pF, F XIN up to 85MHz C0 ≤ 2.0pF, F XIN up to 110MHz C0 ≤ 2.5pF, F XIN up to 105MHz C0 ≤ 3.0pF, F XIN up to 100MHz C0 ≤ 2.0pF, F XIN up to 130MHz C0 ≤ 2.5pF, F XIN up to 120MHz C0 ≤ 3.0pF, F XIN up to 115MHz µW µW 50 C0/C1 ESR MAX. 250 - 30 Ω 25 Ω 20 Ω 15 Ω Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range and oscillator gain. 6. Jitter and Phase Noise Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS RMS Period Jitter (1 sigma – 1000 samples) With capacitive decoupling between VDD and GND. 2.5 ps Phase Noise relative to carrier 77.76MHz @10Hz offset -80 dBc/Hz Phase Noise relative to carrier 77.76MHz @100Hz offset -110 dBc/Hz Phase Noise relative to carrier 77.76MHz @1kHz offset -134 dBc/Hz Phase Noise relative to carrier 77.76MHz @10kHz offset -148 dBc/Hz Phase Noise relative to carrier 77.76MHz @100kHz offset -150 dBc/Hz Phase Noise relative to carrier 77.76MHz @1MHz offset -152 dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 4 (Preliminary) PLL500-37 Low Phase Noise VCXO (36MHz to 130MHz) ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL500-37 X X PART NUMBER PACKAGE TYPE W= Wafer D= DIE Part / Order Number PLL500-37WC PLL500-37DC TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Marking P500-37WC P500-37DC Package Option Wafer Die (Waffle Pack) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/01/06 Page 5