PO100HSTL32A Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator DESCRIPTION: FEATURES: • Patented Technology • Differential LVDS/LVPECL/HSTL to LVTTL Translator • Operating frequency up to 1GHz with 2pf load • Operating frequency up to 800MHz with 5pf load • Operating frequency up to 450MHz with 15pf load • Very low output pin to pin skew < 150ps • Propagation delay < 1.8ns max with 15pf load • 2.4V to 3.6V power supply • Industrial temperature range: –40°C to 85°C • Available in 16-pin SOIC 150ml package Pin Configuration 1B 1A 1Y G 2Y 2A 2B GND 04/19/09 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 Potato Semiconductor’s PO100HSTL32A is designed for world top performance using submicron CMOS technology to achieve 1GHz LVTTL output frequency with less than 1.8ns propagation delay. The PO100HSTL32A is a low-skew, The small outline 16 pin package and the low skew design to make it ideal for applica- tions which require the translation of a clock or a data signal. Logic Block Diagram VCC 4B 4A 4Y G 3Y 3A 3B G G 1A 1B 2A 2B Pin Description ENABLES 3A DIFFERENTIAL INPUT A, B G G OUTPUT Y VID ≥ 10 mV H X X L H H –10 mV < VID < 10 mV H X X L ? ? 4A VID ≤ –10 mV H X X L L L 4B X L H Z Open H X X L H H 3B 4 12 2 3 1Y 1 6 5 2Y 7 10 11 9 14 15 13 3Y 4Y 1 Copyright © Potato Semiconductor Corporation PO100HSTL32A 04/19/09 Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to Vcc V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLUP RPULLDOWN Test Conditions Minimum Typical Maximum Units 4 pF Input B Pullup Resistor 88 KΩ Input A Pulldown Resistor 88 KΩ DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = Vcc - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA -0.7 -1.2 - V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation PO100HSTL32A 04/19/09 Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 30 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Switching Characteristics Symbol Test Conditions (1) M ax Unit Propagation Delay D to Output pair CL = 15pF 1.8 ns tPZH or tPZL Output Enable Time CL = 15pF 2.5 ns tPHZ or tPLZ Output Disable Time CL = 15pF 2.5 ns 0.8V – 2.0V ns ps tPD tr/tf tsk(o) tsk(pp) Description Rise/Fall Time Output Pin to Pin Skew (Same Package) CL = 15pF, 125MHz 0.8 150 Output Skew (Different Package) CL = 15pF, 125MHz 300 ps MHz MHz fmax fmax Input Frequency CL =15pF Input Frequency CL = 5pF 450 250 800 300 fmax Input Frequency CL = 2pF 1000 400 MHz Notes: 1. See test circuits and waveforms. 2. tpLH, tpHL, tsk(p), and tsk(o) are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 133MHz Test Circuit Vcc 50Ω Pulse Generator V+ V+ V- V- 50Ω D.U.T 15pF to 2pF 3 Copyright © Potato Semiconductor Corporation PO100HSTL32A Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator 04/19/09 Test Waveforms FIGURE 1. LVDS/ PECL/ ECL/ HSTL /DIFFERENTIAL INPUT WAVEFORM DEFINITIONS VCC VCC= 3.3V VIH VPP VPP RANGE 0V-VCC VIL VEE=0.0V VEE FIGURE 2. LVTTL OUTPUT tr,tf, VO FIGURE 3. Propogation Delay, Output pulse skew, and output-to-output skew for D to output INPUT CLOCK VPP TPLH TPD TPHL OUTPUT CLOCK VO tSK(O) ANOTHER OUTPUT CLOCK 4 Copyright © Potato Semiconductor Corporation PO100HSTL32A 04/19/09 Quad Differential LVDS/LVPECL/HSTL to LVTTL Translator Packaging Mechanical Drawing: 16 pin SOIC 16 .149 .157 .2284 .2440 3.78 3.99 1 .0075 .0098 .386 .393 9.80 10.00 .016 .050 5.80 6.20 0.41 1.27 0.19 0.25 .0155 0.393 .0260 0.660 1.35 1.75 .053 .068 .050 BSC 1.27 .013 .020 0.330 0.508 .0040 .0098 0.10 0.25 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Ordering Code Package Top-Marking TA PO100HSTL32ASU 16-pin SOIC Tube Pb-free & Green PO100HSTL32AS -40°C to 85°C PO100HSTL32ASR 16-pin SOIC Tape and reel Pb-free & Green PO100HSTL32AS -40°C to 85°C IC Package Information PACKAGE CODE S PACKAGE TYPE SOIC 16 TAPE WIDTH (mm) 16 TAPE PITCH (mm) 8 PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE Top Left Corner 39 (12”) 3000 64 (20”) 48 5 Copyright © Potato Semiconductor Corporation