05109 PLC496 ULTRA LOW CAPACITANCE TVS ARRAY APPLICATIONS ✔ Sensor & Control Circuits ✔ FireWire ✔ Ethernet - 10/100/1000 Base T ✔ Handheld Electronics ✔ RF Applications IEC COMPATIBILITY (EN61000-4) ✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV ✔ 61000-4-4 (EFT): 40A - 5/50ns ✔ 61000-4-5 (Surge): 24A, 8/20µs - Level 2(Line-Ground) & Level 3(Line-Line) SO-8 FEATURES ✔ ✔ ✔ ✔ ✔ ✔ 500 Watts Peak Pulse Power per Line (tp = 8/20µs) Bidirectional Configuration ESD Protection > 40 kilovolts Low Clamping Voltage < 5 Volts Ultra Low Capacitance: 1.25pF RoHS Compliant MECHANICAL CHARACTERISTICS ✔ Molded JEDEC SO-8 ✔ Weight 70 milligrams (Approximate) ✔ Available in Lead-Free Pure-Tin Plating(Annealed) ✔ Solder Reflow Temperature: Pure-Tin - Sn, 100: 260-270°C ✔ Consult Factory for Leaded Device Availability ✔ Flammability Rating UL 94V-0 ✔ 12mm Tape and Reel Per EIA Standard 481 ✔ Marking: Logo, Marking Code, Date Code & Pin One Defined by Dot on Top of Package PIN CONFIGURATION 05109.R7 2/07 8 7 6 5 1 2 3 4 1 www.protekdevices.com PLC496 DEVICE CHARACTERISTICS MAXIMUM RATINGS @ 25°C Unless Otherwise Specified PARAMETER SYMBOL VALUE UNITS PPP 500 Watts TL -55 to 150 °C TSTG -55 to 150 °C Peak Pulse Power (tp = 8/20µs) - See Figure 1 Operating Temperature Storage Temperature ELECTRICAL CHARACTERISTICS PER LINE PART NUMBER PLC496 DEVICE MARKING CODE VEC @ 25°C Unless Otherwise Specified MINIMUM BREAKDOWN VOLTAGE (See Note 1) MAXIMUM REVERSE LEAKAGE CURRENT (See Note 1) MAXIMUM CLAMPING VOLTAGE (See Note 1) (See Fig. 2) WORKING INVERSE BLOCKING VOLTAGE (See Note 2) INVERSE BLOCKING LEAKAGE CURRENT (See Note 2) VWM VOLTS @1mA V(BR) VOLTS @VWM ID µA @8/20µs VC @ IPP VWIB VOLTS @VWIB IR µA @0V, 1MHz C pF 1.0 2.5 20 12.5V @ 30A 75 1.0 1.25 RATED STAND-OFF VOLTAGE MAXIMUM CAPACITANCE (See Note 3) Note 1: Apply positive voltage from pin 4 to 1 and pin 8 to 5. Note 2: Apply positive voltage from pin 1 to 4 and pin 5 to 8. Note 3: Capcitance from pin 1 to 4 < 1.25pF. Capacitance from pin 8 to 5 < 1.25pF. FIGURE 1 PEAK PULSE POWER VS PULSE TIME IPP - Peak Pulse Current - % of IPP PPP - Peak Pulse Current - Watts 10,000 500W, 8/20µs Waveform 1,000 100 10 0.01 05109.R7 2/07 FIGURE 2 PULSE WAVE FORM 120 tf 100 TEST WAVEFORM PARAMETERS tf = 8µs td = 20µs Peak Value IPP 80 e-t 60 40 td = t I /2 PP 20 0 1 10 100 td - Pulse Duration - µs 1,000 10,000 2 0 5 10 15 t - Time - µs 20 25 30 www.protekdevices.com PLC496 GRAPHS FIGURE 3 POWER DERATING CURVE 100 Peak Pulse Power 8/20µs % Of Rated Power 80 60 40 20 Average Power 0 0 25 50 75 100 125 TL - Lead Temperature - °C 150 FIGURE 4 OVERSHOOT & CLAMPING VOLTAGE FOR PLC496 5 Volts per Division 35 25 15 5 -5 ESD Test Pulse: 25 kilovolt, 1/30ns (waveshape) 05109.R7 2/07 3 www.protekdevices.com PLC496 APPLICATION NOTE The PLC496 is an ultra low capacitance, bidirectional array that is designed to protect I/O or high speed data lines from the damaging effects of ESD or EFT. This product has a surge capability of 500 Watts PPP per line for an 8/20µs waveshape and offers ESD protection > 40kV. DIFFERENTIAL-MODE CONFIGURATION (Figure 1) The PLC496 is designed to protect one bidirectional line where the normal signal voltage is both positive and negative. Figure 1 shows a typical differential-mode line to line) I/O port protection circuit application. Circuit connectivity is as follows: ✔ Pins 1, 4 5 and 8 are connected to the data lines ✔ Pins 2, 3, 7 and 6 are not connected. Figure 1. Typical Differential Mode I/O Port Protection LINE 1 IN LINE 1 OUT 1 8 NC 2 7 NC NC 3 6 NC 4 5 COMMON-MODE CONFIGURATION (Figure 2) The PLC496 can provide protection for sensor circuit applications. Figure 2, is a typical common-mode (line to ground) sensor circuit application. Circuit connectivity is as follows: ✔ Pins 1 and 8 connected to the dataline ✔ Pins 4 and 5 connected to ground ✔ Pins 2, 3, 6, and 7 are not connected CIRCUIT BOARD LAYOUT RECOMMENDATIONS Circuit board layout is critical for Electromagnetic Compatibility (EMC) protection. The following guidelines are recommended: ✔ The protection device should be placed near the input terminals or connectors, the device will divert the transient current immediately before it can be coupled into the nearby traces. ✔ The path length between the TVS device and the protected line should be minimized. ✔ All conductive loops including power and ground loops should be minimized. ✔ ✔ LINE 2 IN LINE 2 OUT Figure 2. Typical Common Mode Sensor Protection Circuit SENSOR 1 8 NC 2 7 NC NC 3 6 NC 4 5 1 8 NC 2 7 NC NC 3 6 NC 4 5 The transient current return path to ground should be kept as short as possible to reduce parasitic inductance. CIRCUITRY Ground planes should be used whenever possible. For multilayer PCBs, use ground vias. 05109.R7 2/07 4 www.protekdevices.com PLC496 SO-8 PACKAGE OUTLINE & DIMENSIONS PACKAGE OUTLINE SO-8 -A- 8 5 + 0.010 (0.25 MM) M B M 4 PL -B - P 1 G PACKAGE DIMENSIONS 4 DIM A B C D F G J K P R D C R x 45° 0° - 10° -T- K 0.010 (0.25 MM) M T B S A S 8 PL + J F MILLIMETERS MIN MAX 4.80 3.80 1.35 0.35 0.40 1.27 BSC 0.18 0.10 5.80 0.25 INCHES MIN MAX 0.196 5.00 0.189 0.150 0.157 4.00 1.75 0.054 0.068 0.49 0.014 0.019 0.049 1.250 0.016 1.27 BSC 0.05 BSC 0.05 BSC 0.25 0.007 0.009 0.004 0.008 0.25 6.20 0.229 0.244 0.019 0.50 0.010 NOTES 1. 2. 3. 4. 5. 6. MOUNTING PAD 0.050 ± 0.005 0.030 ± 0.005 - T - = Seating Plane and Datum Surface. Dimensions “A” and “B” are Datum. Dimensions “A” and “B” do not include mold protrusion. Maximum mold protrusion is 0.015” (0.380 mm) per side. Dimensioning and tolerances per ANSI Y14.5M, 1982. Dimensions are exclusive of mold flash and metal burrs. TAPE & REEL/BULK ORDERING NOMENCLATURE 0.160 ± 0.005 1. Surface mount product is taped and reeled in accordance with EIA-481. 2. Suffix-T7 = 7 Inch Reel - 1,000 pieces per 12mm tape, i.e. PLC496-T7.. 3. Suffix-T13 = 13 Inch Reel - 2,500 pieces per 12mm tape, i.e., PLC496-T13. 4. Suffix - LF = Lead-Free, Pure-Tin Plating, i.e., PLC496-LF-T7. 5. No Suffix = Product Shipped in Tubes of 98 pcs per Tube. 0.245 MIN 0.045 ± 0.005 Outline & Dimensions: Rev 1 - 11/01, 06009 COPYRIGHT © ProTek Devices 2007 SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC). DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is the buyer’s and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such products. 05109.R7 2/07 5 ProTek Devices 2929 South Fair Lane, Tempe, AZ 85282 Tel: 602-431-8101 Fax: 602-431-2288 E-Mail: [email protected] Web Site: www.protekdevices.com www.protekdevices.com