PCS3P73Z01BW May 2008 rev 0.2 Wide Frequency range Timing-Safe™ Peak EMI reduction IC General Features delivering a 1x Timing-Safe™ clock. PCS3P73Z01BW has • 1x , LVCMOS Timing-Safe™ Peak EMI Reduction • Input frequency: 12MHz - 150MHz @ 2.5V 15MHz - 175MHz @ 3.3V a Frequency Selection (FS) control that facilitates selecting one of the two frequency ranges within the operating frequency range. Refer to the frequency Selection table for details. The device has an SSEXTR pin to select different deviations and associated Input-Output Skew (TSKEW), • Output frequency ( Timing-Safe™): 12MHz - 150MHz @ 2.5V 15MHz - 175MHz @ 3.3V depending upon the value of an external resistor connected • Analog Spread Selection up to ±1% DLY_CTRL for adjusting the Input-Output clock delay, • External Input-Output Delay Control option depending upon the value of capacitor connected at this • Power Down option for Power Save mode pin to GND. PD#/OE provides the Power Down option. • Supply Voltage: 2.5V±0.2V Outputs will be tri-stated when power down is active. between SSEXTR and GND. PCS3P73Z01BW has a 3.3V ± 0.3V • • • Commercial temperature range PCS3P73Z01BW operates from a 2.5V/3.3V supply and is 8 pin, TSSOP, and TDFN(2X2) COL packages available in an 8 Pin TSSOP, and TDFN (2X2) COL The First True Drop-in Solution Packages, over Commercial temperature range. Functional Description Application PCS3P73Z01BW is a 2.5V/3.3V versatile EMI reduction IC based on PulseCore Semiconductor’s patent pending Timing-Safe™ technology. PCS3P73Z01BW accepts one input from an external reference, and locks on to it PCS3P73Z01BW is targeted for use in Displays, Camera modules and high speed SDRAM memory interface systems. Block Diagram DLY_CTRL CLKIN VDD SSEXTR PLL ModOUT (Timing-Safe™) PD#/OE GND FS PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS3P73Z01BW May 2008 rev 0.2 Pin Configuration 8 VDD 7 SSEXTR FS 3 6 DLY_CTRL GND 4 5 ModOUT CLKIN 1 PD#/OE 2 PCS3P73Z01BW Pin Description Pin # Type Pin Name 1 I CLKIN 2 I PD#/OE 3 I FS 4 P GND 5 O ModOUT 6 O DLY_CTRL 7 I SSEXTR 8 P VDD Description External reference Clock input. Power Down. Pull LOW to enable Power Down. Outputs will be tri-stated when power down is enabled. Pull HIGH to disable power down and enable output. Frequency Select (see Frequency Selection table for details). Ground Buffered modulated Timing-Safe™ clock output External Input-Output Delay control Analog Spread Selection through external resistor to GND. 2.5V / 3.3V supply Voltage Frequency Selection Table VDD 2.5V 3.3V FS Frequency(MHz) 0 12-40 1 40-150 0 15-50 1 50-175 Absolute Maximum Rating Symbol Rating Unit VDD Voltage on any pin with respect to Ground Parameter -0.5 to +4.6 V TSTG Storage temperature -65 to +125 °C °C Ts Max. Soldering Temperature (10 sec) 260 TJ Junction Temperature 150 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 2 of 16 PCS3P73Z01BW May 2008 rev 0.2 Operating Conditions Parameter Description Min Max Unit VDD(3.3V) Supply Voltage 3.0 3.6 V VDD(2.5V) Supply Voltage 2.3 2.7 V 0 TA Operating Temperature (Ambient Temperature) +70 °C CL Load Capacitance 10 pF CIN Input Capacitance 7 pF Electrical Characteristics for 2.5V Supply Parameter Description VDD Supply Voltage Test Conditions Min Typ Max Unit 2.3 2.5 2.7 V 0.7 V VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50 µA IIH Input HIGH Current VIN = VDD 50 µA VOL Output LOW Voltage IOL = 8mA 0.6 V VOH Output HIGH Voltage IOH = -8mA ICC Static Supply Current CLKIN & PD#/OE pins pulled to GND 1.7 1.8 Zo Dynamic Supply Current Unloaded Output V 2 12MHz IDD V µA 3 40MHz 7 150MHz 15 Output Impedance mA Ω 36 Electrical Characteristics for 3.3V Supply Parameter Description Test Conditions Min Typ Max Unit 3.3 3.6 V VDD Supply Voltage 3.0 VIH Input HIGH Voltage 2.0 VIL Input LOW Voltage IIH Input HIGH Current IIL V 0.8 V VIN = VDD 50 µA Input LOW Current VIN = 0V 50 µA VOH Output HIGH Voltage IOH = -8mA VOL Output LOW Voltage IOL =8mA ICC Static Supply Current CLKIN pulled Low, PD#/OE pulled Low IDD Zo Dynamic Supply Current Unloaded outputs 2.4 V 15MHz 5 50MHz 10 175MHz 25 Output Impedance Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 27 0.4 V 2 µA mA Ω 3 of 16 PCS3P73Z01BW May 2008 rev 0.2 Switching Characteristics for 2.5V Parameter Test Conditions Input Frequency ModOUT Min Typ Max FS=0 12 40 FS=1 40 150 FS=0 12 40 FS=1 40 150 ≤ 100MHz 45 50 55 ≥100MHz 40 50 60 Unit MHz Duty Cycle 1, 2 Measured at VDD /2 Rise Time 1, 2 Measured between 20% to 80% 1.7 nS Measured between 80% to 20% 0.9 nS Fall Time 1, 2 Cycle-to-Cycle Jitter2 Unloaded outputs Unloaded outputs with Input-to-Output propagation Delay 2 SSEXTR pin OPEN, No load on DLY_CTRL FS=0; @ 25 MHz ±175 FS=1; @ 66 MHz ±150 pS FS=0; @ 25 MHz 250 pS FS=1; @ 66 MHz Stable power supply, valid clock presented on PLL Lock Time 2 % CLKIN pin 3 mS Max Unit Notes: 1. All parameters are specified with 10 pF loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics for 3.3V Parameter Test Conditions Input Frequency ModOUT Min Typ FS=0 15 50 FS=1 50 175 FS=0 15 50 FS=1 50 175 ≤ 100MHz 45 50 55 ≥100MHz 40 50 60 MHz Duty Cycle 3,4 Measured at VDD /2 Rise Time 3,4 Measured between 20% to 80% 1.2 nS Measured between 80% to 20% 0.8 nS Fall Time 3,4 Cycle-to-CycleJjitter 4 Unloaded outputs Unloaded outputs with Input-to-Output propagation Delay 4 PLL Lock Time4 SSEXTR pin OPEN, No load on DLY_CTRL FS=0; @ 25 MHz ±150 FS=1; @ 66 MHz ±125 % pS FS=0; @ 25 MHz 350 pS FS=1; @ 66 MHz Stable power supply, valid clock presented on CLKIN pin 3 mS Notes: 3. All parameters are specified with 10 pF loaded outputs. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 4 of 16 PCS3P73Z01BW May 2008 rev 0.2 Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 OUTPUT All Outputs Rise/Fall Time 80% 80% 20% 3.3V 20% OUTPUT 0V t3 t4 Input - Output Propagation Delay VDD/2 INPUT VDD/2 OUTPUT t6 Input-Output Skew Input TSKEW - Timing-Safe™ Output TSKEW+ One clock cycle N=1 TSKEW represents input-output skew when spread spectrum is ON For example, TSKEW = ± 0.20 for an Input clock of 12MHz, translates in to (1/12MHz) * 0.20=16.66nS Note: Tskew is measured in units of Clock Period Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 5 of 16 PCS3P73Z01BW May 2008 rev 0.2 Typical example of Timing-Safe™ waveform Input Input ModOUT with SSOFF Timing-Safe™ ModOUT Typical Application Schematic VDD VDD CLKIN 1 CLKIN VDD 8 0Ω VDD 0Ω 2 PD#/OE 3 FS External Spread Control SSEXTR 7 0Ω 0Ω 0.01uF DLY_CTRL 6 External Input-Output Delay Control R C 4 GND ModOUT 5 SSEXTR can be Pulled HIGH to turn OFF SS Note: Refer to Pin Description table for Functionality details Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 6 of 16 PCS3P73Z01BW May 2008 rev 0.2 Charts (for VDD=2.5V±0.2V) Deviation Vs Resistance 0.8 Tskew Vs Resistance 0.25 12MHz 0.75 0.7 0.2 0.65 0.175 0.6 0.55 Tskew Deviation (+/-) 12MHz 0.225 0.5 0.45 0.15 0.125 0.1 0.075 0.4 0.35 0.05 0.3 0.025 0.25 100 200 300 400 500 600 700 0 100 800 200 300 Resistance (KOhms) 400 500 600 700 800 Resistance (KOhms) Fig1: Deviation Vs Resistance (12MHz, FS=0) Fig2: Tskew Vs Resistance (12MHz, FS=0) Charts (for VDD=2.5V±0.2V and 3.3V±0.3V) Deviation Vs Resistance 0.8 Tskew Vs Resistance 0.25 25MHz 0.75 0.7 0.2 0.65 0.175 0.6 0.55 Tskew Deviation (+/-) 25MHz 0.225 0.5 0.45 0.15 0.125 0.1 0.075 0.4 0.35 0.05 0.3 0.025 0.25 0 40 50 60 70 80 90 100 110 120 130 140 150 160 40 50 60 70 Resistance (KOhms) 80 90 100 110 120 130 140 150 160 Resistance (KOhms) Fig3: Deviation Vs Resistance (25MHz, FS=0) Fig4: Tskew Vs Resistance (25MHz, FS=0) Tskew Vs Resistance Deviation Vs Resistance 0.8 0.25 33MHz 0.75 0.2 0.7 0.175 Tskew 0.65 Deviation (+/-) 33MHz 0.225 0.6 0.55 0.5 0.15 0.125 0.1 0.075 0.45 0.05 0.4 0.35 0.025 0.3 0 30 0.25 30 40 50 60 70 80 90 100 110 120 130 140 150 40 50 60 70 80 90 100 110 120 130 140 150 Resistance (KOhms) Resistance (KOhms) Fig5: Deviation Vs Resistance (33MHz, FS=0) Fig6: Tskew Vs Resistance (33MHz, FS=0) Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 7 of 16 PCS3P73Z01BW May 2008 rev 0.2 Deviation Vs Resistance Tskew Vs Resistance 0.8 0.25 40MHz 0.75 0.7 0.2 0.65 0.175 0.6 0.55 Tskew Deviation (+/-) 40MHz 0.225 0.5 0.45 0.15 0.125 0.1 0.075 0.4 0.35 0.05 0.3 0.025 0.25 0 30 40 50 60 70 80 90 100 110 120 30 40 50 60 Resistance (KOhms) 70 80 90 100 Fig7: Deviation Vs Resistance (40MHz, FS=0) 120 Fig8: Tskew Vs Resistance (40MHz, FS=0) Deviation Vs Resistance Tskew Vs Resistance 0.25 0.25 66MHz 66MHz 0.225 0.2 0.2 0.175 Tskew Deviation (+/-) 110 Resistance (KOhms) 0.15 0.15 0.125 0.1 0.075 0.1 0.05 0.025 0.05 250 300 350 400 450 500 550 600 650 700 750 800 850 900 0 250 300 350 400 450 500 550 600 650 700 750 800 850 900 Resistance (KOhms) Resistance (KOhms) Fig10: Tskew Vs Resistance (66MHz, FS=1) Fig9: Deviation Vs Resistance (66MHz, FS=1) Deviation Vs Resistance Tskew Vs Resistance 0.3 0.25 75MHz 0.225 0.25 0.2 0.2 Tskew Deviation (+/-) 75MHz 0.15 0.175 0.15 0.1 0.05 150 0.125 180 210 240 270 300 330 Resistance (KOhms) Fig11: Deviation Vs Resistance (75MHz, FS=1) 0.1 150 180 210 240 270 300 330 Resistance (KOhms) Fig12: Tskew Vs Resistance (75MHz, FS=1) Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 8 of 16 PCS3P73Z01BW May 2008 rev 0.2 Deviation Vs Resistance Tskew Vs Resistance 0.3 0.25 100MHz 0.25 0.2 0.2 Tskew Deviation (+/-) 100MHz 0.225 0.15 0.175 0.15 0.1 0.125 0.05 120 150 180 210 240 270 0.1 120 300 150 180 Resistance (KOhms) 210 240 270 Fig13: Deviation Vs Resistance (100MHz, FS=1) Fig14: Tskew Vs Resistance (100MHz, FS=1) Deviation Vs Resistance Tskew Vs Resistance 0.3 0.25 133MHz 133MHz 0.225 0.25 0.2 0.175 0.2 Tskew Deviation (+/-) 300 Resistance (KOhms) 0.15 0.15 0.125 0.1 0.075 0.1 0.05 0.025 0.05 0 80 110 140 170 200 230 260 290 80 110 140 Resistance (KOhms) 170 200 230 260 Fig15: Deviation Vs Resistance (133MHz, FS=1) Fig16: Tskew Vs Resistance (133MHz, FS=1) Tskew Vs Resistance Deviation Vs Resistance 0.3 0.25 150MHz 150MHz 0.225 0.25 0.2 0.175 0.2 Tskew Deviation (+/-) 290 Resistance (KOhms) 0.15 0.15 0.125 0.1 0.075 0.1 0.05 0.025 0 0.05 60 90 120 150 180 210 240 270 Resistance (KOhms) Fig17: Deviation Vs Resistance (150MHz, FS=1) 60 90 120 150 180 210 240 270 Resistance (KOhms) Fig18: Tskew Vs Resistance (150MHz, FS=1) Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 9 of 16 PCS3P73Z01BW May 2008 rev 0.2 Charts (for VDD= 3.3V±0.3V) Tskew Vs Resistance Deviation Vs Resistance 0.25 0.3 166MHz 166MHz 0.225 0.2 0.25 0.2 Tskew Deviation (+/-) 0.175 0.15 0.15 0.125 0.1 0.075 0.05 0.1 0.025 0 0.05 50 60 70 80 50 90 100 110 120 130 140 150 160 170 180 60 70 80 90 100 110 120 130 140 150 160 170 180 Resistance (KOhms) Resistance (KOhms) Fig19: Deviation Vs Resistance (166MHz, FS=1) Fig20: Tskew Vs Resistance (166MHz, FS=1) Deviation Vs Resistance 0.3 Tskew Vs Resistance 0.25 175MHz 175MHz 0.225 0.25 0.2 Tskew Deviation (+/-) 0.175 0.2 0.15 0.15 0.125 0.1 0.075 0.1 0.05 0.025 0.05 0 40 50 60 70 80 90 100 110 120 130 140 150 160 Resistance (KOhms) Fig21: Deviation Vs Resistance (175MHz, FS=1) 40 50 60 70 80 90 100 110 120 130 140 150 160 Resistance (KOhms) Fig22: Tskew Vs Resistance (175MHz, FS=1) Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 10 of 16 PCS3P73Z01BW May 2008 rev 0.2 Charts (for VDD=2.5V±0.2V) I/O Delay Vs Load (DLY_CTRL) 800 800 2.3V 2.5V 600 2.3V 2.5V 600 2.7V 2.7V 400 3.3V 3.6V 200 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I/O Delay (nS) 3V 400 I/O Delay (nS) I/O Delay Vs Load (DLY_CTRL) -200 3V 3.3V 200 3.6V 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -200 -400 -400 -600 -600 -800 Capacitance (pF) Capacitance (pF) Fig23: I/O Delay Vs Load (DLY_CTRL) (For 12MHz, FS=0) Fig24: I/O Delay Vs Load (DLY_CTRL) (For 25MHz, FS=0) Charts (for VDD=2.5V±0.2V and 3.3V±0.3V) I/O Delay Vs Load (DLY_CTRL) I/O Delay Vs Load (DLY_CTRL) 800 800 2.5V 600 2.3V 2.5V 600 2.3V 2.7V 400 3V I/O Delay (nS) 400 3V 3.3V 200 3.6V 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 I/O Delay (nS) 2.7V 3.3V 200 3.6V 0 -200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -400 -200 -600 -400 -800 -600 -1000 Capacitance (pF) -800 Capacitance (pF) Fig26: I/O Delay Vs Load (DLY_CTRL) (For 40MHz, FS=0) Fig25: I/O Delay Vs Load (DLY_CTRL) (For 33MHz, FS=0) I/O Delay Vs Load (DLY_CTRL) 800 2.3V 2.5V 600 2.7V I/O Delay (nS) 400 3V 3.3V 200 3.6V 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -200 -400 -600 -800 Capacitance (pF) Fig27: I/O Delay Vs Load (DLY_CTRL) (For 66MHz, FS=1) Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 11 of 16 PCS3P73Z01BW May 2008 rev 0.2 I/O Delay Vs Load (DLY_CTRL) 800 2.5V 3.6V 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -400 I/O Delay (nS) 3.3V 2.5V 2.7V 400 3V 200 2.3V 600 2.7V 400 I/O Delay (nS) 800 2.3V 600 -200 I/O Delay Vs Load (DLY_CTRL) -600 3V 3.3V 200 3.6V 0 -200 0 1 2 3 4 5 8 9 10 11 12 13 14 15 -600 -800 -1000 -1000 Capacitance (pF) Capacitance (pF) Fig29: I/O Delay Vs Load (DLY_CTRL) (For 100MHz, FS=1) Fig28: I/O Delay Vs Load (DLY_CTRL) (For 75MHz, FS=1) I/O Delay Vs Load (DLY_CTRL) 800 I/O Delay Vs Load (DLY_CTRL) 800 2.3V 2.5V 600 3.6V 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -400 I/O Delay (nS) 3.3V 2.5V 2.7V 400 3V 200 2.3V 600 2.7V 400 I/O Delay (nS) 7 -400 -800 -200 6 -600 3V 3.3V 200 3.6V 0 -200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -400 -600 -800 -800 -1000 -1000 Capacitance (pF) Capacitance (pF) Fig31: I/O Delay Vs Load (DLY_CTRL) (For 150MHz, FS=1) Fig30: I/O Delay Vs Load (DLY_CTRL) (For 133MHz, FS=1) Charts (for VDD= 3.3V±0.3V) I/O Delay Vs Load (DLY_CTRL) 800 600 800 400 400 200 200 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -200 3V 3.3V 3.6V 600 I/O Delay (nS) I/O Delay (nS) I/O Delay Vs Load (DLY_CTRL) 3V 3.3V 3.6V 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -200 -400 -400 -600 -600 Capacitance (pF) Fig32: I/O Delay Vs Load (DLY_CTRL) (For 166MHz, FS=1) -800 Capacitance (pF) Fig33: I/O Delay Vs Load (DLY_CTRL) (For 175MHz, FS=1) Note: Device to Device variation of Deviation and I/O delay is ± 10% Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 12 of 16 PCS3P73Z01BW May 2008 rev 0.2 Package Information 8-lead TSSOP Package (4.40-MM Body) H E D A2 A C θ e A1 L B Dimensions Symbol Inches Min Millimeters Max A Min Max 0.043 1.10 A1 0.002 0.006 0.05 0.15 A2 0.033 0.037 0.85 0.95 B 0.008 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 D 0.114 0.122 2.90 3.10 E 0.169 0.177 4.30 4.50 e 0.026 BSC 0.65 BSC H 0.252 BSC 6.40 BSC L 0.020 0.028 0.50 0.70 θ 0° 8° 0° 8° Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 13 of 16 PCS3P73Z01BW May 2008 rev 0.2 TDFN COL 2x2 8L package Outline drawing Dimensions Symbol A A3 b Inches Min Max Millimeters Min Max 0.027 0.70 0.0315 0.008 BSC 0.008 0.012 0.80 0.203 BSC 0.20 0.30 D 0.079 BSC 2.00 BSC E 0.078 BSC 2.00 BSC e L 0.020 BSC 0.020 0.024 0.50 BSC 0.50 0.60 Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 14 of 16 PCS3P73Z01BW May 2008 rev 0.2 Ordering Codes Ordering Code Marking Package Type Temperature PCS3P73Z01BWG-08-TT 3P73Z01BWG 8-pin 4.4-mm TSSOP - TUBE, Green Commercial PCS3P73Z01BWG-08-TR 3P73Z01BWG 8- pin 4.4-mm TSSOP - TAPE & REEL, Green Commercial PCS3P73Z01BWG-08-CR AF1LL 8- pin 2-mm TDFN COL - TAPE & REEL, Green Commercial LL = 2 Character LOT # Device Ordering Information P C S 3 P 7 3 Z 0 1 B W G - 0 8 - T R R = Tape & Reel, T = Tube or Tray O = TSOT23 S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 J=TSOT26 C=TDFN (2X2) COL DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 15 of 16 PCS3P73Z01BW May 2008 rev 0.2 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS3P73Z01BW Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Many PulseCore Semiconductor products are protected by issued patents or by applications for patent © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Wide Frequency range Timing-Safe™ Peak EMI reduction IC Notice: The information in this document is subject to change without notice. 16 of 16